Revision fb0eaffc target-ppc/helper.c
| b/target-ppc/helper.c | ||
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| 121 | 121 |
} |
| 122 | 122 |
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| 123 | 123 |
/* The 32 MSB of the target fpr are undefined. They'll be zero... */ |
| 124 |
uint32_t do_load_fpscr (void) |
|
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/* Floating point operations helpers */ |
|
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void do_load_fpscr (void) |
|
| 125 | 126 |
{
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return (fpscr_fx << FPSCR_FX) | |
|
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(fpscr_fex << FPSCR_FEX) | |
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(fpscr_vx << FPSCR_VX) | |
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(fpscr_ox << FPSCR_OX) | |
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(fpscr_ux << FPSCR_UX) | |
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(fpscr_zx << FPSCR_ZX) | |
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(fpscr_xx << FPSCR_XX) | |
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(fpscr_vsxnan << FPSCR_VXSNAN) | |
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(fpscr_vxisi << FPSCR_VXISI) | |
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(fpscr_vxidi << FPSCR_VXIDI) | |
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(fpscr_vxzdz << FPSCR_VXZDZ) | |
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(fpscr_vximz << FPSCR_VXIMZ) | |
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(fpscr_fr << FPSCR_FR) | |
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(fpscr_fi << FPSCR_FI) | |
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(fpscr_fprf << FPSCR_FPRF) | |
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(fpscr_vxsoft << FPSCR_VXSOFT) | |
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(fpscr_vxsqrt << FPSCR_VXSQRT) | |
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(fpscr_oe << FPSCR_OE) | |
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(fpscr_ue << FPSCR_UE) | |
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(fpscr_ze << FPSCR_ZE) | |
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(fpscr_xe << FPSCR_XE) | |
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(fpscr_ni << FPSCR_NI) | |
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(fpscr_rn << FPSCR_RN); |
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/* The 32 MSB of the target fpr are undefined. |
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* They'll be zero... |
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*/ |
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union {
|
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double d; |
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struct {
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uint32_t u[2]; |
|
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} s; |
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} u; |
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int i; |
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|
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u.s.u[0] = 0; |
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u.s.u[1] = 0; |
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for (i = 0; i < 8; i++) |
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u.s.u[1] |= env->fpscr[i] << (4 * i); |
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FT0 = u.d; |
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| 149 | 143 |
} |
| 150 | 144 |
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/* We keep only 32 bits of input... */ |
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/* For now, this is COMPLETELY BUGGY ! */ |
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void do_store_fpscr (uint8_t mask, uint32_t fp) |
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void do_store_fpscr (uint32_t mask) |
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| 154 | 146 |
{
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/* |
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* We use only the 32 LSB of the incoming fpr |
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*/ |
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union {
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double d; |
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struct {
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uint32_t u[2]; |
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} s; |
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} u; |
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| 155 | 156 |
int i; |
| 156 | 157 |
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for (i = 0; i < 7; i++) {
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if ((mask & (1 << i)) == 0) |
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fp &= ~(0xf << (4 * i)); |
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u.d = FT0; |
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if (mask & 0x80) |
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env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[1] >> 28) & ~0x9); |
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for (i = 1; i < 7; i++) {
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if (mask & (1 << (7 - i))) |
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env->fpscr[i] = (u.s.u[1] >> (4 * (7 - i))) & 0xF; |
|
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} |
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/* TODO: update FEX & VX */ |
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/* Set rounding mode */ |
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switch (env->fpscr[0] & 0x3) {
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case 0: |
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/* Best approximation (round to nearest) */ |
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fesetround(FE_TONEAREST); |
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break; |
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case 1: |
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/* Smaller magnitude (round toward zero) */ |
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fesetround(FE_TOWARDZERO); |
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break; |
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case 2: |
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/* Round toward +infinite */ |
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fesetround(FE_UPWARD); |
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break; |
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case 3: |
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/* Round toward -infinite */ |
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fesetround(FE_DOWNWARD); |
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break; |
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| 160 | 184 |
} |
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if ((mask & 80) != 0) |
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fpscr_fx = (fp >> FPSCR_FX) & 0x01; |
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fpscr_fex = (fp >> FPSCR_FEX) & 0x01; |
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fpscr_vx = (fp >> FPSCR_VX) & 0x01; |
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fpscr_ox = (fp >> FPSCR_OX) & 0x01; |
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fpscr_ux = (fp >> FPSCR_UX) & 0x01; |
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fpscr_zx = (fp >> FPSCR_ZX) & 0x01; |
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fpscr_xx = (fp >> FPSCR_XX) & 0x01; |
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fpscr_vsxnan = (fp >> FPSCR_VXSNAN) & 0x01; |
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fpscr_vxisi = (fp >> FPSCR_VXISI) & 0x01; |
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fpscr_vxidi = (fp >> FPSCR_VXIDI) & 0x01; |
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fpscr_vxzdz = (fp >> FPSCR_VXZDZ) & 0x01; |
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fpscr_vximz = (fp >> FPSCR_VXIMZ) & 0x01; |
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fpscr_fr = (fp >> FPSCR_FR) & 0x01; |
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fpscr_fi = (fp >> FPSCR_FI) & 0x01; |
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fpscr_fprf = (fp >> FPSCR_FPRF) & 0x1F; |
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fpscr_vxsoft = (fp >> FPSCR_VXSOFT) & 0x01; |
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fpscr_vxsqrt = (fp >> FPSCR_VXSQRT) & 0x01; |
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fpscr_oe = (fp >> FPSCR_OE) & 0x01; |
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fpscr_ue = (fp >> FPSCR_UE) & 0x01; |
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fpscr_ze = (fp >> FPSCR_ZE) & 0x01; |
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fpscr_xe = (fp >> FPSCR_XE) & 0x01; |
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fpscr_ni = (fp >> FPSCR_NI) & 0x01; |
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fpscr_rn = (fp >> FPSCR_RN) & 0x03; |
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| 185 | 185 |
} |
| 186 | 186 |
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| 187 | 187 |
int32_t do_sraw(int32_t value, uint32_t shift) |
| ... | ... | |
| 220 | 220 |
int sh; |
| 221 | 221 |
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| 222 | 222 |
for (; count > 3; count -= 4, src += 4) {
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if (reg == 32) |
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reg = 0; |
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| 225 | 223 |
ugpr(reg++) = ld32(src); |
| 224 |
if (T2 == 32) |
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T2 = 0; |
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| 226 | 226 |
} |
| 227 | 227 |
if (count > 0) {
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for (sh = 24, tmp = 0; count > 0; count--, src++, sh -= 8) {
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if (reg == 32) |
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reg = 0; |
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tmp |= ld8(src) << sh; |
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if (sh == 0) {
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sh = 32; |
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ugpr(reg++) = tmp; |
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| 235 | 228 |
tmp = 0; |
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} |
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for (sh = 24; count > 0; count--, src++, sh -= 8) {
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tmp |= ld8(src) << sh; |
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| 237 | 231 |
} |
| 238 | 232 |
ugpr(reg) = tmp; |
| 239 | 233 |
} |
| ... | ... | |
| 244 | 238 |
int sh; |
| 245 | 239 |
|
| 246 | 240 |
for (; count > 3; count -= 4, dest += 4) {
|
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st32(dest, ugpr(reg++)); |
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| 247 | 242 |
if (reg == 32) |
| 248 | 243 |
reg = 0; |
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st32(dest, ugpr(reg++)); |
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| 250 | 244 |
} |
| 251 | 245 |
if (count > 0) {
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| 252 | 246 |
for (sh = 24; count > 0; count--, dest++, sh -= 8) {
|
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if (reg == 32) |
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reg = 0; |
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| 255 | 247 |
st8(dest, (ugpr(reg) >> sh) & 0xFF); |
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if (sh == 0) {
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sh = 32; |
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reg++; |
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| 259 | 248 |
} |
| 260 | 249 |
} |
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} |
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|
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void do_dcbz (void) |
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{
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int i; |
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|
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/* Assume cache line size is 32 */ |
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for (i = 0; i < 8; i++) {
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st32(T0, 0); |
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T0 += 4; |
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| 261 | 260 |
} |
| 262 | 261 |
} |
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|
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/* Instruction cache invalidation helper */ |
|
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void do_icbi (void) |
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{
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tb_invalidate_page(T0); |
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} |
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