Archipelago » qemu

/* Board init.  */

                     const char *boot_device,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

}

static

                     const char *boot_device,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

#ifndef HW_BOARDS_H

#define HW_BOARDS_H

                                 const char *boot_device,

                                 const char *kernel_filename,

                                 const char *kernel_cmdline,

 *

 ***************************************/

{

    CirrusVGAState *s;

    s = qemu_mallocz(sizeof(CirrusVGAState));

    cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);

    s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,

                                     s->vga.screen_dump, s->vga.text_update,

    cirrus_update_memory_access(s);

}

{

    PCICirrusVGAState *d;

    uint8_t *pci_conf;

    /* setup VGA */

    s = &d->cirrus_vga;

    cirrus_init_common(s, device_id, 1);

    s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,

/* Board init.  */

                     const char *boot_device,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

}

static

                       const char *boot_device,

                       const char *kernel_filename, const char *kernel_cmdline,

                       const char *initrd_filename, const char *cpu_model)

    qemu_put_be32(f, s->height);

}

                   target_phys_addr_t ctrl_base, int it_shift,

                   qemu_irq irq)

{

    s = qemu_mallocz(sizeof(G364State));

    s->vram = qemu_get_ram_ptr(s->vram_offset);

    s->irq = irq;

    qemu_register_reset(g364fb_reset, s);

static const int sector_len = 128 * 1024;

                const char *boot_device,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

                    pxa2xx_gpio_in_get(cpu->gpio)[36]);

}

                const char *boot_device,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

    .board_id = 0x113,

};

                     const char *boot_device,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

    .ram_size = 0x04000000,

};

                const char *kernel_filename,

                const char *kernel_cmdline, const char *initrd_filename,

                const char *cpu_model, enum mainstone_model_e model, int arm_id)

    arm_load_kernel(cpu->env, &mainstone_binfo);

}

                const char *boot_device,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

{

                kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196);

}

    }

}

                     const char *boot_device,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

void ds1225y_set_protection(void *opaque, int protection);

/* g364fb.c */

                   target_phys_addr_t ctrl_base, int it_shift,

                   qemu_irq irq);

#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)

static

                     const char *cpu_model,

                     enum jazz_model_e jazz_model)

{

    /* Video card */

    switch (jazz_model) {

    case JAZZ_MAGNUM:

        break;

    case JAZZ_PICA61:

        break;

    default:

        break;

}

static

                       const char *boot_device,

                       const char *kernel_filename, const char *kernel_cmdline,

                       const char *initrd_filename, const char *cpu_model)

{

}

static

                       const char *boot_device,

                       const char *kernel_filename, const char *kernel_cmdline,

                       const char *initrd_filename, const char *cpu_model)

{

}

QEMUMachine mips_magnum_machine = {

}

static

                      const char *boot_device,

                      const char *kernel_filename, const char *kernel_cmdline,

                      const char *initrd_filename, const char *cpu_model)

    /* Optional PCI video card */

    if (cirrus_vga_enabled) {

    } else if (vmsvga_enabled) {

    } else if (std_vga_enabled) {

    }

}

}

static void

                   const char *boot_device,

                   const char *kernel_filename, const char *kernel_cmdline,

                   const char *initrd_filename, const char *cpu_model)

static const int sector_len = 32 * 1024;

static

                    const char *boot_device,

                    const char *kernel_filename, const char *kernel_cmdline,

                    const char *initrd_filename, const char *cpu_model)

        }

    }

    if (nd_table[0].vlan)

        isa_ne2000_init(0x300, i8259[9], &nd_table[0]);

    .board_id = 0x20e,

};

               const char *boot_device,

               const char *kernel_filename, const char *kernel_cmdline,

               const char *initrd_filename, const char *cpu_model)

    .atag_board = n810_atag_setup,

};

                const char *boot_device,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

                    cpu_model, &n800_binfo, 800);

}

                const char *boot_device,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

    .board_id = 0x265,

};

                const char *boot_device,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model,

    //~ qemu_console_resize(ds, 640, 480);

}

                const char *boot_device,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

{

                kernel_cmdline, initrd_filename, cpu_model, 1);

}

                const char *boot_device,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

{

                kernel_cmdline, initrd_filename, cpu_model, 2);

}

    .board_id = 0x331,

};

                const char *boot_device,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

}

/* PC hardware initialisation */

                     const char *boot_device,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename,

    if (cirrus_vga_enabled) {

        if (pci_enabled) {

        } else {

        }

    } else if (vmsvga_enabled) {

        if (pci_enabled)

        else

            fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);

    } else if (std_vga_enabled) {

        if (pci_enabled) {

        } else {

        }

    }

    }

}

                        const char *boot_device,

                        const char *kernel_filename,

                        const char *kernel_cmdline,

                        const char *initrd_filename,

                        const char *cpu_model)

{

             kernel_filename, kernel_cmdline,

             initrd_filename, 1, cpu_model);

}

                        const char *boot_device,

                        const char *kernel_filename,

                        const char *kernel_cmdline,

                        const char *initrd_filename,

                        const char *cpu_model)

{

             kernel_filename, kernel_cmdline,

             initrd_filename, 0, cpu_model);

}

extern enum vga_retrace_method vga_retrace_method;

                 unsigned long vga_bios_offset, int vga_bios_size);

                    target_phys_addr_t ctrl_base, int it_shift);

/* cirrus_vga.c */

/* ide.c */

void isa_ide_init(int iobase, int iobase2, qemu_irq irq,

void *lsi_scsi_init(PCIBus *bus, int devfn);

/* vmware_vga.c */

/* usb-uhci.c */

void usb_uhci_piix3_init(PCIBus *bus, int devfn);

    qemu_register_reset(&ref405ep_fpga_reset, fpga);

}

                           const char *boot_device,

                           const char *kernel_filename,

                           const char *kernel_cmdline,

    qemu_register_reset(&taihu_cpld_reset, cpld);

}

                             const char *boot_device,

                             const char *kernel_filename,

                             const char *kernel_cmdline,

    return fdt;

}

                        const char *boot_device,

                        const char *kernel_filename,

                        const char *kernel_cmdline,

}

/* PowerPC Mac99 hardware initialisation */

                             const char *boot_device,

                             const char *kernel_filename,

                             const char *kernel_cmdline,

    pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL);

    pci_bus = pci_pmac_init(pic);

    /* init basic PC hardware */

    /* XXX: suppress that */

    dummy_irq = i8259_init(NULL);

    return 0;

}

                               const char *boot_device,

                               const char *kernel_filename,

                               const char *kernel_cmdline,

    }

    pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);

    pci_bus = pci_grackle_init(0xfec00000, pic);

    escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],

                               serial_hds[1], ESCC_CLOCK, 4);

#define NVRAM_SIZE        0x2000

/* PowerPC PREP hardware initialisation */

                           const char *boot_device,

                           const char *kernel_filename,

                           const char *kernel_cmdline,

    cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);

    /* init basic PC hardware */

    //    openpic = openpic_init(0x00000000, 0xF0000000, 1);

    //    pit = pit_init(0x40, i8259[0]);

    rtc_init(0x70, i8259[8], 2000);

    return fdt;

}

                         const char *boot_device,

                         const char *kernel_filename,

                         const char *kernel_cmdline,

    return intx[d->devfn >> 3];

}

              const char *boot_device,

	      const char *kernel_filename, const char *kernel_cmdline,

	      const char *initrd_filename, const char *cpu_model)

    .board_id = 0x33b,

};

                     const char *boot_device,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

    /* XXXXX */

}

               const char *boot_device,

	       const char *kernel_filename, const char *kernel_cmdline,

	       const char *initrd_filename, const char *cpu_model)

    .ram_size = 0x04000000,

};

                const char *kernel_filename,

                const char *kernel_cmdline, const char *initrd_filename,

                const char *cpu_model, enum spitz_model_e model, int arm_id)

    sl_bootparam_write(SL_PXA_PARAM_BASE);

}

                const char *boot_device,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

{

                kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);

}

                const char *boot_device,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

{

                kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);

}

                const char *boot_device,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

{

                kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);

}

                const char *boot_device,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

{

                kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);

}

}

/* FIXME: Figure out how to generate these from stellaris_boards.  */

                     const char *boot_device,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

    stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);

}

                     const char *boot_device,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

};

/* SPARCstation 5 hardware initialisation */

                     const char *boot_device,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

}

/* SPARCstation 10 hardware initialisation */

                      const char *boot_device,

                      const char *kernel_filename, const char *kernel_cmdline,

                      const char *initrd_filename, const char *cpu_model)

}

/* SPARCserver 600MP hardware initialisation */

                         const char *boot_device,

                         const char *kernel_filename,

                         const char *kernel_cmdline,

}

/* SPARCstation 20 hardware initialisation */

                      const char *boot_device,

                      const char *kernel_filename, const char *kernel_cmdline,

                      const char *initrd_filename, const char *cpu_model)

}

/* SPARCstation Voyager hardware initialisation */

                      const char *boot_device,

                      const char *kernel_filename, const char *kernel_cmdline,

                      const char *initrd_filename, const char *cpu_model)

}

/* SPARCstation LX hardware initialisation */

                       const char *boot_device,

                       const char *kernel_filename, const char *kernel_cmdline,

                       const char *initrd_filename, const char *cpu_model)

}

/* SPARCstation 4 hardware initialisation */

                     const char *boot_device,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

}

/* SPARCClassic hardware initialisation */

                      const char *boot_device,

                      const char *kernel_filename, const char *kernel_cmdline,

                      const char *initrd_filename, const char *cpu_model)

}

/* SPARCbook hardware initialisation */

                       const char *boot_device,

                       const char *kernel_filename, const char *kernel_cmdline,

                       const char *initrd_filename, const char *cpu_model)

}

/* SPARCserver 1000 hardware initialisation */

                        const char *boot_device,

                        const char *kernel_filename, const char *kernel_cmdline,

                        const char *initrd_filename, const char *cpu_model)

}

/* SPARCcenter 2000 hardware initialisation */

                        const char *boot_device,

                        const char *kernel_filename, const char *kernel_cmdline,

                        const char *initrd_filename, const char *cpu_model)

}

/* SPARCstation 2 hardware initialisation */

                     const char *boot_device,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

                           ebus_mmio_mapfunc);

}

                        const char *boot_devices,

                        const char *kernel_filename, const char *kernel_cmdline,

                        const char *initrd_filename, const char *cpu_model,

    pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL, &pci_bus2,

                           &pci_bus3);

    isa_mem_base = VGA_BASE;

    // XXX Should be pci_bus3

    pci_ebus_init(pci_bus, -1);

};

/* Sun4u hardware initialisation */

                       const char *boot_devices,

                       const char *kernel_filename, const char *kernel_cmdline,

                       const char *initrd_filename, const char *cpu_model)

{

                kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);

}

/* Sun4v hardware initialisation */

                       const char *boot_devices,

                       const char *kernel_filename, const char *kernel_cmdline,

                       const char *initrd_filename, const char *cpu_model)

{

                kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);

}

/* Niagara hardware initialisation */

                         const char *boot_devices,

                         const char *kernel_filename, const char *kernel_cmdline,

                         const char *initrd_filename, const char *cpu_model)

{

                kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);

}

    .ram_size = 0x04000000,

};

                const char *boot_device,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

static struct arm_boot_info versatile_binfo;

                     const char *boot_device,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model,

    arm_load_kernel(env, &versatile_binfo);

}

                     const char *boot_device,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

{

                   boot_device,

                   kernel_filename, kernel_cmdline,

                   initrd_filename, cpu_model, 0x183);

}

                     const char *boot_device,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

{

                   boot_device,

                   kernel_filename, kernel_cmdline,

                   initrd_filename, cpu_model, 0x25e);

    qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000);

}

{

    VGAState *s;

    s = qemu_mallocz(sizeof(VGAState));

    vga_init(s);

    s->ds = graphic_console_init(s->update, s->invalidate,

#ifdef CONFIG_BOCHS_VBE

    /* XXX: use optimized standard vga accesses */

    cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,

#endif

    return 0;

}

                    target_phys_addr_t ctrl_base, int it_shift)

{

    VGAState *s;

    s = qemu_mallocz(sizeof(VGAState));

    vga_mm_init(s, vram_base, ctrl_base, it_shift);

    s->ds = graphic_console_init(s->update, s->invalidate,

#ifdef CONFIG_BOCHS_VBE

    /* XXX: use optimized standard vga accesses */

    cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,

#endif

    return 0;

}

        s->map_addr = 0;

}

                 unsigned long vga_bios_offset, int vga_bios_size)

{

    PCIVGAState *d;

        return -1;

    s = &d->vga_state;

    vga_init(s);

    s->ds = graphic_console_init(s->update, s->invalidate,

    pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);

    pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type

                           PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);

    if (vga_bios_size != 0) {

        unsigned int bios_total_size;

extern const uint8_t sr_mask[8];

extern const uint8_t gr_mask[16];

                    iomemtype);

}

{

    struct pci_vmsvga_state_s *s;

    pci_register_io_region(&s->card, 0, 0x10,

                    PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);

                    PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem);

    register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);

}

   to store the VM snapshots */

DriveInfo drives_table[MAX_DRIVES+1];

int nb_drives;

enum vga_retrace_method vga_retrace_method = VGA_RETRACE_DUMB;

static DisplayState *display_state;

int nographic;

    cpu_model = NULL;

    initrd_filename = NULL;

    ram_size = 0;

    snapshot = 0;

    nographic = 0;

    curses = 0;

        }

    }

                  kernel_filename, kernel_cmdline, initrd_filename, cpu_model);