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/*
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* Luminary Micro Stellaris peripherals
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*
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* Copyright (c) 2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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#include "hw.h" |
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#include "arm-misc.h" |
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#include "primecell.h" |
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#include "devices.h" |
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#include "qemu-timer.h" |
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#include "i2c.h" |
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#include "net.h" |
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#include "sd.h" |
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#include "sysemu.h" |
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#include "boards.h" |
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|
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#define GPIO_A 0 |
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#define GPIO_B 1 |
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#define GPIO_C 2 |
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#define GPIO_D 3 |
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#define GPIO_E 4 |
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#define GPIO_F 5 |
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#define GPIO_G 6 |
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|
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#define BP_OLED_I2C 0x01 |
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#define BP_OLED_SSI 0x02 |
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#define BP_GAMEPAD 0x04 |
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|
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typedef const struct { |
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const char *name; |
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uint32_t did0; |
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uint32_t did1; |
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uint32_t dc0; |
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uint32_t dc1; |
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uint32_t dc2; |
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uint32_t dc3; |
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uint32_t dc4; |
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uint32_t peripherals; |
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} stellaris_board_info; |
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|
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/* General purpose timer module. */
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|
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typedef struct gptm_state { |
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uint32_t config; |
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uint32_t mode[2];
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uint32_t control; |
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uint32_t state; |
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uint32_t mask; |
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uint32_t load[2];
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uint32_t match[2];
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uint32_t prescale[2];
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uint32_t match_prescale[2];
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uint32_t rtc; |
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int64_t tick[2];
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struct gptm_state *opaque[2]; |
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QEMUTimer *timer[2];
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/* The timers have an alternate output used to trigger the ADC. */
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qemu_irq trigger; |
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qemu_irq irq; |
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} gptm_state; |
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|
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static void gptm_update_irq(gptm_state *s) |
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{
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int level;
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level = (s->state & s->mask) != 0;
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qemu_set_irq(s->irq, level); |
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} |
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|
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static void gptm_stop(gptm_state *s, int n) |
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{
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qemu_del_timer(s->timer[n]); |
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} |
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|
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static void gptm_reload(gptm_state *s, int n, int reset) |
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{
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int64_t tick; |
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if (reset)
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tick = qemu_get_clock(vm_clock); |
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else
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tick = s->tick[n]; |
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|
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if (s->config == 0) { |
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/* 32-bit CountDown. */
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uint32_t count; |
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count = s->load[0] | (s->load[1] << 16); |
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tick += (int64_t)count * system_clock_scale; |
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} else if (s->config == 1) { |
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/* 32-bit RTC. 1Hz tick. */
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tick += ticks_per_sec; |
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} else if (s->mode[n] == 0xa) { |
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/* PWM mode. Not implemented. */
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} else {
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hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
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} |
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s->tick[n] = tick; |
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qemu_mod_timer(s->timer[n], tick); |
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} |
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|
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static void gptm_tick(void *opaque) |
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{
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gptm_state **p = (gptm_state **)opaque; |
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gptm_state *s; |
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int n;
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s = *p; |
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n = p - s->opaque; |
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if (s->config == 0) { |
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s->state |= 1;
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if ((s->control & 0x20)) { |
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/* Output trigger. */
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qemu_irq_raise(s->trigger); |
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qemu_irq_lower(s->trigger); |
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} |
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if (s->mode[0] & 1) { |
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/* One-shot. */
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s->control &= ~1;
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} else {
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/* Periodic. */
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gptm_reload(s, 0, 0); |
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} |
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} else if (s->config == 1) { |
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/* RTC. */
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uint32_t match; |
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s->rtc++; |
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match = s->match[0] | (s->match[1] << 16); |
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if (s->rtc > match)
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s->rtc = 0;
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if (s->rtc == 0) { |
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s->state |= 8;
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} |
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gptm_reload(s, 0, 0); |
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} else if (s->mode[n] == 0xa) { |
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/* PWM mode. Not implemented. */
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} else {
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hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
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} |
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gptm_update_irq(s); |
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} |
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|
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static uint32_t gptm_read(void *opaque, target_phys_addr_t offset) |
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{
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gptm_state *s = (gptm_state *)opaque; |
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|
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switch (offset) {
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case 0x00: /* CFG */ |
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return s->config;
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case 0x04: /* TAMR */ |
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return s->mode[0]; |
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case 0x08: /* TBMR */ |
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return s->mode[1]; |
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case 0x0c: /* CTL */ |
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return s->control;
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case 0x18: /* IMR */ |
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return s->mask;
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case 0x1c: /* RIS */ |
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return s->state;
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case 0x20: /* MIS */ |
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return s->state & s->mask;
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case 0x24: /* CR */ |
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return 0; |
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case 0x28: /* TAILR */ |
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return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); |
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case 0x2c: /* TBILR */ |
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return s->load[1]; |
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case 0x30: /* TAMARCHR */ |
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return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); |
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case 0x34: /* TBMATCHR */ |
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return s->match[1]; |
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case 0x38: /* TAPR */ |
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return s->prescale[0]; |
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case 0x3c: /* TBPR */ |
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return s->prescale[1]; |
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case 0x40: /* TAPMR */ |
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return s->match_prescale[0]; |
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case 0x44: /* TBPMR */ |
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return s->match_prescale[1]; |
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case 0x48: /* TAR */ |
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if (s->control == 1) |
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return s->rtc;
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case 0x4c: /* TBR */ |
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hw_error("TODO: Timer value read\n");
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default:
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hw_error("gptm_read: Bad offset 0x%x\n", (int)offset); |
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return 0; |
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} |
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} |
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|
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static void gptm_write(void *opaque, target_phys_addr_t offset, uint32_t value) |
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{
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gptm_state *s = (gptm_state *)opaque; |
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uint32_t oldval; |
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/* The timers should be disabled before changing the configuration.
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We take advantage of this and defer everything until the timer
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is enabled. */
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switch (offset) {
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case 0x00: /* CFG */ |
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s->config = value; |
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break;
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case 0x04: /* TAMR */ |
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s->mode[0] = value;
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break;
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case 0x08: /* TBMR */ |
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s->mode[1] = value;
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break;
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case 0x0c: /* CTL */ |
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oldval = s->control; |
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s->control = value; |
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/* TODO: Implement pause. */
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if ((oldval ^ value) & 1) { |
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if (value & 1) { |
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gptm_reload(s, 0, 1); |
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} else {
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gptm_stop(s, 0);
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} |
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} |
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if (((oldval ^ value) & 0x100) && s->config >= 4) { |
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if (value & 0x100) { |
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gptm_reload(s, 1, 1); |
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} else {
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gptm_stop(s, 1);
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} |
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} |
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break;
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case 0x18: /* IMR */ |
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s->mask = value & 0x77;
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gptm_update_irq(s); |
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break;
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case 0x24: /* CR */ |
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s->state &= ~value; |
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break;
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case 0x28: /* TAILR */ |
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s->load[0] = value & 0xffff; |
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if (s->config < 4) { |
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s->load[1] = value >> 16; |
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} |
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break;
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case 0x2c: /* TBILR */ |
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s->load[1] = value & 0xffff; |
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break;
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case 0x30: /* TAMARCHR */ |
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s->match[0] = value & 0xffff; |
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if (s->config < 4) { |
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s->match[1] = value >> 16; |
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} |
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break;
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case 0x34: /* TBMATCHR */ |
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s->match[1] = value >> 16; |
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break;
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case 0x38: /* TAPR */ |
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s->prescale[0] = value;
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break;
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case 0x3c: /* TBPR */ |
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s->prescale[1] = value;
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break;
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case 0x40: /* TAPMR */ |
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s->match_prescale[0] = value;
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break;
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case 0x44: /* TBPMR */ |
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s->match_prescale[0] = value;
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break;
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default:
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hw_error("gptm_write: Bad offset 0x%x\n", (int)offset); |
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} |
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gptm_update_irq(s); |
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} |
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|
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static CPUReadMemoryFunc *gptm_readfn[] = {
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gptm_read, |
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gptm_read, |
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gptm_read |
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}; |
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|
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static CPUWriteMemoryFunc *gptm_writefn[] = {
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gptm_write, |
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gptm_write, |
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gptm_write |
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}; |
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|
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static void gptm_save(QEMUFile *f, void *opaque) |
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{
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gptm_state *s = (gptm_state *)opaque; |
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|
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qemu_put_be32(f, s->config); |
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qemu_put_be32(f, s->mode[0]);
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qemu_put_be32(f, s->mode[1]);
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qemu_put_be32(f, s->control); |
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qemu_put_be32(f, s->state); |
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qemu_put_be32(f, s->mask); |
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qemu_put_be32(f, s->mode[0]);
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qemu_put_be32(f, s->mode[0]);
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qemu_put_be32(f, s->load[0]);
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qemu_put_be32(f, s->load[1]);
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qemu_put_be32(f, s->match[0]);
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qemu_put_be32(f, s->match[1]);
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qemu_put_be32(f, s->prescale[0]);
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qemu_put_be32(f, s->prescale[1]);
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qemu_put_be32(f, s->match_prescale[0]);
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qemu_put_be32(f, s->match_prescale[1]);
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qemu_put_be32(f, s->rtc); |
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qemu_put_be64(f, s->tick[0]);
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qemu_put_be64(f, s->tick[1]);
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qemu_put_timer(f, s->timer[0]);
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qemu_put_timer(f, s->timer[1]);
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} |
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|
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static int gptm_load(QEMUFile *f, void *opaque, int version_id) |
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{
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gptm_state *s = (gptm_state *)opaque; |
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|
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if (version_id != 1) |
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return -EINVAL;
|
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|
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s->config = qemu_get_be32(f); |
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s->mode[0] = qemu_get_be32(f);
|
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s->mode[1] = qemu_get_be32(f);
|
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s->control = qemu_get_be32(f); |
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s->state = qemu_get_be32(f); |
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s->mask = qemu_get_be32(f); |
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s->mode[0] = qemu_get_be32(f);
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s->mode[0] = qemu_get_be32(f);
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s->load[0] = qemu_get_be32(f);
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s->load[1] = qemu_get_be32(f);
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s->match[0] = qemu_get_be32(f);
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s->match[1] = qemu_get_be32(f);
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s->prescale[0] = qemu_get_be32(f);
|
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s->prescale[1] = qemu_get_be32(f);
|
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s->match_prescale[0] = qemu_get_be32(f);
|
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s->match_prescale[1] = qemu_get_be32(f);
|
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s->rtc = qemu_get_be32(f); |
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s->tick[0] = qemu_get_be64(f);
|
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s->tick[1] = qemu_get_be64(f);
|
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qemu_get_timer(f, s->timer[0]);
|
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qemu_get_timer(f, s->timer[1]);
|
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|
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return 0; |
| 341 |
} |
| 342 |
|
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static void stellaris_gptm_init(uint32_t base, qemu_irq irq, qemu_irq trigger) |
| 344 |
{
|
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int iomemtype;
|
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gptm_state *s; |
| 347 |
|
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s = (gptm_state *)qemu_mallocz(sizeof(gptm_state));
|
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s->irq = irq; |
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s->trigger = trigger; |
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s->opaque[0] = s->opaque[1] = s; |
| 352 |
|
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iomemtype = cpu_register_io_memory(0, gptm_readfn,
|
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gptm_writefn, s); |
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cpu_register_physical_memory(base, 0x00001000, iomemtype);
|
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s->timer[0] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[0]); |
| 357 |
s->timer[1] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[1]); |
| 358 |
register_savevm("stellaris_gptm", -1, 1, gptm_save, gptm_load, s); |
| 359 |
} |
| 360 |
|
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|
| 362 |
/* System controller. */
|
| 363 |
|
| 364 |
typedef struct { |
| 365 |
uint32_t pborctl; |
| 366 |
uint32_t ldopctl; |
| 367 |
uint32_t int_status; |
| 368 |
uint32_t int_mask; |
| 369 |
uint32_t resc; |
| 370 |
uint32_t rcc; |
| 371 |
uint32_t rcgc[3];
|
| 372 |
uint32_t scgc[3];
|
| 373 |
uint32_t dcgc[3];
|
| 374 |
uint32_t clkvclr; |
| 375 |
uint32_t ldoarst; |
| 376 |
uint32_t user0; |
| 377 |
uint32_t user1; |
| 378 |
qemu_irq irq; |
| 379 |
stellaris_board_info *board; |
| 380 |
} ssys_state; |
| 381 |
|
| 382 |
static void ssys_update(ssys_state *s) |
| 383 |
{
|
| 384 |
qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
|
| 385 |
} |
| 386 |
|
| 387 |
static uint32_t pllcfg_sandstorm[16] = { |
| 388 |
0x31c0, /* 1 Mhz */ |
| 389 |
0x1ae0, /* 1.8432 Mhz */ |
| 390 |
0x18c0, /* 2 Mhz */ |
| 391 |
0xd573, /* 2.4576 Mhz */ |
| 392 |
0x37a6, /* 3.57954 Mhz */ |
| 393 |
0x1ae2, /* 3.6864 Mhz */ |
| 394 |
0x0c40, /* 4 Mhz */ |
| 395 |
0x98bc, /* 4.906 Mhz */ |
| 396 |
0x935b, /* 4.9152 Mhz */ |
| 397 |
0x09c0, /* 5 Mhz */ |
| 398 |
0x4dee, /* 5.12 Mhz */ |
| 399 |
0x0c41, /* 6 Mhz */ |
| 400 |
0x75db, /* 6.144 Mhz */ |
| 401 |
0x1ae6, /* 7.3728 Mhz */ |
| 402 |
0x0600, /* 8 Mhz */ |
| 403 |
0x585b /* 8.192 Mhz */ |
| 404 |
}; |
| 405 |
|
| 406 |
static uint32_t pllcfg_fury[16] = { |
| 407 |
0x3200, /* 1 Mhz */ |
| 408 |
0x1b20, /* 1.8432 Mhz */ |
| 409 |
0x1900, /* 2 Mhz */ |
| 410 |
0xf42b, /* 2.4576 Mhz */ |
| 411 |
0x37e3, /* 3.57954 Mhz */ |
| 412 |
0x1b21, /* 3.6864 Mhz */ |
| 413 |
0x0c80, /* 4 Mhz */ |
| 414 |
0x98ee, /* 4.906 Mhz */ |
| 415 |
0xd5b4, /* 4.9152 Mhz */ |
| 416 |
0x0a00, /* 5 Mhz */ |
| 417 |
0x4e27, /* 5.12 Mhz */ |
| 418 |
0x1902, /* 6 Mhz */ |
| 419 |
0xec1c, /* 6.144 Mhz */ |
| 420 |
0x1b23, /* 7.3728 Mhz */ |
| 421 |
0x0640, /* 8 Mhz */ |
| 422 |
0xb11c /* 8.192 Mhz */ |
| 423 |
}; |
| 424 |
|
| 425 |
static uint32_t ssys_read(void *opaque, target_phys_addr_t offset) |
| 426 |
{
|
| 427 |
ssys_state *s = (ssys_state *)opaque; |
| 428 |
|
| 429 |
switch (offset) {
|
| 430 |
case 0x000: /* DID0 */ |
| 431 |
return s->board->did0;
|
| 432 |
case 0x004: /* DID1 */ |
| 433 |
return s->board->did1;
|
| 434 |
case 0x008: /* DC0 */ |
| 435 |
return s->board->dc0;
|
| 436 |
case 0x010: /* DC1 */ |
| 437 |
return s->board->dc1;
|
| 438 |
case 0x014: /* DC2 */ |
| 439 |
return s->board->dc2;
|
| 440 |
case 0x018: /* DC3 */ |
| 441 |
return s->board->dc3;
|
| 442 |
case 0x01c: /* DC4 */ |
| 443 |
return s->board->dc4;
|
| 444 |
case 0x030: /* PBORCTL */ |
| 445 |
return s->pborctl;
|
| 446 |
case 0x034: /* LDOPCTL */ |
| 447 |
return s->ldopctl;
|
| 448 |
case 0x040: /* SRCR0 */ |
| 449 |
return 0; |
| 450 |
case 0x044: /* SRCR1 */ |
| 451 |
return 0; |
| 452 |
case 0x048: /* SRCR2 */ |
| 453 |
return 0; |
| 454 |
case 0x050: /* RIS */ |
| 455 |
return s->int_status;
|
| 456 |
case 0x054: /* IMC */ |
| 457 |
return s->int_mask;
|
| 458 |
case 0x058: /* MISC */ |
| 459 |
return s->int_status & s->int_mask;
|
| 460 |
case 0x05c: /* RESC */ |
| 461 |
return s->resc;
|
| 462 |
case 0x060: /* RCC */ |
| 463 |
return s->rcc;
|
| 464 |
case 0x064: /* PLLCFG */ |
| 465 |
{
|
| 466 |
int xtal;
|
| 467 |
xtal = (s->rcc >> 6) & 0xf; |
| 468 |
if (s->board->did0 & (1 << 16)) { |
| 469 |
return pllcfg_fury[xtal];
|
| 470 |
} else {
|
| 471 |
return pllcfg_sandstorm[xtal];
|
| 472 |
} |
| 473 |
} |
| 474 |
case 0x100: /* RCGC0 */ |
| 475 |
return s->rcgc[0]; |
| 476 |
case 0x104: /* RCGC1 */ |
| 477 |
return s->rcgc[1]; |
| 478 |
case 0x108: /* RCGC2 */ |
| 479 |
return s->rcgc[2]; |
| 480 |
case 0x110: /* SCGC0 */ |
| 481 |
return s->scgc[0]; |
| 482 |
case 0x114: /* SCGC1 */ |
| 483 |
return s->scgc[1]; |
| 484 |
case 0x118: /* SCGC2 */ |
| 485 |
return s->scgc[2]; |
| 486 |
case 0x120: /* DCGC0 */ |
| 487 |
return s->dcgc[0]; |
| 488 |
case 0x124: /* DCGC1 */ |
| 489 |
return s->dcgc[1]; |
| 490 |
case 0x128: /* DCGC2 */ |
| 491 |
return s->dcgc[2]; |
| 492 |
case 0x150: /* CLKVCLR */ |
| 493 |
return s->clkvclr;
|
| 494 |
case 0x160: /* LDOARST */ |
| 495 |
return s->ldoarst;
|
| 496 |
case 0x1e0: /* USER0 */ |
| 497 |
return s->user0;
|
| 498 |
case 0x1e4: /* USER1 */ |
| 499 |
return s->user1;
|
| 500 |
default:
|
| 501 |
hw_error("ssys_read: Bad offset 0x%x\n", (int)offset); |
| 502 |
return 0; |
| 503 |
} |
| 504 |
} |
| 505 |
|
| 506 |
static void ssys_calculate_system_clock(ssys_state *s) |
| 507 |
{
|
| 508 |
system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); |
| 509 |
} |
| 510 |
|
| 511 |
static void ssys_write(void *opaque, target_phys_addr_t offset, uint32_t value) |
| 512 |
{
|
| 513 |
ssys_state *s = (ssys_state *)opaque; |
| 514 |
|
| 515 |
switch (offset) {
|
| 516 |
case 0x030: /* PBORCTL */ |
| 517 |
s->pborctl = value & 0xffff;
|
| 518 |
break;
|
| 519 |
case 0x034: /* LDOPCTL */ |
| 520 |
s->ldopctl = value & 0x1f;
|
| 521 |
break;
|
| 522 |
case 0x040: /* SRCR0 */ |
| 523 |
case 0x044: /* SRCR1 */ |
| 524 |
case 0x048: /* SRCR2 */ |
| 525 |
fprintf(stderr, "Peripheral reset not implemented\n");
|
| 526 |
break;
|
| 527 |
case 0x054: /* IMC */ |
| 528 |
s->int_mask = value & 0x7f;
|
| 529 |
break;
|
| 530 |
case 0x058: /* MISC */ |
| 531 |
s->int_status &= ~value; |
| 532 |
break;
|
| 533 |
case 0x05c: /* RESC */ |
| 534 |
s->resc = value & 0x3f;
|
| 535 |
break;
|
| 536 |
case 0x060: /* RCC */ |
| 537 |
if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { |
| 538 |
/* PLL enable. */
|
| 539 |
s->int_status |= (1 << 6); |
| 540 |
} |
| 541 |
s->rcc = value; |
| 542 |
ssys_calculate_system_clock(s); |
| 543 |
break;
|
| 544 |
case 0x100: /* RCGC0 */ |
| 545 |
s->rcgc[0] = value;
|
| 546 |
break;
|
| 547 |
case 0x104: /* RCGC1 */ |
| 548 |
s->rcgc[1] = value;
|
| 549 |
break;
|
| 550 |
case 0x108: /* RCGC2 */ |
| 551 |
s->rcgc[2] = value;
|
| 552 |
break;
|
| 553 |
case 0x110: /* SCGC0 */ |
| 554 |
s->scgc[0] = value;
|
| 555 |
break;
|
| 556 |
case 0x114: /* SCGC1 */ |
| 557 |
s->scgc[1] = value;
|
| 558 |
break;
|
| 559 |
case 0x118: /* SCGC2 */ |
| 560 |
s->scgc[2] = value;
|
| 561 |
break;
|
| 562 |
case 0x120: /* DCGC0 */ |
| 563 |
s->dcgc[0] = value;
|
| 564 |
break;
|
| 565 |
case 0x124: /* DCGC1 */ |
| 566 |
s->dcgc[1] = value;
|
| 567 |
break;
|
| 568 |
case 0x128: /* DCGC2 */ |
| 569 |
s->dcgc[2] = value;
|
| 570 |
break;
|
| 571 |
case 0x150: /* CLKVCLR */ |
| 572 |
s->clkvclr = value; |
| 573 |
break;
|
| 574 |
case 0x160: /* LDOARST */ |
| 575 |
s->ldoarst = value; |
| 576 |
break;
|
| 577 |
default:
|
| 578 |
hw_error("ssys_write: Bad offset 0x%x\n", (int)offset); |
| 579 |
} |
| 580 |
ssys_update(s); |
| 581 |
} |
| 582 |
|
| 583 |
static CPUReadMemoryFunc *ssys_readfn[] = {
|
| 584 |
ssys_read, |
| 585 |
ssys_read, |
| 586 |
ssys_read |
| 587 |
}; |
| 588 |
|
| 589 |
static CPUWriteMemoryFunc *ssys_writefn[] = {
|
| 590 |
ssys_write, |
| 591 |
ssys_write, |
| 592 |
ssys_write |
| 593 |
}; |
| 594 |
|
| 595 |
static void ssys_reset(void *opaque) |
| 596 |
{
|
| 597 |
ssys_state *s = (ssys_state *)opaque; |
| 598 |
|
| 599 |
s->pborctl = 0x7ffd;
|
| 600 |
s->rcc = 0x078e3ac0;
|
| 601 |
s->rcgc[0] = 1; |
| 602 |
s->scgc[0] = 1; |
| 603 |
s->dcgc[0] = 1; |
| 604 |
} |
| 605 |
|
| 606 |
static void ssys_save(QEMUFile *f, void *opaque) |
| 607 |
{
|
| 608 |
ssys_state *s = (ssys_state *)opaque; |
| 609 |
|
| 610 |
qemu_put_be32(f, s->pborctl); |
| 611 |
qemu_put_be32(f, s->ldopctl); |
| 612 |
qemu_put_be32(f, s->int_mask); |
| 613 |
qemu_put_be32(f, s->int_status); |
| 614 |
qemu_put_be32(f, s->resc); |
| 615 |
qemu_put_be32(f, s->rcc); |
| 616 |
qemu_put_be32(f, s->rcgc[0]);
|
| 617 |
qemu_put_be32(f, s->rcgc[1]);
|
| 618 |
qemu_put_be32(f, s->rcgc[2]);
|
| 619 |
qemu_put_be32(f, s->scgc[0]);
|
| 620 |
qemu_put_be32(f, s->scgc[1]);
|
| 621 |
qemu_put_be32(f, s->scgc[2]);
|
| 622 |
qemu_put_be32(f, s->dcgc[0]);
|
| 623 |
qemu_put_be32(f, s->dcgc[1]);
|
| 624 |
qemu_put_be32(f, s->dcgc[2]);
|
| 625 |
qemu_put_be32(f, s->clkvclr); |
| 626 |
qemu_put_be32(f, s->ldoarst); |
| 627 |
} |
| 628 |
|
| 629 |
static int ssys_load(QEMUFile *f, void *opaque, int version_id) |
| 630 |
{
|
| 631 |
ssys_state *s = (ssys_state *)opaque; |
| 632 |
|
| 633 |
if (version_id != 1) |
| 634 |
return -EINVAL;
|
| 635 |
|
| 636 |
s->pborctl = qemu_get_be32(f); |
| 637 |
s->ldopctl = qemu_get_be32(f); |
| 638 |
s->int_mask = qemu_get_be32(f); |
| 639 |
s->int_status = qemu_get_be32(f); |
| 640 |
s->resc = qemu_get_be32(f); |
| 641 |
s->rcc = qemu_get_be32(f); |
| 642 |
s->rcgc[0] = qemu_get_be32(f);
|
| 643 |
s->rcgc[1] = qemu_get_be32(f);
|
| 644 |
s->rcgc[2] = qemu_get_be32(f);
|
| 645 |
s->scgc[0] = qemu_get_be32(f);
|
| 646 |
s->scgc[1] = qemu_get_be32(f);
|
| 647 |
s->scgc[2] = qemu_get_be32(f);
|
| 648 |
s->dcgc[0] = qemu_get_be32(f);
|
| 649 |
s->dcgc[1] = qemu_get_be32(f);
|
| 650 |
s->dcgc[2] = qemu_get_be32(f);
|
| 651 |
s->clkvclr = qemu_get_be32(f); |
| 652 |
s->ldoarst = qemu_get_be32(f); |
| 653 |
ssys_calculate_system_clock(s); |
| 654 |
|
| 655 |
return 0; |
| 656 |
} |
| 657 |
|
| 658 |
static void stellaris_sys_init(uint32_t base, qemu_irq irq, |
| 659 |
stellaris_board_info * board, |
| 660 |
uint8_t *macaddr) |
| 661 |
{
|
| 662 |
int iomemtype;
|
| 663 |
ssys_state *s; |
| 664 |
|
| 665 |
s = (ssys_state *)qemu_mallocz(sizeof(ssys_state));
|
| 666 |
s->irq = irq; |
| 667 |
s->board = board; |
| 668 |
/* Most devices come preprogrammed with a MAC address in the user data. */
|
| 669 |
s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); |
| 670 |
s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); |
| 671 |
|
| 672 |
iomemtype = cpu_register_io_memory(0, ssys_readfn,
|
| 673 |
ssys_writefn, s); |
| 674 |
cpu_register_physical_memory(base, 0x00001000, iomemtype);
|
| 675 |
ssys_reset(s); |
| 676 |
register_savevm("stellaris_sys", -1, 1, ssys_save, ssys_load, s); |
| 677 |
} |
| 678 |
|
| 679 |
|
| 680 |
/* I2C controller. */
|
| 681 |
|
| 682 |
typedef struct { |
| 683 |
i2c_bus *bus; |
| 684 |
qemu_irq irq; |
| 685 |
uint32_t msa; |
| 686 |
uint32_t mcs; |
| 687 |
uint32_t mdr; |
| 688 |
uint32_t mtpr; |
| 689 |
uint32_t mimr; |
| 690 |
uint32_t mris; |
| 691 |
uint32_t mcr; |
| 692 |
} stellaris_i2c_state; |
| 693 |
|
| 694 |
#define STELLARIS_I2C_MCS_BUSY 0x01 |
| 695 |
#define STELLARIS_I2C_MCS_ERROR 0x02 |
| 696 |
#define STELLARIS_I2C_MCS_ADRACK 0x04 |
| 697 |
#define STELLARIS_I2C_MCS_DATACK 0x08 |
| 698 |
#define STELLARIS_I2C_MCS_ARBLST 0x10 |
| 699 |
#define STELLARIS_I2C_MCS_IDLE 0x20 |
| 700 |
#define STELLARIS_I2C_MCS_BUSBSY 0x40 |
| 701 |
|
| 702 |
static uint32_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset) |
| 703 |
{
|
| 704 |
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; |
| 705 |
|
| 706 |
switch (offset) {
|
| 707 |
case 0x00: /* MSA */ |
| 708 |
return s->msa;
|
| 709 |
case 0x04: /* MCS */ |
| 710 |
/* We don't emulate timing, so the controller is never busy. */
|
| 711 |
return s->mcs | STELLARIS_I2C_MCS_IDLE;
|
| 712 |
case 0x08: /* MDR */ |
| 713 |
return s->mdr;
|
| 714 |
case 0x0c: /* MTPR */ |
| 715 |
return s->mtpr;
|
| 716 |
case 0x10: /* MIMR */ |
| 717 |
return s->mimr;
|
| 718 |
case 0x14: /* MRIS */ |
| 719 |
return s->mris;
|
| 720 |
case 0x18: /* MMIS */ |
| 721 |
return s->mris & s->mimr;
|
| 722 |
case 0x20: /* MCR */ |
| 723 |
return s->mcr;
|
| 724 |
default:
|
| 725 |
hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset); |
| 726 |
return 0; |
| 727 |
} |
| 728 |
} |
| 729 |
|
| 730 |
static void stellaris_i2c_update(stellaris_i2c_state *s) |
| 731 |
{
|
| 732 |
int level;
|
| 733 |
|
| 734 |
level = (s->mris & s->mimr) != 0;
|
| 735 |
qemu_set_irq(s->irq, level); |
| 736 |
} |
| 737 |
|
| 738 |
static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset, |
| 739 |
uint32_t value) |
| 740 |
{
|
| 741 |
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; |
| 742 |
|
| 743 |
switch (offset) {
|
| 744 |
case 0x00: /* MSA */ |
| 745 |
s->msa = value & 0xff;
|
| 746 |
break;
|
| 747 |
case 0x04: /* MCS */ |
| 748 |
if ((s->mcr & 0x10) == 0) { |
| 749 |
/* Disabled. Do nothing. */
|
| 750 |
break;
|
| 751 |
} |
| 752 |
/* Grab the bus if this is starting a transfer. */
|
| 753 |
if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { |
| 754 |
if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { |
| 755 |
s->mcs |= STELLARIS_I2C_MCS_ARBLST; |
| 756 |
} else {
|
| 757 |
s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; |
| 758 |
s->mcs |= STELLARIS_I2C_MCS_BUSBSY; |
| 759 |
} |
| 760 |
} |
| 761 |
/* If we don't have the bus then indicate an error. */
|
| 762 |
if (!i2c_bus_busy(s->bus)
|
| 763 |
|| (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
|
| 764 |
s->mcs |= STELLARIS_I2C_MCS_ERROR; |
| 765 |
break;
|
| 766 |
} |
| 767 |
s->mcs &= ~STELLARIS_I2C_MCS_ERROR; |
| 768 |
if (value & 1) { |
| 769 |
/* Transfer a byte. */
|
| 770 |
/* TODO: Handle errors. */
|
| 771 |
if (s->msa & 1) { |
| 772 |
/* Recv */
|
| 773 |
s->mdr = i2c_recv(s->bus) & 0xff;
|
| 774 |
} else {
|
| 775 |
/* Send */
|
| 776 |
i2c_send(s->bus, s->mdr); |
| 777 |
} |
| 778 |
/* Raise an interrupt. */
|
| 779 |
s->mris |= 1;
|
| 780 |
} |
| 781 |
if (value & 4) { |
| 782 |
/* Finish transfer. */
|
| 783 |
i2c_end_transfer(s->bus); |
| 784 |
s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; |
| 785 |
} |
| 786 |
break;
|
| 787 |
case 0x08: /* MDR */ |
| 788 |
s->mdr = value & 0xff;
|
| 789 |
break;
|
| 790 |
case 0x0c: /* MTPR */ |
| 791 |
s->mtpr = value & 0xff;
|
| 792 |
break;
|
| 793 |
case 0x10: /* MIMR */ |
| 794 |
s->mimr = 1;
|
| 795 |
break;
|
| 796 |
case 0x1c: /* MICR */ |
| 797 |
s->mris &= ~value; |
| 798 |
break;
|
| 799 |
case 0x20: /* MCR */ |
| 800 |
if (value & 1) |
| 801 |
hw_error( |
| 802 |
"stellaris_i2c_write: Loopback not implemented\n");
|
| 803 |
if (value & 0x20) |
| 804 |
hw_error( |
| 805 |
"stellaris_i2c_write: Slave mode not implemented\n");
|
| 806 |
s->mcr = value & 0x31;
|
| 807 |
break;
|
| 808 |
default:
|
| 809 |
hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
|
| 810 |
(int)offset);
|
| 811 |
} |
| 812 |
stellaris_i2c_update(s); |
| 813 |
} |
| 814 |
|
| 815 |
static void stellaris_i2c_reset(stellaris_i2c_state *s) |
| 816 |
{
|
| 817 |
if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
|
| 818 |
i2c_end_transfer(s->bus); |
| 819 |
|
| 820 |
s->msa = 0;
|
| 821 |
s->mcs = 0;
|
| 822 |
s->mdr = 0;
|
| 823 |
s->mtpr = 1;
|
| 824 |
s->mimr = 0;
|
| 825 |
s->mris = 0;
|
| 826 |
s->mcr = 0;
|
| 827 |
stellaris_i2c_update(s); |
| 828 |
} |
| 829 |
|
| 830 |
static CPUReadMemoryFunc *stellaris_i2c_readfn[] = {
|
| 831 |
stellaris_i2c_read, |
| 832 |
stellaris_i2c_read, |
| 833 |
stellaris_i2c_read |
| 834 |
}; |
| 835 |
|
| 836 |
static CPUWriteMemoryFunc *stellaris_i2c_writefn[] = {
|
| 837 |
stellaris_i2c_write, |
| 838 |
stellaris_i2c_write, |
| 839 |
stellaris_i2c_write |
| 840 |
}; |
| 841 |
|
| 842 |
static void stellaris_i2c_save(QEMUFile *f, void *opaque) |
| 843 |
{
|
| 844 |
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; |
| 845 |
|
| 846 |
qemu_put_be32(f, s->msa); |
| 847 |
qemu_put_be32(f, s->mcs); |
| 848 |
qemu_put_be32(f, s->mdr); |
| 849 |
qemu_put_be32(f, s->mtpr); |
| 850 |
qemu_put_be32(f, s->mimr); |
| 851 |
qemu_put_be32(f, s->mris); |
| 852 |
qemu_put_be32(f, s->mcr); |
| 853 |
} |
| 854 |
|
| 855 |
static int stellaris_i2c_load(QEMUFile *f, void *opaque, int version_id) |
| 856 |
{
|
| 857 |
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; |
| 858 |
|
| 859 |
if (version_id != 1) |
| 860 |
return -EINVAL;
|
| 861 |
|
| 862 |
s->msa = qemu_get_be32(f); |
| 863 |
s->mcs = qemu_get_be32(f); |
| 864 |
s->mdr = qemu_get_be32(f); |
| 865 |
s->mtpr = qemu_get_be32(f); |
| 866 |
s->mimr = qemu_get_be32(f); |
| 867 |
s->mris = qemu_get_be32(f); |
| 868 |
s->mcr = qemu_get_be32(f); |
| 869 |
|
| 870 |
return 0; |
| 871 |
} |
| 872 |
|
| 873 |
static void stellaris_i2c_init(uint32_t base, qemu_irq irq, i2c_bus *bus) |
| 874 |
{
|
| 875 |
stellaris_i2c_state *s; |
| 876 |
int iomemtype;
|
| 877 |
|
| 878 |
s = (stellaris_i2c_state *)qemu_mallocz(sizeof(stellaris_i2c_state));
|
| 879 |
s->irq = irq; |
| 880 |
s->bus = bus; |
| 881 |
|
| 882 |
iomemtype = cpu_register_io_memory(0, stellaris_i2c_readfn,
|
| 883 |
stellaris_i2c_writefn, s); |
| 884 |
cpu_register_physical_memory(base, 0x00001000, iomemtype);
|
| 885 |
/* ??? For now we only implement the master interface. */
|
| 886 |
stellaris_i2c_reset(s); |
| 887 |
register_savevm("stellaris_i2c", -1, 1, |
| 888 |
stellaris_i2c_save, stellaris_i2c_load, s); |
| 889 |
} |
| 890 |
|
| 891 |
/* Analogue to Digital Converter. This is only partially implemented,
|
| 892 |
enough for applications that use a combined ADC and timer tick. */
|
| 893 |
|
| 894 |
#define STELLARIS_ADC_EM_CONTROLLER 0 |
| 895 |
#define STELLARIS_ADC_EM_COMP 1 |
| 896 |
#define STELLARIS_ADC_EM_EXTERNAL 4 |
| 897 |
#define STELLARIS_ADC_EM_TIMER 5 |
| 898 |
#define STELLARIS_ADC_EM_PWM0 6 |
| 899 |
#define STELLARIS_ADC_EM_PWM1 7 |
| 900 |
#define STELLARIS_ADC_EM_PWM2 8 |
| 901 |
|
| 902 |
#define STELLARIS_ADC_FIFO_EMPTY 0x0100 |
| 903 |
#define STELLARIS_ADC_FIFO_FULL 0x1000 |
| 904 |
|
| 905 |
typedef struct |
| 906 |
{
|
| 907 |
uint32_t actss; |
| 908 |
uint32_t ris; |
| 909 |
uint32_t im; |
| 910 |
uint32_t emux; |
| 911 |
uint32_t ostat; |
| 912 |
uint32_t ustat; |
| 913 |
uint32_t sspri; |
| 914 |
uint32_t sac; |
| 915 |
struct {
|
| 916 |
uint32_t state; |
| 917 |
uint32_t data[16];
|
| 918 |
} fifo[4];
|
| 919 |
uint32_t ssmux[4];
|
| 920 |
uint32_t ssctl[4];
|
| 921 |
uint32_t noise; |
| 922 |
qemu_irq irq; |
| 923 |
} stellaris_adc_state; |
| 924 |
|
| 925 |
static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) |
| 926 |
{
|
| 927 |
int tail;
|
| 928 |
|
| 929 |
tail = s->fifo[n].state & 0xf;
|
| 930 |
if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
|
| 931 |
s->ustat |= 1 << n;
|
| 932 |
} else {
|
| 933 |
s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); |
| 934 |
s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; |
| 935 |
if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) |
| 936 |
s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; |
| 937 |
} |
| 938 |
return s->fifo[n].data[tail];
|
| 939 |
} |
| 940 |
|
| 941 |
static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, |
| 942 |
uint32_t value) |
| 943 |
{
|
| 944 |
int head;
|
| 945 |
|
| 946 |
head = (s->fifo[n].state >> 4) & 0xf; |
| 947 |
if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
|
| 948 |
s->ostat |= 1 << n;
|
| 949 |
return;
|
| 950 |
} |
| 951 |
s->fifo[n].data[head] = value; |
| 952 |
head = (head + 1) & 0xf; |
| 953 |
s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; |
| 954 |
s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); |
| 955 |
if ((s->fifo[n].state & 0xf) == head) |
| 956 |
s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; |
| 957 |
} |
| 958 |
|
| 959 |
static void stellaris_adc_update(stellaris_adc_state *s) |
| 960 |
{
|
| 961 |
int level;
|
| 962 |
|
| 963 |
level = (s->ris & s->im) != 0;
|
| 964 |
qemu_set_irq(s->irq, level); |
| 965 |
} |
| 966 |
|
| 967 |
static void stellaris_adc_trigger(void *opaque, int irq, int level) |
| 968 |
{
|
| 969 |
stellaris_adc_state *s = (stellaris_adc_state *)opaque; |
| 970 |
|
| 971 |
if ((s->actss & 1) == 0) { |
| 972 |
return;
|
| 973 |
} |
| 974 |
|
| 975 |
/* Some applications use the ADC as a random number source, so introduce
|
| 976 |
some variation into the signal. */
|
| 977 |
s->noise = s->noise * 314159 + 1; |
| 978 |
/* ??? actual inputs not implemented. Return an arbitrary value. */
|
| 979 |
stellaris_adc_fifo_write(s, 0, 0x200 + ((s->noise >> 16) & 7)); |
| 980 |
s->ris |= 1;
|
| 981 |
stellaris_adc_update(s); |
| 982 |
} |
| 983 |
|
| 984 |
static void stellaris_adc_reset(stellaris_adc_state *s) |
| 985 |
{
|
| 986 |
int n;
|
| 987 |
|
| 988 |
for (n = 0; n < 4; n++) { |
| 989 |
s->ssmux[n] = 0;
|
| 990 |
s->ssctl[n] = 0;
|
| 991 |
s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; |
| 992 |
} |
| 993 |
} |
| 994 |
|
| 995 |
static uint32_t stellaris_adc_read(void *opaque, target_phys_addr_t offset) |
| 996 |
{
|
| 997 |
stellaris_adc_state *s = (stellaris_adc_state *)opaque; |
| 998 |
|
| 999 |
/* TODO: Implement this. */
|
| 1000 |
if (offset >= 0x40 && offset < 0xc0) { |
| 1001 |
int n;
|
| 1002 |
n = (offset - 0x40) >> 5; |
| 1003 |
switch (offset & 0x1f) { |
| 1004 |
case 0x00: /* SSMUX */ |
| 1005 |
return s->ssmux[n];
|
| 1006 |
case 0x04: /* SSCTL */ |
| 1007 |
return s->ssctl[n];
|
| 1008 |
case 0x08: /* SSFIFO */ |
| 1009 |
return stellaris_adc_fifo_read(s, n);
|
| 1010 |
case 0x0c: /* SSFSTAT */ |
| 1011 |
return s->fifo[n].state;
|
| 1012 |
default:
|
| 1013 |
break;
|
| 1014 |
} |
| 1015 |
} |
| 1016 |
switch (offset) {
|
| 1017 |
case 0x00: /* ACTSS */ |
| 1018 |
return s->actss;
|
| 1019 |
case 0x04: /* RIS */ |
| 1020 |
return s->ris;
|
| 1021 |
case 0x08: /* IM */ |
| 1022 |
return s->im;
|
| 1023 |
case 0x0c: /* ISC */ |
| 1024 |
return s->ris & s->im;
|
| 1025 |
case 0x10: /* OSTAT */ |
| 1026 |
return s->ostat;
|
| 1027 |
case 0x14: /* EMUX */ |
| 1028 |
return s->emux;
|
| 1029 |
case 0x18: /* USTAT */ |
| 1030 |
return s->ustat;
|
| 1031 |
case 0x20: /* SSPRI */ |
| 1032 |
return s->sspri;
|
| 1033 |
case 0x30: /* SAC */ |
| 1034 |
return s->sac;
|
| 1035 |
default:
|
| 1036 |
hw_error("strllaris_adc_read: Bad offset 0x%x\n",
|
| 1037 |
(int)offset);
|
| 1038 |
return 0; |
| 1039 |
} |
| 1040 |
} |
| 1041 |
|
| 1042 |
static void stellaris_adc_write(void *opaque, target_phys_addr_t offset, |
| 1043 |
uint32_t value) |
| 1044 |
{
|
| 1045 |
stellaris_adc_state *s = (stellaris_adc_state *)opaque; |
| 1046 |
|
| 1047 |
/* TODO: Implement this. */
|
| 1048 |
if (offset >= 0x40 && offset < 0xc0) { |
| 1049 |
int n;
|
| 1050 |
n = (offset - 0x40) >> 5; |
| 1051 |
switch (offset & 0x1f) { |
| 1052 |
case 0x00: /* SSMUX */ |
| 1053 |
s->ssmux[n] = value & 0x33333333;
|
| 1054 |
return;
|
| 1055 |
case 0x04: /* SSCTL */ |
| 1056 |
if (value != 6) { |
| 1057 |
hw_error("ADC: Unimplemented sequence %x\n",
|
| 1058 |
value); |
| 1059 |
} |
| 1060 |
s->ssctl[n] = value; |
| 1061 |
return;
|
| 1062 |
default:
|
| 1063 |
break;
|
| 1064 |
} |
| 1065 |
} |
| 1066 |
switch (offset) {
|
| 1067 |
case 0x00: /* ACTSS */ |
| 1068 |
s->actss = value & 0xf;
|
| 1069 |
if (value & 0xe) { |
| 1070 |
hw_error("Not implemented: ADC sequencers 1-3\n");
|
| 1071 |
} |
| 1072 |
break;
|
| 1073 |
case 0x08: /* IM */ |
| 1074 |
s->im = value; |
| 1075 |
break;
|
| 1076 |
case 0x0c: /* ISC */ |
| 1077 |
s->ris &= ~value; |
| 1078 |
break;
|
| 1079 |
case 0x10: /* OSTAT */ |
| 1080 |
s->ostat &= ~value; |
| 1081 |
break;
|
| 1082 |
case 0x14: /* EMUX */ |
| 1083 |
s->emux = value; |
| 1084 |
break;
|
| 1085 |
case 0x18: /* USTAT */ |
| 1086 |
s->ustat &= ~value; |
| 1087 |
break;
|
| 1088 |
case 0x20: /* SSPRI */ |
| 1089 |
s->sspri = value; |
| 1090 |
break;
|
| 1091 |
case 0x28: /* PSSI */ |
| 1092 |
hw_error("Not implemented: ADC sample initiate\n");
|
| 1093 |
break;
|
| 1094 |
case 0x30: /* SAC */ |
| 1095 |
s->sac = value; |
| 1096 |
break;
|
| 1097 |
default:
|
| 1098 |
hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset); |
| 1099 |
} |
| 1100 |
stellaris_adc_update(s); |
| 1101 |
} |
| 1102 |
|
| 1103 |
static CPUReadMemoryFunc *stellaris_adc_readfn[] = {
|
| 1104 |
stellaris_adc_read, |
| 1105 |
stellaris_adc_read, |
| 1106 |
stellaris_adc_read |
| 1107 |
}; |
| 1108 |
|
| 1109 |
static CPUWriteMemoryFunc *stellaris_adc_writefn[] = {
|
| 1110 |
stellaris_adc_write, |
| 1111 |
stellaris_adc_write, |
| 1112 |
stellaris_adc_write |
| 1113 |
}; |
| 1114 |
|
| 1115 |
static void stellaris_adc_save(QEMUFile *f, void *opaque) |
| 1116 |
{
|
| 1117 |
stellaris_adc_state *s = (stellaris_adc_state *)opaque; |
| 1118 |
int i;
|
| 1119 |
int j;
|
| 1120 |
|
| 1121 |
qemu_put_be32(f, s->actss); |
| 1122 |
qemu_put_be32(f, s->ris); |
| 1123 |
qemu_put_be32(f, s->im); |
| 1124 |
qemu_put_be32(f, s->emux); |
| 1125 |
qemu_put_be32(f, s->ostat); |
| 1126 |
qemu_put_be32(f, s->ustat); |
| 1127 |
qemu_put_be32(f, s->sspri); |
| 1128 |
qemu_put_be32(f, s->sac); |
| 1129 |
for (i = 0; i < 4; i++) { |
| 1130 |
qemu_put_be32(f, s->fifo[i].state); |
| 1131 |
for (j = 0; j < 16; j++) { |
| 1132 |
qemu_put_be32(f, s->fifo[i].data[j]); |
| 1133 |
} |
| 1134 |
qemu_put_be32(f, s->ssmux[i]); |
| 1135 |
qemu_put_be32(f, s->ssctl[i]); |
| 1136 |
} |
| 1137 |
qemu_put_be32(f, s->noise); |
| 1138 |
} |
| 1139 |
|
| 1140 |
static int stellaris_adc_load(QEMUFile *f, void *opaque, int version_id) |
| 1141 |
{
|
| 1142 |
stellaris_adc_state *s = (stellaris_adc_state *)opaque; |
| 1143 |
int i;
|
| 1144 |
int j;
|
| 1145 |
|
| 1146 |
if (version_id != 1) |
| 1147 |
return -EINVAL;
|
| 1148 |
|
| 1149 |
s->actss = qemu_get_be32(f); |
| 1150 |
s->ris = qemu_get_be32(f); |
| 1151 |
s->im = qemu_get_be32(f); |
| 1152 |
s->emux = qemu_get_be32(f); |
| 1153 |
s->ostat = qemu_get_be32(f); |
| 1154 |
s->ustat = qemu_get_be32(f); |
| 1155 |
s->sspri = qemu_get_be32(f); |
| 1156 |
s->sac = qemu_get_be32(f); |
| 1157 |
for (i = 0; i < 4; i++) { |
| 1158 |
s->fifo[i].state = qemu_get_be32(f); |
| 1159 |
for (j = 0; j < 16; j++) { |
| 1160 |
s->fifo[i].data[j] = qemu_get_be32(f); |
| 1161 |
} |
| 1162 |
s->ssmux[i] = qemu_get_be32(f); |
| 1163 |
s->ssctl[i] = qemu_get_be32(f); |
| 1164 |
} |
| 1165 |
s->noise = qemu_get_be32(f); |
| 1166 |
|
| 1167 |
return 0; |
| 1168 |
} |
| 1169 |
|
| 1170 |
static qemu_irq stellaris_adc_init(uint32_t base, qemu_irq irq)
|
| 1171 |
{
|
| 1172 |
stellaris_adc_state *s; |
| 1173 |
int iomemtype;
|
| 1174 |
qemu_irq *qi; |
| 1175 |
|
| 1176 |
s = (stellaris_adc_state *)qemu_mallocz(sizeof(stellaris_adc_state));
|
| 1177 |
s->irq = irq; |
| 1178 |
|
| 1179 |
iomemtype = cpu_register_io_memory(0, stellaris_adc_readfn,
|
| 1180 |
stellaris_adc_writefn, s); |
| 1181 |
cpu_register_physical_memory(base, 0x00001000, iomemtype);
|
| 1182 |
stellaris_adc_reset(s); |
| 1183 |
qi = qemu_allocate_irqs(stellaris_adc_trigger, s, 1);
|
| 1184 |
register_savevm("stellaris_adc", -1, 1, |
| 1185 |
stellaris_adc_save, stellaris_adc_load, s); |
| 1186 |
return qi[0]; |
| 1187 |
} |
| 1188 |
|
| 1189 |
/* Some boards have both an OLED controller and SD card connected to
|
| 1190 |
the same SSI port, with the SD card chip select connected to a
|
| 1191 |
GPIO pin. Technically the OLED chip select is connected to the SSI
|
| 1192 |
Fss pin. We do not bother emulating that as both devices should
|
| 1193 |
never be selected simultaneously, and our OLED controller ignores stray
|
| 1194 |
0xff commands that occur when deselecting the SD card. */
|
| 1195 |
|
| 1196 |
typedef struct { |
| 1197 |
ssi_xfer_cb xfer_cb[2];
|
| 1198 |
void *opaque[2]; |
| 1199 |
qemu_irq irq; |
| 1200 |
int current_dev;
|
| 1201 |
} stellaris_ssi_bus_state; |
| 1202 |
|
| 1203 |
static void stellaris_ssi_bus_select(void *opaque, int irq, int level) |
| 1204 |
{
|
| 1205 |
stellaris_ssi_bus_state *s = (stellaris_ssi_bus_state *)opaque; |
| 1206 |
|
| 1207 |
s->current_dev = level; |
| 1208 |
} |
| 1209 |
|
| 1210 |
static int stellaris_ssi_bus_xfer(void *opaque, int val) |
| 1211 |
{
|
| 1212 |
stellaris_ssi_bus_state *s = (stellaris_ssi_bus_state *)opaque; |
| 1213 |
|
| 1214 |
return s->xfer_cb[s->current_dev](s->opaque[s->current_dev], val);
|
| 1215 |
} |
| 1216 |
|
| 1217 |
static void stellaris_ssi_bus_save(QEMUFile *f, void *opaque) |
| 1218 |
{
|
| 1219 |
stellaris_ssi_bus_state *s = (stellaris_ssi_bus_state *)opaque; |
| 1220 |
|
| 1221 |
qemu_put_be32(f, s->current_dev); |
| 1222 |
} |
| 1223 |
|
| 1224 |
static int stellaris_ssi_bus_load(QEMUFile *f, void *opaque, int version_id) |
| 1225 |
{
|
| 1226 |
stellaris_ssi_bus_state *s = (stellaris_ssi_bus_state *)opaque; |
| 1227 |
|
| 1228 |
if (version_id != 1) |
| 1229 |
return -EINVAL;
|
| 1230 |
|
| 1231 |
s->current_dev = qemu_get_be32(f); |
| 1232 |
|
| 1233 |
return 0; |
| 1234 |
} |
| 1235 |
|
| 1236 |
static void *stellaris_ssi_bus_init(qemu_irq *irqp, |
| 1237 |
ssi_xfer_cb cb0, void *opaque0,
|
| 1238 |
ssi_xfer_cb cb1, void *opaque1)
|
| 1239 |
{
|
| 1240 |
qemu_irq *qi; |
| 1241 |
stellaris_ssi_bus_state *s; |
| 1242 |
|
| 1243 |
s = (stellaris_ssi_bus_state *)qemu_mallocz(sizeof(stellaris_ssi_bus_state));
|
| 1244 |
s->xfer_cb[0] = cb0;
|
| 1245 |
s->opaque[0] = opaque0;
|
| 1246 |
s->xfer_cb[1] = cb1;
|
| 1247 |
s->opaque[1] = opaque1;
|
| 1248 |
qi = qemu_allocate_irqs(stellaris_ssi_bus_select, s, 1);
|
| 1249 |
*irqp = *qi; |
| 1250 |
register_savevm("stellaris_ssi_bus", -1, 1, |
| 1251 |
stellaris_ssi_bus_save, stellaris_ssi_bus_load, s); |
| 1252 |
return s;
|
| 1253 |
} |
| 1254 |
|
| 1255 |
/* Board init. */
|
| 1256 |
static stellaris_board_info stellaris_boards[] = {
|
| 1257 |
{ "LM3S811EVB",
|
| 1258 |
0,
|
| 1259 |
0x0032000e,
|
| 1260 |
0x001f001f, /* dc0 */ |
| 1261 |
0x001132bf,
|
| 1262 |
0x01071013,
|
| 1263 |
0x3f0f01ff,
|
| 1264 |
0x0000001f,
|
| 1265 |
BP_OLED_I2C |
| 1266 |
}, |
| 1267 |
{ "LM3S6965EVB",
|
| 1268 |
0x10010002,
|
| 1269 |
0x1073402e,
|
| 1270 |
0x00ff007f, /* dc0 */ |
| 1271 |
0x001133ff,
|
| 1272 |
0x030f5317,
|
| 1273 |
0x0f0f87ff,
|
| 1274 |
0x5000007f,
|
| 1275 |
BP_OLED_SSI | BP_GAMEPAD |
| 1276 |
} |
| 1277 |
}; |
| 1278 |
|
| 1279 |
static void stellaris_init(const char *kernel_filename, const char *cpu_model, |
| 1280 |
stellaris_board_info *board) |
| 1281 |
{
|
| 1282 |
static const int uart_irq[] = {5, 6, 33, 34}; |
| 1283 |
static const int timer_irq[] = {19, 21, 23, 35}; |
| 1284 |
static const uint32_t gpio_addr[7] = |
| 1285 |
{ 0x40004000, 0x40005000, 0x40006000, 0x40007000,
|
| 1286 |
0x40024000, 0x40025000, 0x40026000}; |
| 1287 |
static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; |
| 1288 |
|
| 1289 |
qemu_irq *pic; |
| 1290 |
qemu_irq *gpio_in[7];
|
| 1291 |
qemu_irq *gpio_out[7];
|
| 1292 |
qemu_irq adc; |
| 1293 |
int sram_size;
|
| 1294 |
int flash_size;
|
| 1295 |
i2c_bus *i2c; |
| 1296 |
int i;
|
| 1297 |
|
| 1298 |
flash_size = ((board->dc0 & 0xffff) + 1) << 1; |
| 1299 |
sram_size = (board->dc0 >> 18) + 1; |
| 1300 |
pic = armv7m_init(flash_size, sram_size, kernel_filename, cpu_model); |
| 1301 |
|
| 1302 |
if (board->dc1 & (1 << 16)) { |
| 1303 |
adc = stellaris_adc_init(0x40038000, pic[14]); |
| 1304 |
} else {
|
| 1305 |
adc = NULL;
|
| 1306 |
} |
| 1307 |
for (i = 0; i < 4; i++) { |
| 1308 |
if (board->dc2 & (0x10000 << i)) { |
| 1309 |
stellaris_gptm_init(0x40030000 + i * 0x1000, |
| 1310 |
pic[timer_irq[i]], adc); |
| 1311 |
} |
| 1312 |
} |
| 1313 |
|
| 1314 |
stellaris_sys_init(0x400fe000, pic[28], board, nd_table[0].macaddr); |
| 1315 |
|
| 1316 |
for (i = 0; i < 7; i++) { |
| 1317 |
if (board->dc4 & (1 << i)) { |
| 1318 |
gpio_in[i] = pl061_init(gpio_addr[i], pic[gpio_irq[i]], |
| 1319 |
&gpio_out[i]); |
| 1320 |
} |
| 1321 |
} |
| 1322 |
|
| 1323 |
if (board->dc2 & (1 << 12)) { |
| 1324 |
i2c = i2c_init_bus(); |
| 1325 |
stellaris_i2c_init(0x40020000, pic[8], i2c); |
| 1326 |
if (board->peripherals & BP_OLED_I2C) {
|
| 1327 |
ssd0303_init(i2c, 0x3d);
|
| 1328 |
} |
| 1329 |
} |
| 1330 |
|
| 1331 |
for (i = 0; i < 4; i++) { |
| 1332 |
if (board->dc2 & (1 << i)) { |
| 1333 |
pl011_init(0x4000c000 + i * 0x1000, pic[uart_irq[i]], |
| 1334 |
serial_hds[i], PL011_LUMINARY); |
| 1335 |
} |
| 1336 |
} |
| 1337 |
if (board->dc2 & (1 << 4)) { |
| 1338 |
if (board->peripherals & BP_OLED_SSI) {
|
| 1339 |
void * oled;
|
| 1340 |
void * sd;
|
| 1341 |
void *ssi_bus;
|
| 1342 |
int index;
|
| 1343 |
|
| 1344 |
oled = ssd0323_init(&gpio_out[GPIO_C][7]);
|
| 1345 |
index = drive_get_index(IF_SD, 0, 0); |
| 1346 |
sd = ssi_sd_init(drives_table[index].bdrv); |
| 1347 |
|
| 1348 |
ssi_bus = stellaris_ssi_bus_init(&gpio_out[GPIO_D][0],
|
| 1349 |
ssi_sd_xfer, sd, |
| 1350 |
ssd0323_xfer_ssi, oled); |
| 1351 |
|
| 1352 |
pl022_init(0x40008000, pic[7], stellaris_ssi_bus_xfer, ssi_bus); |
| 1353 |
/* Make sure the select pin is high. */
|
| 1354 |
qemu_irq_raise(gpio_out[GPIO_D][0]);
|
| 1355 |
} else {
|
| 1356 |
pl022_init(0x40008000, pic[7], NULL, NULL); |
| 1357 |
} |
| 1358 |
} |
| 1359 |
if (board->dc4 & (1 << 28)) |
| 1360 |
stellaris_enet_init(&nd_table[0], 0x40048000, pic[42]); |
| 1361 |
if (board->peripherals & BP_GAMEPAD) {
|
| 1362 |
qemu_irq gpad_irq[5];
|
| 1363 |
static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; |
| 1364 |
|
| 1365 |
gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ |
| 1366 |
gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ |
| 1367 |
gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ |
| 1368 |
gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ |
| 1369 |
gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ |
| 1370 |
|
| 1371 |
stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
|
| 1372 |
} |
| 1373 |
} |
| 1374 |
|
| 1375 |
/* FIXME: Figure out how to generate these from stellaris_boards. */
|
| 1376 |
static void lm3s811evb_init(ram_addr_t ram_size, |
| 1377 |
const char *boot_device, |
| 1378 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1379 |
const char *initrd_filename, const char *cpu_model) |
| 1380 |
{
|
| 1381 |
stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);
|
| 1382 |
} |
| 1383 |
|
| 1384 |
static void lm3s6965evb_init(ram_addr_t ram_size, |
| 1385 |
const char *boot_device, |
| 1386 |
const char *kernel_filename, const char *kernel_cmdline, |
| 1387 |
const char *initrd_filename, const char *cpu_model) |
| 1388 |
{
|
| 1389 |
stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);
|
| 1390 |
} |
| 1391 |
|
| 1392 |
QEMUMachine lm3s811evb_machine = {
|
| 1393 |
.name = "lm3s811evb",
|
| 1394 |
.desc = "Stellaris LM3S811EVB",
|
| 1395 |
.init = lm3s811evb_init, |
| 1396 |
}; |
| 1397 |
|
| 1398 |
QEMUMachine lm3s6965evb_machine = {
|
| 1399 |
.name = "lm3s6965evb",
|
| 1400 |
.desc = "Stellaris LM3S6965EVB",
|
| 1401 |
.init = lm3s6965evb_init, |
| 1402 |
}; |