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/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "pm_smbus.h" |
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#include "pci.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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#include "i2c.h" |
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#include "smbus.h" |
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//#define DEBUG
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/* i82731AB (PIIX4) compatible power management function */
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#define PM_FREQ 3579545 |
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#define ACPI_DBG_IO_ADDR 0xb044 |
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typedef struct PIIX4PMState { |
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PCIDevice dev; |
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uint16_t pmsts; |
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uint16_t pmen; |
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uint16_t pmcntrl; |
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uint8_t apmc; |
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uint8_t apms; |
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QEMUTimer *tmr_timer; |
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int64_t tmr_overflow_time; |
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PMSMBus smb; |
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qemu_irq irq; |
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qemu_irq cmos_s3; |
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qemu_irq smi_irq; |
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int kvm_enabled;
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} PIIX4PMState; |
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#define RSM_STS (1 << 15) |
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#define PWRBTN_STS (1 << 8) |
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#define RTC_EN (1 << 10) |
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#define PWRBTN_EN (1 << 8) |
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#define GBL_EN (1 << 5) |
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#define TMROF_EN (1 << 0) |
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#define SCI_EN (1 << 0) |
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#define SUS_EN (1 << 13) |
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#define ACPI_ENABLE 0xf1 |
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#define ACPI_DISABLE 0xf0 |
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static PIIX4PMState *pm_state;
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static uint32_t get_pmtmr(PIIX4PMState *s)
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{ |
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uint32_t d; |
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec()); |
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return d & 0xffffff; |
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} |
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static int get_pmsts(PIIX4PMState *s) |
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{ |
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int64_t d; |
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec()); |
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if (d >= s->tmr_overflow_time)
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s->pmsts |= TMROF_EN; |
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return s->pmsts;
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} |
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static void pm_update_sci(PIIX4PMState *s) |
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{ |
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int sci_level, pmsts;
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int64_t expire_time; |
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pmsts = get_pmsts(s); |
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sci_level = (((pmsts & s->pmen) & |
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(RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
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qemu_set_irq(s->irq, sci_level); |
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/* schedule a timer interruption if needed */
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if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
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expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(), PM_FREQ); |
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qemu_mod_timer(s->tmr_timer, expire_time); |
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} else {
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qemu_del_timer(s->tmr_timer); |
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} |
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} |
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static void pm_tmr_timer(void *opaque) |
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{ |
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PIIX4PMState *s = opaque; |
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pm_update_sci(s); |
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} |
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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PIIX4PMState *s = opaque; |
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addr &= 0x3f;
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switch(addr) {
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case 0x00: |
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{ |
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int64_t d; |
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int pmsts;
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pmsts = get_pmsts(s); |
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if (pmsts & val & TMROF_EN) {
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/* if TMRSTS is reset, then compute the new overflow time */
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, |
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get_ticks_per_sec()); |
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s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; |
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} |
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s->pmsts &= ~val; |
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pm_update_sci(s); |
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} |
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break;
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case 0x02: |
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s->pmen = val; |
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pm_update_sci(s); |
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break;
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case 0x04: |
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{ |
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int sus_typ;
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s->pmcntrl = val & ~(SUS_EN); |
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if (val & SUS_EN) {
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/* change suspend type */
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sus_typ = (val >> 10) & 7; |
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switch(sus_typ) {
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case 0: /* soft power off */ |
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qemu_system_shutdown_request(); |
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break;
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case 1: |
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/* RSM_STS should be set on resume. Pretend that resume
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was caused by power button */
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s->pmsts |= (RSM_STS | PWRBTN_STS); |
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qemu_system_reset_request(); |
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if (s->cmos_s3) {
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qemu_irq_raise(s->cmos_s3); |
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} |
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default:
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break;
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} |
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} |
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} |
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break;
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default:
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break;
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} |
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#ifdef DEBUG
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printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
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#endif
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} |
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) |
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{ |
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PIIX4PMState *s = opaque; |
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uint32_t val; |
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addr &= 0x3f;
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switch(addr) {
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case 0x00: |
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val = get_pmsts(s); |
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break;
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case 0x02: |
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val = s->pmen; |
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break;
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case 0x04: |
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val = s->pmcntrl; |
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break;
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default:
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val = 0;
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break;
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} |
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#ifdef DEBUG
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printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
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#endif
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return val;
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} |
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static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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// PIIX4PMState *s = opaque;
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#ifdef DEBUG
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addr &= 0x3f;
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printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
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#endif
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} |
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static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) |
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{ |
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PIIX4PMState *s = opaque; |
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uint32_t val; |
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addr &= 0x3f;
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switch(addr) {
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case 0x08: |
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val = get_pmtmr(s); |
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break;
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default:
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val = 0;
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break;
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} |
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#ifdef DEBUG
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printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
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#endif
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return val;
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} |
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static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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PIIX4PMState *s = opaque; |
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addr &= 1;
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#ifdef DEBUG
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printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
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#endif
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if (addr == 0) { |
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s->apmc = val; |
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/* ACPI specs 3.0, 4.7.2.5 */
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if (val == ACPI_ENABLE) {
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s->pmcntrl |= SCI_EN; |
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} else if (val == ACPI_DISABLE) { |
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s->pmcntrl &= ~SCI_EN; |
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} |
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if (s->dev.config[0x5b] & (1 << 1)) { |
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if (s->smi_irq) {
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qemu_irq_raise(s->smi_irq); |
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} |
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} |
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} else {
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s->apms = val; |
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} |
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} |
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static uint32_t pm_smi_readb(void *opaque, uint32_t addr) |
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{ |
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PIIX4PMState *s = opaque; |
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uint32_t val; |
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addr &= 1;
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if (addr == 0) { |
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val = s->apmc; |
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} else {
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val = s->apms; |
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} |
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#ifdef DEBUG
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printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
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#endif
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return val;
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} |
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static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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#if defined(DEBUG)
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printf("ACPI: DBG: 0x%08x\n", val);
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#endif
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} |
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static void pm_io_space_update(PIIX4PMState *s) |
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{ |
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uint32_t pm_io_base; |
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if (s->dev.config[0x80] & 1) { |
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pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
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pm_io_base &= 0xffc0;
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/* XXX: need to improve memory and ioport allocation */
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#if defined(DEBUG)
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printf("PM: mapping to 0x%x\n", pm_io_base);
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#endif
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register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); |
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register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); |
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register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); |
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register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); |
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} |
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} |
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static void pm_write_config(PCIDevice *d, |
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uint32_t address, uint32_t val, int len)
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{ |
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pci_default_write_config(d, address, val, len); |
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if (range_covers_byte(address, len, 0x80)) |
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pm_io_space_update((PIIX4PMState *)d); |
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} |
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static int vmstate_acpi_post_load(void *opaque, int version_id) |
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{ |
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PIIX4PMState *s = opaque; |
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pm_io_space_update(s); |
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return 0; |
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} |
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static const VMStateDescription vmstate_acpi = { |
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.name = "piix4_pm",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = vmstate_acpi_post_load, |
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.fields = (VMStateField []) { |
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VMSTATE_PCI_DEVICE(dev, PIIX4PMState), |
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VMSTATE_UINT16(pmsts, PIIX4PMState), |
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VMSTATE_UINT16(pmen, PIIX4PMState), |
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VMSTATE_UINT16(pmcntrl, PIIX4PMState), |
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VMSTATE_UINT8(apmc, PIIX4PMState), |
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VMSTATE_UINT8(apms, PIIX4PMState), |
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VMSTATE_TIMER(tmr_timer, PIIX4PMState), |
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VMSTATE_INT64(tmr_overflow_time, PIIX4PMState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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static void piix4_reset(void *opaque) |
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{ |
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PIIX4PMState *s = opaque; |
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uint8_t *pci_conf = s->dev.config; |
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pci_conf[0x58] = 0; |
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pci_conf[0x59] = 0; |
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pci_conf[0x5a] = 0; |
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pci_conf[0x5b] = 0; |
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if (s->kvm_enabled) {
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/* Mark SMM as already inited (until KVM supports SMM). */
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pci_conf[0x5B] = 0x02; |
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} |
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} |
341 |
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static void piix4_powerdown(void *opaque, int irq, int power_failing) |
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{ |
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PIIX4PMState *s = opaque; |
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if (!s) {
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qemu_system_shutdown_request(); |
348 |
} else if (s->pmen & PWRBTN_EN) { |
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s->pmsts |= PWRBTN_EN; |
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pm_update_sci(s); |
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} |
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} |
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i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq, |
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int kvm_enabled)
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{ |
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PIIX4PMState *s; |
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uint8_t *pci_conf; |
360 |
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s = (PIIX4PMState *)pci_register_device(bus, |
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"PM", sizeof(PIIX4PMState), |
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devfn, NULL, pm_write_config);
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pm_state = s; |
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pci_conf = s->dev.config; |
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
367 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3); |
368 |
pci_conf[0x06] = 0x80; |
369 |
pci_conf[0x07] = 0x02; |
370 |
pci_conf[0x08] = 0x03; // revision number |
371 |
pci_conf[0x09] = 0x00; |
372 |
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); |
373 |
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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pci_conf[0x3d] = 0x01; // interrupt pin 1 |
375 |
|
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pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
377 |
|
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register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s); |
379 |
register_ioport_read(0xb2, 2, 1, pm_smi_readb, s); |
380 |
|
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register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); |
382 |
|
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s->kvm_enabled = kvm_enabled; |
384 |
if (s->kvm_enabled) {
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/* Mark SMM as already inited to prevent SMM from running. KVM does not
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* support SMM mode. */
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pci_conf[0x5B] = 0x02; |
388 |
} |
389 |
|
390 |
/* XXX: which specification is used ? The i82731AB has different
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391 |
mappings */
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392 |
pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10; |
393 |
pci_conf[0x63] = 0x60; |
394 |
pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) | |
395 |
(serial_hds[1] != NULL ? 0x90 : 0); |
396 |
|
397 |
pci_conf[0x90] = smb_io_base | 1; |
398 |
pci_conf[0x91] = smb_io_base >> 8; |
399 |
pci_conf[0xd2] = 0x09; |
400 |
register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, &s->smb); |
401 |
register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, &s->smb); |
402 |
|
403 |
s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); |
404 |
|
405 |
qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
|
406 |
|
407 |
vmstate_register(0, &vmstate_acpi, s);
|
408 |
|
409 |
pm_smbus_init(NULL, &s->smb);
|
410 |
s->irq = sci_irq; |
411 |
s->cmos_s3 = cmos_s3; |
412 |
s->smi_irq = smi_irq; |
413 |
qemu_register_reset(piix4_reset, s); |
414 |
|
415 |
return s->smb.smbus;
|
416 |
} |
417 |
|
418 |
#define GPE_BASE 0xafe0 |
419 |
#define PCI_BASE 0xae00 |
420 |
#define PCI_EJ_BASE 0xae08 |
421 |
|
422 |
struct gpe_regs {
|
423 |
uint16_t sts; /* status */
|
424 |
uint16_t en; /* enabled */
|
425 |
}; |
426 |
|
427 |
struct pci_status {
|
428 |
uint32_t up; |
429 |
uint32_t down; |
430 |
}; |
431 |
|
432 |
static struct gpe_regs gpe; |
433 |
static struct pci_status pci0_status; |
434 |
|
435 |
static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
|
436 |
{ |
437 |
if (addr & 1) |
438 |
return (val >> 8) & 0xff; |
439 |
return val & 0xff; |
440 |
} |
441 |
|
442 |
static uint32_t gpe_readb(void *opaque, uint32_t addr) |
443 |
{ |
444 |
uint32_t val = 0;
|
445 |
struct gpe_regs *g = opaque;
|
446 |
switch (addr) {
|
447 |
case GPE_BASE:
|
448 |
case GPE_BASE + 1: |
449 |
val = gpe_read_val(g->sts, addr); |
450 |
break;
|
451 |
case GPE_BASE + 2: |
452 |
case GPE_BASE + 3: |
453 |
val = gpe_read_val(g->en, addr); |
454 |
break;
|
455 |
default:
|
456 |
break;
|
457 |
} |
458 |
|
459 |
#if defined(DEBUG)
|
460 |
printf("gpe read %x == %x\n", addr, val);
|
461 |
#endif
|
462 |
return val;
|
463 |
} |
464 |
|
465 |
static void gpe_write_val(uint16_t *cur, int addr, uint32_t val) |
466 |
{ |
467 |
if (addr & 1) |
468 |
*cur = (*cur & 0xff) | (val << 8); |
469 |
else
|
470 |
*cur = (*cur & 0xff00) | (val & 0xff); |
471 |
} |
472 |
|
473 |
static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val) |
474 |
{ |
475 |
uint16_t x1, x0 = val & 0xff;
|
476 |
int shift = (addr & 1) ? 8 : 0; |
477 |
|
478 |
x1 = (*cur >> shift) & 0xff;
|
479 |
|
480 |
x1 = x1 & ~x0; |
481 |
|
482 |
*cur = (*cur & (0xff << (8 - shift))) | (x1 << shift); |
483 |
} |
484 |
|
485 |
static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
486 |
{ |
487 |
struct gpe_regs *g = opaque;
|
488 |
switch (addr) {
|
489 |
case GPE_BASE:
|
490 |
case GPE_BASE + 1: |
491 |
gpe_reset_val(&g->sts, addr, val); |
492 |
break;
|
493 |
case GPE_BASE + 2: |
494 |
case GPE_BASE + 3: |
495 |
gpe_write_val(&g->en, addr, val); |
496 |
break;
|
497 |
default:
|
498 |
break;
|
499 |
} |
500 |
|
501 |
#if defined(DEBUG)
|
502 |
printf("gpe write %x <== %d\n", addr, val);
|
503 |
#endif
|
504 |
} |
505 |
|
506 |
static uint32_t pcihotplug_read(void *opaque, uint32_t addr) |
507 |
{ |
508 |
uint32_t val = 0;
|
509 |
struct pci_status *g = opaque;
|
510 |
switch (addr) {
|
511 |
case PCI_BASE:
|
512 |
val = g->up; |
513 |
break;
|
514 |
case PCI_BASE + 4: |
515 |
val = g->down; |
516 |
break;
|
517 |
default:
|
518 |
break;
|
519 |
} |
520 |
|
521 |
#if defined(DEBUG)
|
522 |
printf("pcihotplug read %x == %x\n", addr, val);
|
523 |
#endif
|
524 |
return val;
|
525 |
} |
526 |
|
527 |
static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val) |
528 |
{ |
529 |
struct pci_status *g = opaque;
|
530 |
switch (addr) {
|
531 |
case PCI_BASE:
|
532 |
g->up = val; |
533 |
break;
|
534 |
case PCI_BASE + 4: |
535 |
g->down = val; |
536 |
break;
|
537 |
} |
538 |
|
539 |
#if defined(DEBUG)
|
540 |
printf("pcihotplug write %x <== %d\n", addr, val);
|
541 |
#endif
|
542 |
} |
543 |
|
544 |
static uint32_t pciej_read(void *opaque, uint32_t addr) |
545 |
{ |
546 |
#if defined(DEBUG)
|
547 |
printf("pciej read %x\n", addr);
|
548 |
#endif
|
549 |
return 0; |
550 |
} |
551 |
|
552 |
static void pciej_write(void *opaque, uint32_t addr, uint32_t val) |
553 |
{ |
554 |
BusState *bus = opaque; |
555 |
DeviceState *qdev, *next; |
556 |
PCIDevice *dev; |
557 |
int slot = ffs(val) - 1; |
558 |
|
559 |
QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) { |
560 |
dev = DO_UPCAST(PCIDevice, qdev, qdev); |
561 |
if (PCI_SLOT(dev->devfn) == slot) {
|
562 |
qdev_free(qdev); |
563 |
} |
564 |
} |
565 |
|
566 |
|
567 |
#if defined(DEBUG)
|
568 |
printf("pciej write %x <== %d\n", addr, val);
|
569 |
#endif
|
570 |
} |
571 |
|
572 |
static int piix4_device_hotplug(PCIDevice *dev, int state); |
573 |
|
574 |
void piix4_acpi_system_hot_add_init(PCIBus *bus)
|
575 |
{ |
576 |
register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe); |
577 |
register_ioport_read(GPE_BASE, 4, 1, gpe_readb, &gpe); |
578 |
|
579 |
register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status); |
580 |
register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, &pci0_status); |
581 |
|
582 |
register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus); |
583 |
register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, bus); |
584 |
|
585 |
pci_bus_hotplug(bus, piix4_device_hotplug); |
586 |
} |
587 |
|
588 |
static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot) |
589 |
{ |
590 |
g->sts |= 2;
|
591 |
p->up |= (1 << slot);
|
592 |
} |
593 |
|
594 |
static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot) |
595 |
{ |
596 |
g->sts |= 2;
|
597 |
p->down |= (1 << slot);
|
598 |
} |
599 |
|
600 |
static int piix4_device_hotplug(PCIDevice *dev, int state) |
601 |
{ |
602 |
int slot = PCI_SLOT(dev->devfn);
|
603 |
|
604 |
pci0_status.up = 0;
|
605 |
pci0_status.down = 0;
|
606 |
if (state)
|
607 |
enable_device(&pci0_status, &gpe, slot); |
608 |
else
|
609 |
disable_device(&pci0_status, &gpe, slot); |
610 |
if (gpe.en & 2) { |
611 |
qemu_set_irq(pm_state->irq, 1);
|
612 |
qemu_set_irq(pm_state->irq, 0);
|
613 |
} |
614 |
return 0; |
615 |
} |
616 |
|
617 |
struct acpi_table_header
|
618 |
{ |
619 |
char signature [4]; /* ACPI signature (4 ASCII characters) */ |
620 |
uint32_t length; /* Length of table, in bytes, including header */
|
621 |
uint8_t revision; /* ACPI Specification minor version # */
|
622 |
uint8_t checksum; /* To make sum of entire table == 0 */
|
623 |
char oem_id [6]; /* OEM identification */ |
624 |
char oem_table_id [8]; /* OEM table identification */ |
625 |
uint32_t oem_revision; /* OEM revision number */
|
626 |
char asl_compiler_id [4]; /* ASL compiler vendor ID */ |
627 |
uint32_t asl_compiler_revision; /* ASL compiler revision number */
|
628 |
} __attribute__((packed)); |
629 |
|
630 |
char *acpi_tables;
|
631 |
size_t acpi_tables_len; |
632 |
|
633 |
static int acpi_checksum(const uint8_t *data, int len) |
634 |
{ |
635 |
int sum, i;
|
636 |
sum = 0;
|
637 |
for(i = 0; i < len; i++) |
638 |
sum += data[i]; |
639 |
return (-sum) & 0xff; |
640 |
} |
641 |
|
642 |
int acpi_table_add(const char *t) |
643 |
{ |
644 |
static const char *dfl_id = "QEMUQEMU"; |
645 |
char buf[1024], *p, *f; |
646 |
struct acpi_table_header acpi_hdr;
|
647 |
unsigned long val; |
648 |
size_t off; |
649 |
|
650 |
memset(&acpi_hdr, 0, sizeof(acpi_hdr)); |
651 |
|
652 |
if (get_param_value(buf, sizeof(buf), "sig", t)) { |
653 |
strncpy(acpi_hdr.signature, buf, 4);
|
654 |
} else {
|
655 |
strncpy(acpi_hdr.signature, dfl_id, 4);
|
656 |
} |
657 |
if (get_param_value(buf, sizeof(buf), "rev", t)) { |
658 |
val = strtoul(buf, &p, 10);
|
659 |
if (val > 255 || *p != '\0') |
660 |
goto out;
|
661 |
} else {
|
662 |
val = 1;
|
663 |
} |
664 |
acpi_hdr.revision = (int8_t)val; |
665 |
|
666 |
if (get_param_value(buf, sizeof(buf), "oem_id", t)) { |
667 |
strncpy(acpi_hdr.oem_id, buf, 6);
|
668 |
} else {
|
669 |
strncpy(acpi_hdr.oem_id, dfl_id, 6);
|
670 |
} |
671 |
|
672 |
if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) { |
673 |
strncpy(acpi_hdr.oem_table_id, buf, 8);
|
674 |
} else {
|
675 |
strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
|
676 |
} |
677 |
|
678 |
if (get_param_value(buf, sizeof(buf), "oem_rev", t)) { |
679 |
val = strtol(buf, &p, 10);
|
680 |
if(*p != '\0') |
681 |
goto out;
|
682 |
} else {
|
683 |
val = 1;
|
684 |
} |
685 |
acpi_hdr.oem_revision = cpu_to_le32(val); |
686 |
|
687 |
if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) { |
688 |
strncpy(acpi_hdr.asl_compiler_id, buf, 4);
|
689 |
} else {
|
690 |
strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
|
691 |
} |
692 |
|
693 |
if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) { |
694 |
val = strtol(buf, &p, 10);
|
695 |
if(*p != '\0') |
696 |
goto out;
|
697 |
} else {
|
698 |
val = 1;
|
699 |
} |
700 |
acpi_hdr.asl_compiler_revision = cpu_to_le32(val); |
701 |
|
702 |
if (!get_param_value(buf, sizeof(buf), "data", t)) { |
703 |
buf[0] = '\0'; |
704 |
} |
705 |
|
706 |
acpi_hdr.length = sizeof(acpi_hdr);
|
707 |
|
708 |
f = buf; |
709 |
while (buf[0]) { |
710 |
struct stat s;
|
711 |
char *n = strchr(f, ':'); |
712 |
if (n)
|
713 |
*n = '\0';
|
714 |
if(stat(f, &s) < 0) { |
715 |
fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
|
716 |
goto out;
|
717 |
} |
718 |
acpi_hdr.length += s.st_size; |
719 |
if (!n)
|
720 |
break;
|
721 |
*n = ':';
|
722 |
f = n + 1;
|
723 |
} |
724 |
|
725 |
if (!acpi_tables) {
|
726 |
acpi_tables_len = sizeof(uint16_t);
|
727 |
acpi_tables = qemu_mallocz(acpi_tables_len); |
728 |
} |
729 |
p = acpi_tables + acpi_tables_len; |
730 |
acpi_tables_len += sizeof(uint16_t) + acpi_hdr.length;
|
731 |
acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len); |
732 |
|
733 |
acpi_hdr.length = cpu_to_le32(acpi_hdr.length); |
734 |
*(uint16_t*)p = acpi_hdr.length; |
735 |
p += sizeof(uint16_t);
|
736 |
memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
|
737 |
off = sizeof(acpi_hdr);
|
738 |
|
739 |
f = buf; |
740 |
while (buf[0]) { |
741 |
struct stat s;
|
742 |
int fd;
|
743 |
char *n = strchr(f, ':'); |
744 |
if (n)
|
745 |
*n = '\0';
|
746 |
fd = open(f, O_RDONLY); |
747 |
|
748 |
if(fd < 0) |
749 |
goto out;
|
750 |
if(fstat(fd, &s) < 0) { |
751 |
close(fd); |
752 |
goto out;
|
753 |
} |
754 |
|
755 |
do {
|
756 |
int r;
|
757 |
r = read(fd, p + off, s.st_size); |
758 |
if (r > 0) { |
759 |
off += r; |
760 |
s.st_size -= r; |
761 |
} else if ((r < 0 && errno != EINTR) || r == 0) { |
762 |
close(fd); |
763 |
goto out;
|
764 |
} |
765 |
} while(s.st_size);
|
766 |
|
767 |
close(fd); |
768 |
if (!n)
|
769 |
break;
|
770 |
f = n + 1;
|
771 |
} |
772 |
|
773 |
((struct acpi_table_header*)p)->checksum = acpi_checksum((uint8_t*)p, off);
|
774 |
/* increase number of tables */
|
775 |
(*(uint16_t*)acpi_tables) = |
776 |
cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
|
777 |
return 0; |
778 |
out:
|
779 |
if (acpi_tables) {
|
780 |
qemu_free(acpi_tables); |
781 |
acpi_tables = NULL;
|
782 |
} |
783 |
return -1; |
784 |
} |