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/*
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 *  MIPS emulation micro-operations for qemu.
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 * 
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 *  Copyright (c) 2004-2005 Jocelyn Mayer
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 *  Copyright (c) 2006 Marius Groeger (FPU operations)
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "config.h"
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#include "exec.h"
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#ifndef CALL_FROM_TB0
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#define CALL_FROM_TB0(func) func();
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#endif
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#ifndef CALL_FROM_TB1
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#define CALL_FROM_TB1(func, arg0) func(arg0);
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#endif
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#ifndef CALL_FROM_TB1_CONST16
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#define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0);
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#endif
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#ifndef CALL_FROM_TB2
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#define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1);
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#endif
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#ifndef CALL_FROM_TB2_CONST16
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#define CALL_FROM_TB2_CONST16(func, arg0, arg1)     \
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CALL_FROM_TB2(func, arg0, arg1);
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#endif
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#ifndef CALL_FROM_TB3
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#define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2);
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#endif
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#ifndef CALL_FROM_TB4
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#define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
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        func(arg0, arg1, arg2, arg3);
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#endif
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#define REG 1
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#include "op_template.c"
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#undef REG
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#define REG 2
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#include "op_template.c"
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#undef REG
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#define REG 3
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#include "op_template.c"
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#undef REG
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#define REG 4
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#include "op_template.c"
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#undef REG
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#define REG 5
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#include "op_template.c"
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#undef REG
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#define REG 6
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#include "op_template.c"
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#undef REG
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#define REG 7
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#include "op_template.c"
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#undef REG
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#define REG 8
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#include "op_template.c"
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#undef REG
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#define REG 9
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#include "op_template.c"
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#undef REG
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#define REG 10
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#include "op_template.c"
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#undef REG
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#define REG 11
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#include "op_template.c"
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#undef REG
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#define REG 12
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#include "op_template.c"
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#undef REG
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#define REG 13
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#include "op_template.c"
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#undef REG
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#define REG 14
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#include "op_template.c"
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#undef REG
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#define REG 15
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#include "op_template.c"
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#undef REG
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#define REG 16
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#include "op_template.c"
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#undef REG
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#define REG 17
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#include "op_template.c"
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#undef REG
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#define REG 18
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#include "op_template.c"
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#undef REG
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#define REG 19
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#include "op_template.c"
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#undef REG
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#define REG 20
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#include "op_template.c"
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#undef REG
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#define REG 21
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#include "op_template.c"
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#undef REG
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#define REG 22
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#include "op_template.c"
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#undef REG
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#define REG 23
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#include "op_template.c"
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#undef REG
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#define REG 24
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#include "op_template.c"
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#undef REG
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#define REG 25
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#include "op_template.c"
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#undef REG
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#define REG 26
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#include "op_template.c"
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#undef REG
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#define REG 27
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#include "op_template.c"
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#undef REG
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#define REG 28
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#include "op_template.c"
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#undef REG
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#define REG 29
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#include "op_template.c"
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#undef REG
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#define REG 30
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#include "op_template.c"
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#undef REG
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#define REG 31
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#include "op_template.c"
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#undef REG
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#define TN
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#include "op_template.c"
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#undef TN
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#define SFREG 0
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#define DFREG 0
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 1
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 2
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#define DFREG 2
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 3
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 4
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#define DFREG 4
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 5
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 6
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#define DFREG 6
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 7
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 8
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#define DFREG 8
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 9
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 10
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#define DFREG 10
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 11
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 12
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#define DFREG 12
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 13
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 14
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#define DFREG 14
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 15
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 16
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#define DFREG 16
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 17
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 18
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#define DFREG 18
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 19
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 20
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#define DFREG 20
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 21
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 22
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#define DFREG 22
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 23
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 24
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#define DFREG 24
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 25
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 26
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#define DFREG 26
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 27
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 28
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#define DFREG 28
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 29
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#include "fop_template.c"
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#undef SFREG
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#define SFREG 30
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#define DFREG 30
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#include "fop_template.c"
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#undef SFREG
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#undef DFREG
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#define SFREG 31
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#include "fop_template.c"
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#undef SFREG
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#define FTN
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#include "fop_template.c"
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#undef FTN
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void op_dup_T0 (void)
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{
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    T2 = T0;
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    RETURN();
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}
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void op_load_HI (void)
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{
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    T0 = env->HI;
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    RETURN();
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}
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void op_store_HI (void)
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{
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    env->HI = T0;
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    RETURN();
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}
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void op_load_LO (void)
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{
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    T0 = env->LO;
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    RETURN();
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}
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void op_store_LO (void)
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{
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    env->LO = T0;
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    RETURN();
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}
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/* Load and store */
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#define MEMSUFFIX _raw
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#include "op_mem.c"
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#undef MEMSUFFIX
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_mem.c"
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#undef MEMSUFFIX
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#define MEMSUFFIX _kernel
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#include "op_mem.c"
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#undef MEMSUFFIX
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#endif
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/* Arithmetic */
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void op_add (void)
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{
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    T0 = (int32_t)((int32_t)T0 + (int32_t)T1);
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    RETURN();
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}
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void op_addo (void)
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{
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    target_ulong tmp;
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    tmp = (int32_t)T0;
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    T0 = (int32_t)T0 + (int32_t)T1;
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    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
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        /* operands of same sign, result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
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    T0 = (int32_t)T0;
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    RETURN();
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}
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void op_sub (void)
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{
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    T0 = (int32_t)((int32_t)T0 - (int32_t)T1);
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    RETURN();
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}
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void op_subo (void)
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{
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    target_ulong tmp;
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    tmp = (int32_t)T0;
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    T0 = (int32_t)T0 - (int32_t)T1;
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    if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
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        /* operands of different sign, first operand and result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
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    T0 = (int32_t)T0;
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    RETURN();
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}
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void op_mul (void)
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{
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    T0 = (int32_t)((int32_t)T0 * (int32_t)T1);
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    RETURN();
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}
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#if HOST_LONG_BITS < 64
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void op_div (void)
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{
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    CALL_FROM_TB0(do_div);
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    RETURN();
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}
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#else
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void op_div (void)
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{
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    if (T1 != 0) {
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        env->LO = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
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        env->HI = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
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    }
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    RETURN();
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}
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#endif
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void op_divu (void)
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{
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    if (T1 != 0) {
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        env->LO = (int32_t)((uint32_t)T0 / (uint32_t)T1);
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        env->HI = (int32_t)((uint32_t)T0 % (uint32_t)T1);
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    }
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    RETURN();
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}
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#ifdef TARGET_MIPS64
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/* Arithmetic */
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void op_dadd (void)
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{
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    T0 += T1;
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    RETURN();
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}
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void op_daddo (void)
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{
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    target_long tmp;
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    tmp = T0;
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    T0 += T1;
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    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) {
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        /* operands of same sign, result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
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    RETURN();
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}
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void op_dsub (void)
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{
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    T0 -= T1;
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    RETURN();
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}
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void op_dsubo (void)
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{
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    target_long tmp;
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    tmp = T0;
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    T0 = (int64_t)T0 - (int64_t)T1;
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    if (((tmp ^ T1) & (tmp ^ T0)) >> 63) {
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        /* operands of different sign, first operand and result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
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    RETURN();
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}
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void op_dmul (void)
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{
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    T0 = (int64_t)T0 * (int64_t)T1;
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    RETURN();
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}
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/* Those might call libgcc functions.  */
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void op_ddiv (void)
445 c570fd16 ths
{
446 c570fd16 ths
    do_ddiv();
447 c570fd16 ths
    RETURN();
448 c570fd16 ths
}
449 c570fd16 ths
450 80c27194 ths
#if TARGET_LONG_BITS > HOST_LONG_BITS
451 c570fd16 ths
void op_ddivu (void)
452 c570fd16 ths
{
453 c570fd16 ths
    do_ddivu();
454 c570fd16 ths
    RETURN();
455 c570fd16 ths
}
456 c570fd16 ths
#else
457 c570fd16 ths
void op_ddivu (void)
458 c570fd16 ths
{
459 c570fd16 ths
    if (T1 != 0) {
460 6af0bf9c bellard
        env->LO = T0 / T1;
461 6af0bf9c bellard
        env->HI = T0 % T1;
462 6af0bf9c bellard
    }
463 6af0bf9c bellard
    RETURN();
464 6af0bf9c bellard
}
465 c570fd16 ths
#endif
466 60aa19ab ths
#endif /* TARGET_MIPS64 */
467 6af0bf9c bellard
468 6af0bf9c bellard
/* Logical */
469 6af0bf9c bellard
void op_and (void)
470 6af0bf9c bellard
{
471 6af0bf9c bellard
    T0 &= T1;
472 6af0bf9c bellard
    RETURN();
473 6af0bf9c bellard
}
474 6af0bf9c bellard
475 6af0bf9c bellard
void op_nor (void)
476 6af0bf9c bellard
{
477 6af0bf9c bellard
    T0 = ~(T0 | T1);
478 6af0bf9c bellard
    RETURN();
479 6af0bf9c bellard
}
480 6af0bf9c bellard
481 6af0bf9c bellard
void op_or (void)
482 6af0bf9c bellard
{
483 6af0bf9c bellard
    T0 |= T1;
484 6af0bf9c bellard
    RETURN();
485 6af0bf9c bellard
}
486 6af0bf9c bellard
487 6af0bf9c bellard
void op_xor (void)
488 6af0bf9c bellard
{
489 6af0bf9c bellard
    T0 ^= T1;
490 6af0bf9c bellard
    RETURN();
491 6af0bf9c bellard
}
492 6af0bf9c bellard
493 6af0bf9c bellard
void op_sll (void)
494 6af0bf9c bellard
{
495 5a63bcb2 ths
    T0 = (int32_t)((uint32_t)T0 << T1);
496 6af0bf9c bellard
    RETURN();
497 6af0bf9c bellard
}
498 6af0bf9c bellard
499 6af0bf9c bellard
void op_sra (void)
500 6af0bf9c bellard
{
501 5a63bcb2 ths
    T0 = (int32_t)((int32_t)T0 >> T1);
502 6af0bf9c bellard
    RETURN();
503 6af0bf9c bellard
}
504 6af0bf9c bellard
505 6af0bf9c bellard
void op_srl (void)
506 6af0bf9c bellard
{
507 5a63bcb2 ths
    T0 = (int32_t)((uint32_t)T0 >> T1);
508 6af0bf9c bellard
    RETURN();
509 6af0bf9c bellard
}
510 6af0bf9c bellard
511 7a387fff ths
void op_rotr (void)
512 7a387fff ths
{
513 7a387fff ths
    target_ulong tmp;
514 7a387fff ths
515 7a387fff ths
    if (T1) {
516 5a63bcb2 ths
       tmp = (int32_t)((uint32_t)T0 << (0x20 - T1));
517 5a63bcb2 ths
       T0 = (int32_t)((uint32_t)T0 >> T1) | tmp;
518 5a63bcb2 ths
    }
519 7a387fff ths
    RETURN();
520 7a387fff ths
}
521 7a387fff ths
522 6af0bf9c bellard
void op_sllv (void)
523 6af0bf9c bellard
{
524 5dc4b744 ths
    T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
525 6af0bf9c bellard
    RETURN();
526 6af0bf9c bellard
}
527 6af0bf9c bellard
528 6af0bf9c bellard
void op_srav (void)
529 6af0bf9c bellard
{
530 5dc4b744 ths
    T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
531 6af0bf9c bellard
    RETURN();
532 6af0bf9c bellard
}
533 6af0bf9c bellard
534 6af0bf9c bellard
void op_srlv (void)
535 6af0bf9c bellard
{
536 5dc4b744 ths
    T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
537 6af0bf9c bellard
    RETURN();
538 6af0bf9c bellard
}
539 6af0bf9c bellard
540 7a387fff ths
void op_rotrv (void)
541 7a387fff ths
{
542 7a387fff ths
    target_ulong tmp;
543 7a387fff ths
544 7a387fff ths
    T0 &= 0x1F;
545 7a387fff ths
    if (T0) {
546 5dc4b744 ths
       tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
547 5dc4b744 ths
       T0 = (int32_t)((uint32_t)T1 >> T0) | tmp;
548 7a387fff ths
    } else
549 7a387fff ths
       T0 = T1;
550 7a387fff ths
    RETURN();
551 7a387fff ths
}
552 7a387fff ths
553 6af0bf9c bellard
void op_clo (void)
554 6af0bf9c bellard
{
555 6af0bf9c bellard
    int n;
556 6af0bf9c bellard
557 c570fd16 ths
    if (T0 == ~((target_ulong)0)) {
558 6af0bf9c bellard
        T0 = 32;
559 6af0bf9c bellard
    } else {
560 6af0bf9c bellard
        for (n = 0; n < 32; n++) {
561 6af0bf9c bellard
            if (!(T0 & (1 << 31)))
562 6af0bf9c bellard
                break;
563 6af0bf9c bellard
            T0 = T0 << 1;
564 6af0bf9c bellard
        }
565 6af0bf9c bellard
        T0 = n;
566 6af0bf9c bellard
    }
567 6af0bf9c bellard
    RETURN();
568 6af0bf9c bellard
}
569 6af0bf9c bellard
570 6af0bf9c bellard
void op_clz (void)
571 6af0bf9c bellard
{
572 6af0bf9c bellard
    int n;
573 6af0bf9c bellard
574 6af0bf9c bellard
    if (T0 == 0) {
575 6af0bf9c bellard
        T0 = 32;
576 6af0bf9c bellard
    } else {
577 6af0bf9c bellard
        for (n = 0; n < 32; n++) {
578 6af0bf9c bellard
            if (T0 & (1 << 31))
579 6af0bf9c bellard
                break;
580 6af0bf9c bellard
            T0 = T0 << 1;
581 6af0bf9c bellard
        }
582 6af0bf9c bellard
        T0 = n;
583 6af0bf9c bellard
    }
584 6af0bf9c bellard
    RETURN();
585 6af0bf9c bellard
}
586 6af0bf9c bellard
587 60aa19ab ths
#ifdef TARGET_MIPS64
588 c570fd16 ths
589 c570fd16 ths
#if TARGET_LONG_BITS > HOST_LONG_BITS
590 c570fd16 ths
/* Those might call libgcc functions.  */
591 c570fd16 ths
void op_dsll (void)
592 6af0bf9c bellard
{
593 c570fd16 ths
    CALL_FROM_TB0(do_dsll);
594 c570fd16 ths
    RETURN();
595 6af0bf9c bellard
}
596 6af0bf9c bellard
597 c570fd16 ths
void op_dsll32 (void)
598 6af0bf9c bellard
{
599 c570fd16 ths
    CALL_FROM_TB0(do_dsll32);
600 c570fd16 ths
    RETURN();
601 6af0bf9c bellard
}
602 6af0bf9c bellard
603 c570fd16 ths
void op_dsra (void)
604 6af0bf9c bellard
{
605 c570fd16 ths
    CALL_FROM_TB0(do_dsra);
606 6af0bf9c bellard
    RETURN();
607 6af0bf9c bellard
}
608 6af0bf9c bellard
609 c570fd16 ths
void op_dsra32 (void)
610 6af0bf9c bellard
{
611 c570fd16 ths
    CALL_FROM_TB0(do_dsra32);
612 6af0bf9c bellard
    RETURN();
613 6af0bf9c bellard
}
614 6af0bf9c bellard
615 c570fd16 ths
void op_dsrl (void)
616 6af0bf9c bellard
{
617 c570fd16 ths
    CALL_FROM_TB0(do_dsrl);
618 c570fd16 ths
    RETURN();
619 c570fd16 ths
}
620 6af0bf9c bellard
621 c570fd16 ths
void op_dsrl32 (void)
622 c570fd16 ths
{
623 c570fd16 ths
    CALL_FROM_TB0(do_dsrl32);
624 6af0bf9c bellard
    RETURN();
625 6af0bf9c bellard
}
626 6af0bf9c bellard
627 c570fd16 ths
void op_drotr (void)
628 6af0bf9c bellard
{
629 c570fd16 ths
    CALL_FROM_TB0(do_drotr);
630 c570fd16 ths
    RETURN();
631 c570fd16 ths
}
632 6af0bf9c bellard
633 c570fd16 ths
void op_drotr32 (void)
634 c570fd16 ths
{
635 c570fd16 ths
    CALL_FROM_TB0(do_drotr32);
636 6af0bf9c bellard
    RETURN();
637 6af0bf9c bellard
}
638 6af0bf9c bellard
639 c570fd16 ths
void op_dsllv (void)
640 6af0bf9c bellard
{
641 c570fd16 ths
    CALL_FROM_TB0(do_dsllv);
642 c570fd16 ths
    RETURN();
643 c570fd16 ths
}
644 6af0bf9c bellard
645 c570fd16 ths
void op_dsrav (void)
646 c570fd16 ths
{
647 c570fd16 ths
    CALL_FROM_TB0(do_dsrav);
648 6af0bf9c bellard
    RETURN();
649 6af0bf9c bellard
}
650 6af0bf9c bellard
651 c570fd16 ths
void op_dsrlv (void)
652 6af0bf9c bellard
{
653 c570fd16 ths
    CALL_FROM_TB0(do_dsrlv);
654 c570fd16 ths
    RETURN();
655 c570fd16 ths
}
656 6af0bf9c bellard
657 c570fd16 ths
void op_drotrv (void)
658 c570fd16 ths
{
659 c570fd16 ths
    CALL_FROM_TB0(do_drotrv);
660 6af0bf9c bellard
    RETURN();
661 6af0bf9c bellard
}
662 c570fd16 ths
663 c570fd16 ths
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
664 c570fd16 ths
665 c570fd16 ths
void op_dsll (void)
666 c570fd16 ths
{
667 c570fd16 ths
    T0 = T0 << T1;
668 c570fd16 ths
    RETURN();
669 c570fd16 ths
}
670 c570fd16 ths
671 c570fd16 ths
void op_dsll32 (void)
672 c570fd16 ths
{
673 c570fd16 ths
    T0 = T0 << (T1 + 32);
674 c570fd16 ths
    RETURN();
675 c570fd16 ths
}
676 c570fd16 ths
677 c570fd16 ths
void op_dsra (void)
678 c570fd16 ths
{
679 c570fd16 ths
    T0 = (int64_t)T0 >> T1;
680 c570fd16 ths
    RETURN();
681 c570fd16 ths
}
682 c570fd16 ths
683 c570fd16 ths
void op_dsra32 (void)
684 c570fd16 ths
{
685 c570fd16 ths
    T0 = (int64_t)T0 >> (T1 + 32);
686 c570fd16 ths
    RETURN();
687 c570fd16 ths
}
688 c570fd16 ths
689 c570fd16 ths
void op_dsrl (void)
690 c570fd16 ths
{
691 c570fd16 ths
    T0 = T0 >> T1;
692 c570fd16 ths
    RETURN();
693 c570fd16 ths
}
694 c570fd16 ths
695 c570fd16 ths
void op_dsrl32 (void)
696 c570fd16 ths
{
697 c570fd16 ths
    T0 = T0 >> (T1 + 32);
698 c570fd16 ths
    RETURN();
699 c570fd16 ths
}
700 c570fd16 ths
701 c570fd16 ths
void op_drotr (void)
702 c570fd16 ths
{
703 c570fd16 ths
    target_ulong tmp;
704 c570fd16 ths
705 c570fd16 ths
    if (T1) {
706 c570fd16 ths
       tmp = T0 << (0x40 - T1);
707 c570fd16 ths
       T0 = (T0 >> T1) | tmp;
708 5a63bcb2 ths
    }
709 c570fd16 ths
    RETURN();
710 c570fd16 ths
}
711 c570fd16 ths
712 c570fd16 ths
void op_drotr32 (void)
713 c570fd16 ths
{
714 c570fd16 ths
    target_ulong tmp;
715 c570fd16 ths
716 c570fd16 ths
    if (T1) {
717 c570fd16 ths
       tmp = T0 << (0x40 - (32 + T1));
718 c570fd16 ths
       T0 = (T0 >> (32 + T1)) | tmp;
719 5a63bcb2 ths
    }
720 c570fd16 ths
    RETURN();
721 c570fd16 ths
}
722 c570fd16 ths
723 c570fd16 ths
void op_dsllv (void)
724 c570fd16 ths
{
725 c570fd16 ths
    T0 = T1 << (T0 & 0x3F);
726 c570fd16 ths
    RETURN();
727 c570fd16 ths
}
728 c570fd16 ths
729 c570fd16 ths
void op_dsrav (void)
730 c570fd16 ths
{
731 c570fd16 ths
    T0 = (int64_t)T1 >> (T0 & 0x3F);
732 c570fd16 ths
    RETURN();
733 c570fd16 ths
}
734 c570fd16 ths
735 c570fd16 ths
void op_dsrlv (void)
736 c570fd16 ths
{
737 c570fd16 ths
    T0 = T1 >> (T0 & 0x3F);
738 c570fd16 ths
    RETURN();
739 c570fd16 ths
}
740 c570fd16 ths
741 c570fd16 ths
void op_drotrv (void)
742 c570fd16 ths
{
743 c570fd16 ths
    target_ulong tmp;
744 c570fd16 ths
745 c570fd16 ths
    T0 &= 0x3F;
746 c570fd16 ths
    if (T0) {
747 c570fd16 ths
       tmp = T1 << (0x40 - T0);
748 c570fd16 ths
       T0 = (T1 >> T0) | tmp;
749 c570fd16 ths
    } else
750 c570fd16 ths
       T0 = T1;
751 c570fd16 ths
    RETURN();
752 c570fd16 ths
}
753 c570fd16 ths
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
754 c570fd16 ths
755 c570fd16 ths
void op_dclo (void)
756 c570fd16 ths
{
757 c570fd16 ths
    int n;
758 c570fd16 ths
759 c570fd16 ths
    if (T0 == ~((target_ulong)0)) {
760 c570fd16 ths
        T0 = 64;
761 c570fd16 ths
    } else {
762 c570fd16 ths
        for (n = 0; n < 64; n++) {
763 c570fd16 ths
            if (!(T0 & (1ULL << 63)))
764 c570fd16 ths
                break;
765 c570fd16 ths
            T0 = T0 << 1;
766 c570fd16 ths
        }
767 c570fd16 ths
        T0 = n;
768 c570fd16 ths
    }
769 c570fd16 ths
    RETURN();
770 c570fd16 ths
}
771 c570fd16 ths
772 c570fd16 ths
void op_dclz (void)
773 c570fd16 ths
{
774 c570fd16 ths
    int n;
775 c570fd16 ths
776 c570fd16 ths
    if (T0 == 0) {
777 c570fd16 ths
        T0 = 64;
778 c570fd16 ths
    } else {
779 c570fd16 ths
        for (n = 0; n < 64; n++) {
780 c570fd16 ths
            if (T0 & (1ULL << 63))
781 c570fd16 ths
                break;
782 c570fd16 ths
            T0 = T0 << 1;
783 c570fd16 ths
        }
784 c570fd16 ths
        T0 = n;
785 c570fd16 ths
    }
786 c570fd16 ths
    RETURN();
787 c570fd16 ths
}
788 c570fd16 ths
#endif
789 c570fd16 ths
790 c570fd16 ths
/* 64 bits arithmetic */
791 c570fd16 ths
#if TARGET_LONG_BITS > HOST_LONG_BITS
792 6af0bf9c bellard
void op_mult (void)
793 6af0bf9c bellard
{
794 6af0bf9c bellard
    CALL_FROM_TB0(do_mult);
795 6af0bf9c bellard
    RETURN();
796 6af0bf9c bellard
}
797 6af0bf9c bellard
798 6af0bf9c bellard
void op_multu (void)
799 6af0bf9c bellard
{
800 6af0bf9c bellard
    CALL_FROM_TB0(do_multu);
801 6af0bf9c bellard
    RETURN();
802 6af0bf9c bellard
}
803 6af0bf9c bellard
804 6af0bf9c bellard
void op_madd (void)
805 6af0bf9c bellard
{
806 6af0bf9c bellard
    CALL_FROM_TB0(do_madd);
807 6af0bf9c bellard
    RETURN();
808 6af0bf9c bellard
}
809 6af0bf9c bellard
810 6af0bf9c bellard
void op_maddu (void)
811 6af0bf9c bellard
{
812 6af0bf9c bellard
    CALL_FROM_TB0(do_maddu);
813 6af0bf9c bellard
    RETURN();
814 6af0bf9c bellard
}
815 6af0bf9c bellard
816 6af0bf9c bellard
void op_msub (void)
817 6af0bf9c bellard
{
818 6af0bf9c bellard
    CALL_FROM_TB0(do_msub);
819 6af0bf9c bellard
    RETURN();
820 6af0bf9c bellard
}
821 6af0bf9c bellard
822 6af0bf9c bellard
void op_msubu (void)
823 6af0bf9c bellard
{
824 6af0bf9c bellard
    CALL_FROM_TB0(do_msubu);
825 6af0bf9c bellard
    RETURN();
826 6af0bf9c bellard
}
827 c570fd16 ths
828 c570fd16 ths
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
829 c570fd16 ths
830 c570fd16 ths
static inline uint64_t get_HILO (void)
831 c570fd16 ths
{
832 c570fd16 ths
    return ((uint64_t)env->HI << 32) | ((uint64_t)(uint32_t)env->LO);
833 c570fd16 ths
}
834 c570fd16 ths
835 c570fd16 ths
static inline void set_HILO (uint64_t HILO)
836 c570fd16 ths
{
837 5dc4b744 ths
    env->LO = (int32_t)(HILO & 0xFFFFFFFF);
838 5dc4b744 ths
    env->HI = (int32_t)(HILO >> 32);
839 c570fd16 ths
}
840 c570fd16 ths
841 c570fd16 ths
void op_mult (void)
842 c570fd16 ths
{
843 c570fd16 ths
    set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
844 c570fd16 ths
    RETURN();
845 c570fd16 ths
}
846 c570fd16 ths
847 c570fd16 ths
void op_multu (void)
848 c570fd16 ths
{
849 c570fd16 ths
    set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
850 c570fd16 ths
    RETURN();
851 c570fd16 ths
}
852 c570fd16 ths
853 c570fd16 ths
void op_madd (void)
854 c570fd16 ths
{
855 c570fd16 ths
    int64_t tmp;
856 c570fd16 ths
857 c570fd16 ths
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
858 c570fd16 ths
    set_HILO((int64_t)get_HILO() + tmp);
859 c570fd16 ths
    RETURN();
860 c570fd16 ths
}
861 c570fd16 ths
862 c570fd16 ths
void op_maddu (void)
863 c570fd16 ths
{
864 c570fd16 ths
    uint64_t tmp;
865 c570fd16 ths
866 c570fd16 ths
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
867 c570fd16 ths
    set_HILO(get_HILO() + tmp);
868 c570fd16 ths
    RETURN();
869 c570fd16 ths
}
870 c570fd16 ths
871 c570fd16 ths
void op_msub (void)
872 c570fd16 ths
{
873 c570fd16 ths
    int64_t tmp;
874 c570fd16 ths
875 c570fd16 ths
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
876 c570fd16 ths
    set_HILO((int64_t)get_HILO() - tmp);
877 c570fd16 ths
    RETURN();
878 c570fd16 ths
}
879 c570fd16 ths
880 c570fd16 ths
void op_msubu (void)
881 c570fd16 ths
{
882 c570fd16 ths
    uint64_t tmp;
883 c570fd16 ths
884 c570fd16 ths
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
885 c570fd16 ths
    set_HILO(get_HILO() - tmp);
886 c570fd16 ths
    RETURN();
887 c570fd16 ths
}
888 c570fd16 ths
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
889 c570fd16 ths
890 60aa19ab ths
#ifdef TARGET_MIPS64
891 c570fd16 ths
void op_dmult (void)
892 c570fd16 ths
{
893 c570fd16 ths
    CALL_FROM_TB0(do_dmult);
894 c570fd16 ths
    RETURN();
895 c570fd16 ths
}
896 c570fd16 ths
897 c570fd16 ths
void op_dmultu (void)
898 c570fd16 ths
{
899 c570fd16 ths
    CALL_FROM_TB0(do_dmultu);
900 c570fd16 ths
    RETURN();
901 c570fd16 ths
}
902 6af0bf9c bellard
#endif
903 6af0bf9c bellard
904 6af0bf9c bellard
/* Conditional moves */
905 6af0bf9c bellard
void op_movn (void)
906 6af0bf9c bellard
{
907 6af0bf9c bellard
    if (T1 != 0)
908 6af0bf9c bellard
        env->gpr[PARAM1] = T0;
909 6af0bf9c bellard
    RETURN();
910 6af0bf9c bellard
}
911 6af0bf9c bellard
912 6af0bf9c bellard
void op_movz (void)
913 6af0bf9c bellard
{
914 6af0bf9c bellard
    if (T1 == 0)
915 6af0bf9c bellard
        env->gpr[PARAM1] = T0;
916 6af0bf9c bellard
    RETURN();
917 6af0bf9c bellard
}
918 6af0bf9c bellard
919 7a387fff ths
void op_movf (void)
920 7a387fff ths
{
921 7a387fff ths
    if (!(env->fcr31 & PARAM1))
922 7a387fff ths
        env->gpr[PARAM2] = env->gpr[PARAM3];
923 7a387fff ths
    RETURN();
924 7a387fff ths
}
925 7a387fff ths
926 7a387fff ths
void op_movt (void)
927 7a387fff ths
{
928 7a387fff ths
    if (env->fcr31 & PARAM1)
929 7a387fff ths
        env->gpr[PARAM2] = env->gpr[PARAM3];
930 7a387fff ths
    RETURN();
931 7a387fff ths
}
932 7a387fff ths
933 6af0bf9c bellard
/* Tests */
934 6af0bf9c bellard
#define OP_COND(name, cond) \
935 6af0bf9c bellard
void glue(op_, name) (void) \
936 6af0bf9c bellard
{                           \
937 6af0bf9c bellard
    if (cond) {             \
938 6af0bf9c bellard
        T0 = 1;             \
939 6af0bf9c bellard
    } else {                \
940 6af0bf9c bellard
        T0 = 0;             \
941 6af0bf9c bellard
    }                       \
942 6af0bf9c bellard
    RETURN();               \
943 6af0bf9c bellard
}
944 6af0bf9c bellard
945 6af0bf9c bellard
OP_COND(eq, T0 == T1);
946 6af0bf9c bellard
OP_COND(ne, T0 != T1);
947 6af0bf9c bellard
OP_COND(ge, (int32_t)T0 >= (int32_t)T1);
948 6af0bf9c bellard
OP_COND(geu, T0 >= T1);
949 6af0bf9c bellard
OP_COND(lt, (int32_t)T0 < (int32_t)T1);
950 6af0bf9c bellard
OP_COND(ltu, T0 < T1);
951 6af0bf9c bellard
OP_COND(gez, (int32_t)T0 >= 0);
952 6af0bf9c bellard
OP_COND(gtz, (int32_t)T0 > 0);
953 6af0bf9c bellard
OP_COND(lez, (int32_t)T0 <= 0);
954 6af0bf9c bellard
OP_COND(ltz, (int32_t)T0 < 0);
955 6af0bf9c bellard
956 7a387fff ths
/* Branches */
957 6af0bf9c bellard
//#undef USE_DIRECT_JUMP
958 c53be334 bellard
959 c53be334 bellard
void OPPROTO op_goto_tb0(void)
960 c53be334 bellard
{
961 c53be334 bellard
    GOTO_TB(op_goto_tb0, PARAM1, 0);
962 7a387fff ths
    RETURN();
963 c53be334 bellard
}
964 c53be334 bellard
965 c53be334 bellard
void OPPROTO op_goto_tb1(void)
966 c53be334 bellard
{
967 c53be334 bellard
    GOTO_TB(op_goto_tb1, PARAM1, 1);
968 7a387fff ths
    RETURN();
969 c53be334 bellard
}
970 6af0bf9c bellard
971 6af0bf9c bellard
/* Branch to register */
972 6af0bf9c bellard
void op_save_breg_target (void)
973 6af0bf9c bellard
{
974 6af0bf9c bellard
    env->btarget = T2;
975 7a387fff ths
    RETURN();
976 6af0bf9c bellard
}
977 6af0bf9c bellard
978 6af0bf9c bellard
void op_restore_breg_target (void)
979 6af0bf9c bellard
{
980 6af0bf9c bellard
    T2 = env->btarget;
981 7a387fff ths
    RETURN();
982 6af0bf9c bellard
}
983 6af0bf9c bellard
984 6af0bf9c bellard
void op_breg (void)
985 6af0bf9c bellard
{
986 6af0bf9c bellard
    env->PC = T2;
987 6af0bf9c bellard
    RETURN();
988 6af0bf9c bellard
}
989 6af0bf9c bellard
990 6af0bf9c bellard
void op_save_btarget (void)
991 6af0bf9c bellard
{
992 6af0bf9c bellard
    env->btarget = PARAM1;
993 6af0bf9c bellard
    RETURN();
994 6af0bf9c bellard
}
995 6af0bf9c bellard
996 6af0bf9c bellard
/* Conditional branch */
997 6af0bf9c bellard
void op_set_bcond (void)
998 6af0bf9c bellard
{
999 6af0bf9c bellard
    T2 = T0;
1000 6af0bf9c bellard
    RETURN();
1001 6af0bf9c bellard
}
1002 6af0bf9c bellard
1003 6af0bf9c bellard
void op_save_bcond (void)
1004 6af0bf9c bellard
{
1005 6af0bf9c bellard
    env->bcond = T2;
1006 6af0bf9c bellard
    RETURN();
1007 6af0bf9c bellard
}
1008 6af0bf9c bellard
1009 6af0bf9c bellard
void op_restore_bcond (void)
1010 6af0bf9c bellard
{
1011 6af0bf9c bellard
    T2 = env->bcond;
1012 6af0bf9c bellard
    RETURN();
1013 6af0bf9c bellard
}
1014 6af0bf9c bellard
1015 c53be334 bellard
void op_jnz_T2 (void)
1016 6af0bf9c bellard
{
1017 c53be334 bellard
    if (T2)
1018 c53be334 bellard
        GOTO_LABEL_PARAM(1);
1019 6af0bf9c bellard
    RETURN();
1020 6af0bf9c bellard
}
1021 6af0bf9c bellard
1022 6af0bf9c bellard
/* CP0 functions */
1023 873eb012 ths
void op_mfc0_index (void)
1024 6af0bf9c bellard
{
1025 9c2149c8 ths
    T0 = env->CP0_Index;
1026 873eb012 ths
    RETURN();
1027 873eb012 ths
}
1028 873eb012 ths
1029 873eb012 ths
void op_mfc0_random (void)
1030 873eb012 ths
{
1031 873eb012 ths
    CALL_FROM_TB0(do_mfc0_random);
1032 873eb012 ths
    RETURN();
1033 873eb012 ths
}
1034 873eb012 ths
1035 873eb012 ths
void op_mfc0_entrylo0 (void)
1036 873eb012 ths
{
1037 9c2149c8 ths
    T0 = (int32_t)env->CP0_EntryLo0;
1038 873eb012 ths
    RETURN();
1039 873eb012 ths
}
1040 873eb012 ths
1041 873eb012 ths
void op_mfc0_entrylo1 (void)
1042 873eb012 ths
{
1043 9c2149c8 ths
    T0 = (int32_t)env->CP0_EntryLo1;
1044 873eb012 ths
    RETURN();
1045 873eb012 ths
}
1046 873eb012 ths
1047 873eb012 ths
void op_mfc0_context (void)
1048 873eb012 ths
{
1049 9c2149c8 ths
    T0 = (int32_t)env->CP0_Context;
1050 873eb012 ths
    RETURN();
1051 873eb012 ths
}
1052 873eb012 ths
1053 873eb012 ths
void op_mfc0_pagemask (void)
1054 873eb012 ths
{
1055 9c2149c8 ths
    T0 = env->CP0_PageMask;
1056 873eb012 ths
    RETURN();
1057 873eb012 ths
}
1058 873eb012 ths
1059 7a387fff ths
void op_mfc0_pagegrain (void)
1060 7a387fff ths
{
1061 9c2149c8 ths
    T0 = env->CP0_PageGrain;
1062 7a387fff ths
    RETURN();
1063 7a387fff ths
}
1064 7a387fff ths
1065 873eb012 ths
void op_mfc0_wired (void)
1066 873eb012 ths
{
1067 9c2149c8 ths
    T0 = env->CP0_Wired;
1068 873eb012 ths
    RETURN();
1069 873eb012 ths
}
1070 873eb012 ths
1071 7a387fff ths
void op_mfc0_hwrena (void)
1072 7a387fff ths
{
1073 9c2149c8 ths
    T0 = env->CP0_HWREna;
1074 7a387fff ths
    RETURN();
1075 7a387fff ths
}
1076 7a387fff ths
1077 873eb012 ths
void op_mfc0_badvaddr (void)
1078 873eb012 ths
{
1079 9c2149c8 ths
    T0 = (int32_t)env->CP0_BadVAddr;
1080 873eb012 ths
    RETURN();
1081 873eb012 ths
}
1082 873eb012 ths
1083 873eb012 ths
void op_mfc0_count (void)
1084 873eb012 ths
{
1085 873eb012 ths
    CALL_FROM_TB0(do_mfc0_count);
1086 873eb012 ths
    RETURN();
1087 873eb012 ths
}
1088 873eb012 ths
1089 873eb012 ths
void op_mfc0_entryhi (void)
1090 873eb012 ths
{
1091 9c2149c8 ths
    T0 = (int32_t)env->CP0_EntryHi;
1092 873eb012 ths
    RETURN();
1093 873eb012 ths
}
1094 873eb012 ths
1095 873eb012 ths
void op_mfc0_compare (void)
1096 873eb012 ths
{
1097 9c2149c8 ths
    T0 = env->CP0_Compare;
1098 873eb012 ths
    RETURN();
1099 873eb012 ths
}
1100 873eb012 ths
1101 873eb012 ths
void op_mfc0_status (void)
1102 873eb012 ths
{
1103 9c2149c8 ths
    T0 = env->CP0_Status;
1104 873eb012 ths
    RETURN();
1105 873eb012 ths
}
1106 873eb012 ths
1107 7a387fff ths
void op_mfc0_intctl (void)
1108 7a387fff ths
{
1109 9c2149c8 ths
    T0 = env->CP0_IntCtl;
1110 7a387fff ths
    RETURN();
1111 7a387fff ths
}
1112 7a387fff ths
1113 7a387fff ths
void op_mfc0_srsctl (void)
1114 7a387fff ths
{
1115 9c2149c8 ths
    T0 = env->CP0_SRSCtl;
1116 9c2149c8 ths
    RETURN();
1117 9c2149c8 ths
}
1118 9c2149c8 ths
1119 9c2149c8 ths
void op_mfc0_srsmap (void)
1120 9c2149c8 ths
{
1121 9c2149c8 ths
    T0 = env->CP0_SRSMap;
1122 7a387fff ths
    RETURN();
1123 7a387fff ths
}
1124 7a387fff ths
1125 873eb012 ths
void op_mfc0_cause (void)
1126 873eb012 ths
{
1127 9c2149c8 ths
    T0 = env->CP0_Cause;
1128 873eb012 ths
    RETURN();
1129 873eb012 ths
}
1130 873eb012 ths
1131 873eb012 ths
void op_mfc0_epc (void)
1132 873eb012 ths
{
1133 9c2149c8 ths
    T0 = (int32_t)env->CP0_EPC;
1134 873eb012 ths
    RETURN();
1135 873eb012 ths
}
1136 873eb012 ths
1137 873eb012 ths
void op_mfc0_prid (void)
1138 873eb012 ths
{
1139 9c2149c8 ths
    T0 = env->CP0_PRid;
1140 873eb012 ths
    RETURN();
1141 873eb012 ths
}
1142 873eb012 ths
1143 7a387fff ths
void op_mfc0_ebase (void)
1144 7a387fff ths
{
1145 b29a0341 ths
    T0 = env->CP0_EBase;
1146 7a387fff ths
    RETURN();
1147 7a387fff ths
}
1148 7a387fff ths
1149 873eb012 ths
void op_mfc0_config0 (void)
1150 873eb012 ths
{
1151 9c2149c8 ths
    T0 = env->CP0_Config0;
1152 873eb012 ths
    RETURN();
1153 873eb012 ths
}
1154 873eb012 ths
1155 873eb012 ths
void op_mfc0_config1 (void)
1156 873eb012 ths
{
1157 9c2149c8 ths
    T0 = env->CP0_Config1;
1158 873eb012 ths
    RETURN();
1159 873eb012 ths
}
1160 873eb012 ths
1161 7a387fff ths
void op_mfc0_config2 (void)
1162 7a387fff ths
{
1163 9c2149c8 ths
    T0 = env->CP0_Config2;
1164 7a387fff ths
    RETURN();
1165 7a387fff ths
}
1166 7a387fff ths
1167 7a387fff ths
void op_mfc0_config3 (void)
1168 7a387fff ths
{
1169 9c2149c8 ths
    T0 = env->CP0_Config3;
1170 7a387fff ths
    RETURN();
1171 7a387fff ths
}
1172 7a387fff ths
1173 e397ee33 ths
void op_mfc0_config6 (void)
1174 e397ee33 ths
{
1175 e397ee33 ths
    T0 = env->CP0_Config6;
1176 e397ee33 ths
    RETURN();
1177 e397ee33 ths
}
1178 e397ee33 ths
1179 e397ee33 ths
void op_mfc0_config7 (void)
1180 e397ee33 ths
{
1181 e397ee33 ths
    T0 = env->CP0_Config7;
1182 e397ee33 ths
    RETURN();
1183 e397ee33 ths
}
1184 e397ee33 ths
1185 873eb012 ths
void op_mfc0_lladdr (void)
1186 873eb012 ths
{
1187 9c2149c8 ths
    T0 = (int32_t)env->CP0_LLAddr >> 4;
1188 873eb012 ths
    RETURN();
1189 873eb012 ths
}
1190 873eb012 ths
1191 7a387fff ths
void op_mfc0_watchlo0 (void)
1192 873eb012 ths
{
1193 5dc4b744 ths
    T0 = (int32_t)env->CP0_WatchLo;
1194 873eb012 ths
    RETURN();
1195 873eb012 ths
}
1196 873eb012 ths
1197 7a387fff ths
void op_mfc0_watchhi0 (void)
1198 873eb012 ths
{
1199 9c2149c8 ths
    T0 = env->CP0_WatchHi;
1200 873eb012 ths
    RETURN();
1201 873eb012 ths
}
1202 873eb012 ths
1203 7a387fff ths
void op_mfc0_xcontext (void)
1204 7a387fff ths
{
1205 9c2149c8 ths
    T0 = (int32_t)env->CP0_XContext;
1206 7a387fff ths
    RETURN();
1207 7a387fff ths
}
1208 7a387fff ths
1209 7a387fff ths
void op_mfc0_framemask (void)
1210 7a387fff ths
{
1211 7a387fff ths
    T0 = env->CP0_Framemask;
1212 7a387fff ths
    RETURN();
1213 7a387fff ths
}
1214 7a387fff ths
1215 873eb012 ths
void op_mfc0_debug (void)
1216 873eb012 ths
{
1217 9c2149c8 ths
    T0 = env->CP0_Debug;
1218 873eb012 ths
    if (env->hflags & MIPS_HFLAG_DM)
1219 873eb012 ths
        T0 |= 1 << CP0DB_DM;
1220 873eb012 ths
    RETURN();
1221 873eb012 ths
}
1222 873eb012 ths
1223 873eb012 ths
void op_mfc0_depc (void)
1224 873eb012 ths
{
1225 9c2149c8 ths
    T0 = (int32_t)env->CP0_DEPC;
1226 873eb012 ths
    RETURN();
1227 873eb012 ths
}
1228 873eb012 ths
1229 7a387fff ths
void op_mfc0_performance0 (void)
1230 7a387fff ths
{
1231 9c2149c8 ths
    T0 = env->CP0_Performance0;
1232 7a387fff ths
    RETURN();
1233 7a387fff ths
}
1234 7a387fff ths
1235 873eb012 ths
void op_mfc0_taglo (void)
1236 873eb012 ths
{
1237 9c2149c8 ths
    T0 = env->CP0_TagLo;
1238 873eb012 ths
    RETURN();
1239 873eb012 ths
}
1240 873eb012 ths
1241 873eb012 ths
void op_mfc0_datalo (void)
1242 873eb012 ths
{
1243 9c2149c8 ths
    T0 = env->CP0_DataLo;
1244 873eb012 ths
    RETURN();
1245 873eb012 ths
}
1246 873eb012 ths
1247 7a387fff ths
void op_mfc0_taghi (void)
1248 7a387fff ths
{
1249 9c2149c8 ths
    T0 = env->CP0_TagHi;
1250 7a387fff ths
    RETURN();
1251 7a387fff ths
}
1252 7a387fff ths
1253 7a387fff ths
void op_mfc0_datahi (void)
1254 7a387fff ths
{
1255 9c2149c8 ths
    T0 = env->CP0_DataHi;
1256 7a387fff ths
    RETURN();
1257 7a387fff ths
}
1258 7a387fff ths
1259 873eb012 ths
void op_mfc0_errorepc (void)
1260 873eb012 ths
{
1261 9c2149c8 ths
    T0 = (int32_t)env->CP0_ErrorEPC;
1262 873eb012 ths
    RETURN();
1263 873eb012 ths
}
1264 873eb012 ths
1265 873eb012 ths
void op_mfc0_desave (void)
1266 873eb012 ths
{
1267 9c2149c8 ths
    T0 = env->CP0_DESAVE;
1268 6af0bf9c bellard
    RETURN();
1269 6af0bf9c bellard
}
1270 6af0bf9c bellard
1271 8c0fdd85 ths
void op_mtc0_index (void)
1272 6af0bf9c bellard
{
1273 fcb4a419 ths
    env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 % env->nb_tlb);
1274 8c0fdd85 ths
    RETURN();
1275 8c0fdd85 ths
}
1276 8c0fdd85 ths
1277 8c0fdd85 ths
void op_mtc0_entrylo0 (void)
1278 8c0fdd85 ths
{
1279 7a387fff ths
    /* Large physaddr not implemented */
1280 7a387fff ths
    /* 1k pages not implemented */
1281 9c2149c8 ths
    env->CP0_EntryLo0 = (int32_t)T0 & 0x3FFFFFFF;
1282 8c0fdd85 ths
    RETURN();
1283 8c0fdd85 ths
}
1284 8c0fdd85 ths
1285 8c0fdd85 ths
void op_mtc0_entrylo1 (void)
1286 8c0fdd85 ths
{
1287 7a387fff ths
    /* Large physaddr not implemented */
1288 7a387fff ths
    /* 1k pages not implemented */
1289 9c2149c8 ths
    env->CP0_EntryLo1 = (int32_t)T0 & 0x3FFFFFFF;
1290 8c0fdd85 ths
    RETURN();
1291 8c0fdd85 ths
}
1292 8c0fdd85 ths
1293 8c0fdd85 ths
void op_mtc0_context (void)
1294 8c0fdd85 ths
{
1295 534ce69f ths
    env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
1296 8c0fdd85 ths
    RETURN();
1297 8c0fdd85 ths
}
1298 8c0fdd85 ths
1299 8c0fdd85 ths
void op_mtc0_pagemask (void)
1300 8c0fdd85 ths
{
1301 7a387fff ths
    /* 1k pages not implemented */
1302 7a387fff ths
    env->CP0_PageMask = T0 & 0x1FFFE000;
1303 7a387fff ths
    RETURN();
1304 7a387fff ths
}
1305 7a387fff ths
1306 7a387fff ths
void op_mtc0_pagegrain (void)
1307 7a387fff ths
{
1308 7a387fff ths
    /* SmartMIPS not implemented */
1309 7a387fff ths
    /* Large physaddr not implemented */
1310 7a387fff ths
    /* 1k pages not implemented */
1311 7a387fff ths
    env->CP0_PageGrain = 0;
1312 8c0fdd85 ths
    RETURN();
1313 8c0fdd85 ths
}
1314 8c0fdd85 ths
1315 8c0fdd85 ths
void op_mtc0_wired (void)
1316 8c0fdd85 ths
{
1317 fcb4a419 ths
    env->CP0_Wired = T0 % env->nb_tlb;
1318 7a387fff ths
    RETURN();
1319 7a387fff ths
}
1320 7a387fff ths
1321 7a387fff ths
void op_mtc0_hwrena (void)
1322 7a387fff ths
{
1323 7a387fff ths
    env->CP0_HWREna = T0 & 0x0000000F;
1324 8c0fdd85 ths
    RETURN();
1325 8c0fdd85 ths
}
1326 8c0fdd85 ths
1327 8c0fdd85 ths
void op_mtc0_count (void)
1328 8c0fdd85 ths
{
1329 8c0fdd85 ths
    CALL_FROM_TB2(cpu_mips_store_count, env, T0);
1330 8c0fdd85 ths
    RETURN();
1331 8c0fdd85 ths
}
1332 8c0fdd85 ths
1333 8c0fdd85 ths
void op_mtc0_entryhi (void)
1334 8c0fdd85 ths
{
1335 0feef828 ths
    target_ulong old, val;
1336 8c0fdd85 ths
1337 7a387fff ths
    /* 1k pages not implemented */
1338 7a387fff ths
    /* Ignore MIPS64 TLB for now */
1339 925fd0f2 ths
    val = (target_ulong)(int32_t)T0 & ~(target_ulong)0x1F00;
1340 8c0fdd85 ths
    old = env->CP0_EntryHi;
1341 8c0fdd85 ths
    env->CP0_EntryHi = val;
1342 8c0fdd85 ths
    /* If the ASID changes, flush qemu's TLB.  */
1343 8c0fdd85 ths
    if ((old & 0xFF) != (val & 0xFF))
1344 8c0fdd85 ths
        CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
1345 8c0fdd85 ths
    RETURN();
1346 8c0fdd85 ths
}
1347 8c0fdd85 ths
1348 8c0fdd85 ths
void op_mtc0_compare (void)
1349 8c0fdd85 ths
{
1350 8c0fdd85 ths
    CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
1351 8c0fdd85 ths
    RETURN();
1352 8c0fdd85 ths
}
1353 8c0fdd85 ths
1354 8c0fdd85 ths
void op_mtc0_status (void)
1355 8c0fdd85 ths
{
1356 4de9b249 ths
    uint32_t val, old;
1357 8c0fdd85 ths
1358 24c7b0e3 ths
    /* No 64bit FPU, no reverse endianness, no MDMX/DSP, no 64bit ops,
1359 24c7b0e3 ths
       no 64bit addressing implemented. */
1360 24c7b0e3 ths
    val = (int32_t)T0 & 0xF878FF17;
1361 8c0fdd85 ths
    old = env->CP0_Status;
1362 f41c52f1 ths
    if (!(val & (1 << CP0St_EXL)) &&
1363 f41c52f1 ths
        !(val & (1 << CP0St_ERL)) &&
1364 f41c52f1 ths
        !(env->hflags & MIPS_HFLAG_DM) &&
1365 f41c52f1 ths
        (val & (1 << CP0St_UM)))
1366 f41c52f1 ths
        env->hflags |= MIPS_HFLAG_UM;
1367 16c00cb2 ths
    env->CP0_Status = (env->CP0_Status & ~0xF878FF17) | val;
1368 f41c52f1 ths
    if (loglevel & CPU_LOG_EXEC)
1369 f41c52f1 ths
        CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1370 4de9b249 ths
    CALL_FROM_TB1(cpu_mips_update_irq, env);
1371 8c0fdd85 ths
    RETURN();
1372 8c0fdd85 ths
}
1373 8c0fdd85 ths
1374 7a387fff ths
void op_mtc0_intctl (void)
1375 7a387fff ths
{
1376 c090a8f4 ths
    /* vectored interrupts not implemented, timer on int 7,
1377 c090a8f4 ths
       no performance counters. */
1378 c090a8f4 ths
    env->CP0_IntCtl |= T0 & 0x000002e0;
1379 7a387fff ths
    RETURN();
1380 7a387fff ths
}
1381 7a387fff ths
1382 7a387fff ths
void op_mtc0_srsctl (void)
1383 7a387fff ths
{
1384 7a387fff ths
    /* shadow registers not implemented */
1385 7a387fff ths
    env->CP0_SRSCtl = 0;
1386 7a387fff ths
    RETURN();
1387 7a387fff ths
}
1388 7a387fff ths
1389 9c2149c8 ths
void op_mtc0_srsmap (void)
1390 9c2149c8 ths
{
1391 9c2149c8 ths
    /* shadow registers not implemented */
1392 9c2149c8 ths
    env->CP0_SRSMap = 0;
1393 9c2149c8 ths
    RETURN();
1394 9c2149c8 ths
}
1395 9c2149c8 ths
1396 8c0fdd85 ths
void op_mtc0_cause (void)
1397 8c0fdd85 ths
{
1398 39d51eb8 ths
    uint32_t mask = 0x00C00300;
1399 39d51eb8 ths
1400 39d51eb8 ths
    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
1401 39d51eb8 ths
        mask |= 1 << CP0Ca_DC;
1402 39d51eb8 ths
1403 e58c8ba5 ths
    env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
1404 8c0fdd85 ths
1405 4de9b249 ths
    /* Handle the software interrupt as an hardware one, as they
1406 4de9b249 ths
       are very similar */
1407 4de9b249 ths
    if (T0 & CP0Ca_IP_mask) {
1408 4de9b249 ths
        CALL_FROM_TB1(cpu_mips_update_irq, env);
1409 8c0fdd85 ths
    }
1410 8c0fdd85 ths
    RETURN();
1411 8c0fdd85 ths
}
1412 8c0fdd85 ths
1413 8c0fdd85 ths
void op_mtc0_epc (void)
1414 8c0fdd85 ths
{
1415 9c2149c8 ths
    env->CP0_EPC = (int32_t)T0;
1416 8c0fdd85 ths
    RETURN();
1417 8c0fdd85 ths
}
1418 8c0fdd85 ths
1419 7a387fff ths
void op_mtc0_ebase (void)
1420 7a387fff ths
{
1421 7a387fff ths
    /* vectored interrupts not implemented */
1422 7a387fff ths
    /* Multi-CPU not implemented */
1423 b29a0341 ths
    env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1424 7a387fff ths
    RETURN();
1425 7a387fff ths
}
1426 7a387fff ths
1427 8c0fdd85 ths
void op_mtc0_config0 (void)
1428 8c0fdd85 ths
{
1429 8c0fdd85 ths
#if defined(MIPS_USES_R4K_TLB)
1430 7a387fff ths
     /* Fixed mapping MMU not implemented */
1431 7a387fff ths
    env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF88) | (T0 & 0x00000001);
1432 8c0fdd85 ths
#else
1433 7a387fff ths
    env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF88) | (T0 & 0x00000001);
1434 8c0fdd85 ths
#endif
1435 8c0fdd85 ths
    RETURN();
1436 8c0fdd85 ths
}
1437 8c0fdd85 ths
1438 7a387fff ths
void op_mtc0_config2 (void)
1439 7a387fff ths
{
1440 7a387fff ths
    /* tertiary/secondary caches not implemented */
1441 7a387fff ths
    env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1442 7a387fff ths
    RETURN();
1443 7a387fff ths
}
1444 7a387fff ths
1445 7a387fff ths
void op_mtc0_watchlo0 (void)
1446 8c0fdd85 ths
{
1447 4e7a4a4e ths
    /* Watch exceptions for instructions, data loads, data stores
1448 4e7a4a4e ths
       not implemented. */
1449 4e7a4a4e ths
    env->CP0_WatchLo = (int32_t)(T0 & ~0x7);
1450 8c0fdd85 ths
    RETURN();
1451 8c0fdd85 ths
}
1452 8c0fdd85 ths
1453 7a387fff ths
void op_mtc0_watchhi0 (void)
1454 8c0fdd85 ths
{
1455 4e7a4a4e ths
    env->CP0_WatchHi = (T0 & 0x40FF0FF8);
1456 4e7a4a4e ths
    env->CP0_WatchHi &= ~(env->CP0_WatchHi & T0 & 0x7);
1457 8c0fdd85 ths
    RETURN();
1458 8c0fdd85 ths
}
1459 8c0fdd85 ths
1460 7a387fff ths
void op_mtc0_framemask (void)
1461 7a387fff ths
{
1462 7a387fff ths
    env->CP0_Framemask = T0; /* XXX */
1463 7a387fff ths
    RETURN();
1464 7a387fff ths
}
1465 7a387fff ths
1466 8c0fdd85 ths
void op_mtc0_debug (void)
1467 8c0fdd85 ths
{
1468 8c0fdd85 ths
    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
1469 8c0fdd85 ths
    if (T0 & (1 << CP0DB_DM))
1470 8c0fdd85 ths
        env->hflags |= MIPS_HFLAG_DM;
1471 8c0fdd85 ths
    else
1472 8c0fdd85 ths
        env->hflags &= ~MIPS_HFLAG_DM;
1473 8c0fdd85 ths
    RETURN();
1474 8c0fdd85 ths
}
1475 8c0fdd85 ths
1476 8c0fdd85 ths
void op_mtc0_depc (void)
1477 8c0fdd85 ths
{
1478 9c2149c8 ths
    env->CP0_DEPC = (int32_t)T0;
1479 8c0fdd85 ths
    RETURN();
1480 8c0fdd85 ths
}
1481 8c0fdd85 ths
1482 7a387fff ths
void op_mtc0_performance0 (void)
1483 7a387fff ths
{
1484 7a387fff ths
    env->CP0_Performance0 = T0; /* XXX */
1485 7a387fff ths
    RETURN();
1486 7a387fff ths
}
1487 7a387fff ths
1488 8c0fdd85 ths
void op_mtc0_taglo (void)
1489 8c0fdd85 ths
{
1490 9c2149c8 ths
    env->CP0_TagLo = T0 & 0xFFFFFCF6;
1491 8c0fdd85 ths
    RETURN();
1492 8c0fdd85 ths
}
1493 8c0fdd85 ths
1494 7a387fff ths
void op_mtc0_datalo (void)
1495 7a387fff ths
{
1496 7a387fff ths
    env->CP0_DataLo = T0; /* XXX */
1497 7a387fff ths
    RETURN();
1498 7a387fff ths
}
1499 7a387fff ths
1500 7a387fff ths
void op_mtc0_taghi (void)
1501 7a387fff ths
{
1502 7a387fff ths
    env->CP0_TagHi = T0; /* XXX */
1503 7a387fff ths
    RETURN();
1504 7a387fff ths
}
1505 7a387fff ths
1506 7a387fff ths
void op_mtc0_datahi (void)
1507 7a387fff ths
{
1508 7a387fff ths
    env->CP0_DataHi = T0; /* XXX */
1509 7a387fff ths
    RETURN();
1510 7a387fff ths
}
1511 7a387fff ths
1512 8c0fdd85 ths
void op_mtc0_errorepc (void)
1513 8c0fdd85 ths
{
1514 9c2149c8 ths
    env->CP0_ErrorEPC = (int32_t)T0;
1515 8c0fdd85 ths
    RETURN();
1516 8c0fdd85 ths
}
1517 8c0fdd85 ths
1518 8c0fdd85 ths
void op_mtc0_desave (void)
1519 8c0fdd85 ths
{
1520 8c0fdd85 ths
    env->CP0_DESAVE = T0;
1521 6af0bf9c bellard
    RETURN();
1522 6af0bf9c bellard
}
1523 6af0bf9c bellard
1524 534ce69f ths
#ifdef TARGET_MIPS64
1525 9c2149c8 ths
void op_dmfc0_entrylo0 (void)
1526 9c2149c8 ths
{
1527 9c2149c8 ths
    T0 = env->CP0_EntryLo0;
1528 9c2149c8 ths
    RETURN();
1529 9c2149c8 ths
}
1530 9c2149c8 ths
1531 9c2149c8 ths
void op_dmfc0_entrylo1 (void)
1532 9c2149c8 ths
{
1533 9c2149c8 ths
    T0 = env->CP0_EntryLo1;
1534 9c2149c8 ths
    RETURN();
1535 9c2149c8 ths
}
1536 9c2149c8 ths
1537 9c2149c8 ths
void op_dmfc0_context (void)
1538 9c2149c8 ths
{
1539 9c2149c8 ths
    T0 = env->CP0_Context;
1540 9c2149c8 ths
    RETURN();
1541 9c2149c8 ths
}
1542 9c2149c8 ths
1543 9c2149c8 ths
void op_dmfc0_badvaddr (void)
1544 9c2149c8 ths
{
1545 9c2149c8 ths
    T0 = env->CP0_BadVAddr;
1546 9c2149c8 ths
    RETURN();
1547 9c2149c8 ths
}
1548 9c2149c8 ths
1549 9c2149c8 ths
void op_dmfc0_entryhi (void)
1550 9c2149c8 ths
{
1551 9c2149c8 ths
    T0 = env->CP0_EntryHi;
1552 9c2149c8 ths
    RETURN();
1553 9c2149c8 ths
}
1554 9c2149c8 ths
1555 9c2149c8 ths
void op_dmfc0_epc (void)
1556 9c2149c8 ths
{
1557 9c2149c8 ths
    T0 = env->CP0_EPC;
1558 9c2149c8 ths
    RETURN();
1559 9c2149c8 ths
}
1560 9c2149c8 ths
1561 9c2149c8 ths
void op_dmfc0_lladdr (void)
1562 9c2149c8 ths
{
1563 9c2149c8 ths
    T0 = env->CP0_LLAddr >> 4;
1564 9c2149c8 ths
    RETURN();
1565 9c2149c8 ths
}
1566 9c2149c8 ths
1567 9c2149c8 ths
void op_dmfc0_watchlo0 (void)
1568 9c2149c8 ths
{
1569 9c2149c8 ths
    T0 = env->CP0_WatchLo;
1570 9c2149c8 ths
    RETURN();
1571 9c2149c8 ths
}
1572 9c2149c8 ths
1573 9c2149c8 ths
void op_dmfc0_xcontext (void)
1574 9c2149c8 ths
{
1575 9c2149c8 ths
    T0 = env->CP0_XContext;
1576 9c2149c8 ths
    RETURN();
1577 9c2149c8 ths
}
1578 9c2149c8 ths
1579 9c2149c8 ths
void op_dmfc0_depc (void)
1580 9c2149c8 ths
{
1581 9c2149c8 ths
    T0 = env->CP0_DEPC;
1582 9c2149c8 ths
    RETURN();
1583 9c2149c8 ths
}
1584 9c2149c8 ths
1585 9c2149c8 ths
void op_dmfc0_errorepc (void)
1586 9c2149c8 ths
{
1587 9c2149c8 ths
    T0 = env->CP0_ErrorEPC;
1588 9c2149c8 ths
    RETURN();
1589 9c2149c8 ths
}
1590 9c2149c8 ths
1591 9c2149c8 ths
void op_dmtc0_entrylo0 (void)
1592 9c2149c8 ths
{
1593 9c2149c8 ths
    /* Large physaddr not implemented */
1594 9c2149c8 ths
    /* 1k pages not implemented */
1595 9c2149c8 ths
    env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1596 9c2149c8 ths
    RETURN();
1597 9c2149c8 ths
}
1598 9c2149c8 ths
1599 9c2149c8 ths
void op_dmtc0_entrylo1 (void)
1600 9c2149c8 ths
{
1601 9c2149c8 ths
    /* Large physaddr not implemented */
1602 9c2149c8 ths
    /* 1k pages not implemented */
1603 9c2149c8 ths
    env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
1604 9c2149c8 ths
    RETURN();
1605 9c2149c8 ths
}
1606 9c2149c8 ths
1607 9c2149c8 ths
void op_dmtc0_context (void)
1608 9c2149c8 ths
{
1609 534ce69f ths
    env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
1610 9c2149c8 ths
    RETURN();
1611 9c2149c8 ths
}
1612 9c2149c8 ths
1613 9c2149c8 ths
void op_dmtc0_epc (void)
1614 9c2149c8 ths
{
1615 9c2149c8 ths
    env->CP0_EPC = T0;
1616 9c2149c8 ths
    RETURN();
1617 9c2149c8 ths
}
1618 9c2149c8 ths
1619 9c2149c8 ths
void op_dmtc0_watchlo0 (void)
1620 9c2149c8 ths
{
1621 4e7a4a4e ths
    /* Watch exceptions for instructions, data loads, data stores
1622 4e7a4a4e ths
       not implemented. */
1623 4e7a4a4e ths
    env->CP0_WatchLo = T0 & ~0x7;
1624 9c2149c8 ths
    RETURN();
1625 9c2149c8 ths
}
1626 9c2149c8 ths
1627 9c2149c8 ths
void op_dmtc0_xcontext (void)
1628 9c2149c8 ths
{
1629 534ce69f ths
    env->CP0_XContext = (env->CP0_XContext & 0xffffffff) | (T0 & ~0xffffffff);
1630 9c2149c8 ths
    RETURN();
1631 9c2149c8 ths
}
1632 9c2149c8 ths
1633 9c2149c8 ths
void op_dmtc0_depc (void)
1634 9c2149c8 ths
{
1635 9c2149c8 ths
    env->CP0_DEPC = T0;
1636 9c2149c8 ths
    RETURN();
1637 9c2149c8 ths
}
1638 9c2149c8 ths
1639 9c2149c8 ths
void op_dmtc0_errorepc (void)
1640 9c2149c8 ths
{
1641 9c2149c8 ths
    env->CP0_ErrorEPC = T0;
1642 9c2149c8 ths
    RETURN();
1643 9c2149c8 ths
}
1644 534ce69f ths
#endif /* TARGET_MIPS64 */
1645 9c2149c8 ths
1646 6ea83fed bellard
#if 0
1647 6ea83fed bellard
# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
1648 6ea83fed bellard
#else
1649 6ea83fed bellard
# define DEBUG_FPU_STATE() do { } while(0)
1650 6ea83fed bellard
#endif
1651 6ea83fed bellard
1652 24c7b0e3 ths
void op_cp0_enabled(void)
1653 24c7b0e3 ths
{
1654 24c7b0e3 ths
    if (!(env->CP0_Status & (1 << CP0St_CU0)) &&
1655 24c7b0e3 ths
        (env->hflags & MIPS_HFLAG_UM)) {
1656 1579a72e ths
        CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 0);
1657 24c7b0e3 ths
    }
1658 24c7b0e3 ths
    RETURN();
1659 24c7b0e3 ths
}
1660 24c7b0e3 ths
1661 6ea83fed bellard
void op_cp1_enabled(void)
1662 6ea83fed bellard
{
1663 6ea83fed bellard
    if (!(env->CP0_Status & (1 << CP0St_CU1))) {
1664 1579a72e ths
        CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1);
1665 6ea83fed bellard
    }
1666 6ea83fed bellard
    RETURN();
1667 6ea83fed bellard
}
1668 6ea83fed bellard
1669 6ea83fed bellard
/* CP1 functions */
1670 6ea83fed bellard
void op_cfc1 (void)
1671 6ea83fed bellard
{
1672 6ea83fed bellard
    if (T1 == 0) {
1673 6ea83fed bellard
        T0 = env->fcr0;
1674 6ea83fed bellard
    }
1675 6ea83fed bellard
    else {
1676 6ea83fed bellard
        /* fetch fcr31, masking unused bits */
1677 6ea83fed bellard
        T0 = env->fcr31 & 0x0183FFFF;
1678 6ea83fed bellard
    }
1679 6ea83fed bellard
    DEBUG_FPU_STATE();
1680 6ea83fed bellard
    RETURN();
1681 6ea83fed bellard
}
1682 6ea83fed bellard
1683 6ea83fed bellard
/* convert MIPS rounding mode in FCR31 to IEEE library */
1684 6ea83fed bellard
unsigned int ieee_rm[] = { 
1685 6ea83fed bellard
    float_round_nearest_even,
1686 6ea83fed bellard
    float_round_to_zero,
1687 6ea83fed bellard
    float_round_up,
1688 6ea83fed bellard
    float_round_down
1689 6ea83fed bellard
};
1690 6ea83fed bellard
1691 6ea83fed bellard
#define RESTORE_ROUNDING_MODE \
1692 6ea83fed bellard
    set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
1693 6ea83fed bellard
1694 6ea83fed bellard
void op_ctc1 (void)
1695 6ea83fed bellard
{
1696 6ea83fed bellard
    if (T1 == 0) {
1697 6ea83fed bellard
        /* XXX should this throw an exception?
1698 6ea83fed bellard
         * don't write to FCR0.
1699 6ea83fed bellard
         * env->fcr0 = T0; 
1700 6ea83fed bellard
         */
1701 6ea83fed bellard
    }
1702 6ea83fed bellard
    else {
1703 6ea83fed bellard
        /* store new fcr31, masking unused bits */  
1704 6ea83fed bellard
        env->fcr31 = T0 & 0x0183FFFF;
1705 6ea83fed bellard
1706 6ea83fed bellard
        /* set rounding mode */
1707 6ea83fed bellard
        RESTORE_ROUNDING_MODE;
1708 6ea83fed bellard
1709 6ea83fed bellard
#ifndef CONFIG_SOFTFLOAT
1710 6ea83fed bellard
        /* no floating point exception for native float */
1711 6ea83fed bellard
        SET_FP_ENABLE(env->fcr31, 0);
1712 6ea83fed bellard
#endif
1713 6ea83fed bellard
    }
1714 6ea83fed bellard
    DEBUG_FPU_STATE();
1715 6ea83fed bellard
    RETURN();
1716 6ea83fed bellard
}
1717 6ea83fed bellard
1718 6ea83fed bellard
void op_mfc1 (void)
1719 6ea83fed bellard
{
1720 6ea83fed bellard
    T0 = WT0;
1721 6ea83fed bellard
    DEBUG_FPU_STATE();
1722 6ea83fed bellard
    RETURN();
1723 6ea83fed bellard
}
1724 6ea83fed bellard
1725 6ea83fed bellard
void op_mtc1 (void)
1726 6ea83fed bellard
{
1727 6ea83fed bellard
    WT0 = T0;
1728 6ea83fed bellard
    DEBUG_FPU_STATE();
1729 6ea83fed bellard
    RETURN();
1730 6ea83fed bellard
}
1731 6ea83fed bellard
1732 6ea83fed bellard
/* Float support.
1733 6ea83fed bellard
   Single precition routines have a "s" suffix, double precision a
1734 6ea83fed bellard
   "d" suffix.  */
1735 6ea83fed bellard
1736 6ea83fed bellard
#define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
1737 6ea83fed bellard
1738 dd016883 bellard
FLOAT_OP(cvtd, s)
1739 dd016883 bellard
{
1740 00a709c7 ths
    FDT2 = float32_to_float64(FST0, &env->fp_status);
1741 dd016883 bellard
    DEBUG_FPU_STATE();
1742 dd016883 bellard
    RETURN();
1743 dd016883 bellard
}
1744 6ea83fed bellard
FLOAT_OP(cvtd, w)
1745 6ea83fed bellard
{
1746 6ea83fed bellard
    FDT2 = int32_to_float64(WT0, &env->fp_status);
1747 6ea83fed bellard
    DEBUG_FPU_STATE();
1748 6ea83fed bellard
    RETURN();
1749 6ea83fed bellard
}
1750 dd016883 bellard
FLOAT_OP(cvts, d)
1751 dd016883 bellard
{
1752 417f38f0 pbrook
    FST2 = float64_to_float32(FDT0, &env->fp_status);
1753 dd016883 bellard
    DEBUG_FPU_STATE();
1754 dd016883 bellard
    RETURN();
1755 dd016883 bellard
}
1756 6ea83fed bellard
FLOAT_OP(cvts, w)
1757 6ea83fed bellard
{
1758 6ea83fed bellard
    FST2 = int32_to_float32(WT0, &env->fp_status);
1759 6ea83fed bellard
    DEBUG_FPU_STATE();
1760 6ea83fed bellard
    RETURN();
1761 6ea83fed bellard
}
1762 6ea83fed bellard
FLOAT_OP(cvtw, s)
1763 6ea83fed bellard
{
1764 6ea83fed bellard
    WT2 = float32_to_int32(FST0, &env->fp_status);
1765 6ea83fed bellard
    DEBUG_FPU_STATE();
1766 6ea83fed bellard
    RETURN();
1767 6ea83fed bellard
}
1768 6ea83fed bellard
FLOAT_OP(cvtw, d)
1769 6ea83fed bellard
{
1770 6ea83fed bellard
    WT2 = float64_to_int32(FDT0, &env->fp_status);
1771 6ea83fed bellard
    DEBUG_FPU_STATE();
1772 6ea83fed bellard
    RETURN();
1773 6ea83fed bellard
}
1774 6ea83fed bellard
1775 6ea83fed bellard
FLOAT_OP(roundw, d)
1776 6ea83fed bellard
{
1777 6ea83fed bellard
    set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1778 6ea83fed bellard
    WT2 = float64_round_to_int(FDT0, &env->fp_status);
1779 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1780 6ea83fed bellard
1781 6ea83fed bellard
    DEBUG_FPU_STATE();
1782 6ea83fed bellard
    RETURN();
1783 6ea83fed bellard
}
1784 6ea83fed bellard
FLOAT_OP(roundw, s)
1785 6ea83fed bellard
{
1786 6ea83fed bellard
    set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1787 6ea83fed bellard
    WT2 = float32_round_to_int(FST0, &env->fp_status);
1788 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1789 6ea83fed bellard
    DEBUG_FPU_STATE();
1790 6ea83fed bellard
    RETURN();
1791 6ea83fed bellard
}
1792 6ea83fed bellard
1793 6ea83fed bellard
FLOAT_OP(truncw, d)
1794 6ea83fed bellard
{
1795 6ea83fed bellard
    WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status);
1796 6ea83fed bellard
    DEBUG_FPU_STATE();
1797 6ea83fed bellard
    RETURN();
1798 6ea83fed bellard
}
1799 6ea83fed bellard
FLOAT_OP(truncw, s)
1800 6ea83fed bellard
{
1801 6ea83fed bellard
    WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status);
1802 6ea83fed bellard
    DEBUG_FPU_STATE();
1803 6ea83fed bellard
    RETURN();
1804 6ea83fed bellard
}
1805 6ea83fed bellard
1806 6ea83fed bellard
FLOAT_OP(ceilw, d)
1807 6ea83fed bellard
{
1808 6ea83fed bellard
    set_float_rounding_mode(float_round_up, &env->fp_status);
1809 6ea83fed bellard
    WT2 = float64_round_to_int(FDT0, &env->fp_status);
1810 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1811 6ea83fed bellard
1812 6ea83fed bellard
    DEBUG_FPU_STATE();
1813 6ea83fed bellard
    RETURN();
1814 6ea83fed bellard
}
1815 6ea83fed bellard
FLOAT_OP(ceilw, s)
1816 6ea83fed bellard
{
1817 6ea83fed bellard
    set_float_rounding_mode(float_round_up, &env->fp_status);
1818 6ea83fed bellard
    WT2 = float32_round_to_int(FST0, &env->fp_status);
1819 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1820 6ea83fed bellard
    DEBUG_FPU_STATE();
1821 6ea83fed bellard
    RETURN();
1822 6ea83fed bellard
}
1823 6ea83fed bellard
1824 6ea83fed bellard
FLOAT_OP(floorw, d)
1825 6ea83fed bellard
{
1826 6ea83fed bellard
    set_float_rounding_mode(float_round_down, &env->fp_status);
1827 6ea83fed bellard
    WT2 = float64_round_to_int(FDT0, &env->fp_status);
1828 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1829 6ea83fed bellard
1830 6ea83fed bellard
    DEBUG_FPU_STATE();
1831 6ea83fed bellard
    RETURN();
1832 6ea83fed bellard
}
1833 6ea83fed bellard
FLOAT_OP(floorw, s)
1834 6ea83fed bellard
{
1835 6ea83fed bellard
    set_float_rounding_mode(float_round_down, &env->fp_status);
1836 6ea83fed bellard
    WT2 = float32_round_to_int(FST0, &env->fp_status);
1837 6ea83fed bellard
    RESTORE_ROUNDING_MODE;
1838 6ea83fed bellard
    DEBUG_FPU_STATE();
1839 6ea83fed bellard
    RETURN();
1840 6ea83fed bellard
}
1841 6ea83fed bellard
1842 6ea83fed bellard
/* binary operations */
1843 6ea83fed bellard
#define FLOAT_BINOP(name) \
1844 6ea83fed bellard
FLOAT_OP(name, d)         \
1845 6ea83fed bellard
{                         \
1846 6ea83fed bellard
    FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status);    \
1847 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1848 6ea83fed bellard
}                         \
1849 6ea83fed bellard
FLOAT_OP(name, s)         \
1850 6ea83fed bellard
{                         \
1851 6ea83fed bellard
    FST2 = float32_ ## name (FST0, FST1, &env->fp_status);    \
1852 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1853 6ea83fed bellard
}
1854 6ea83fed bellard
FLOAT_BINOP(add)
1855 6ea83fed bellard
FLOAT_BINOP(sub)
1856 6ea83fed bellard
FLOAT_BINOP(mul)
1857 6ea83fed bellard
FLOAT_BINOP(div)
1858 6ea83fed bellard
#undef FLOAT_BINOP
1859 6ea83fed bellard
1860 6ea83fed bellard
/* unary operations, modifying fp status  */
1861 6ea83fed bellard
#define FLOAT_UNOP(name)  \
1862 6ea83fed bellard
FLOAT_OP(name, d)         \
1863 6ea83fed bellard
{                         \
1864 6ea83fed bellard
    FDT2 = float64_ ## name(FDT0, &env->fp_status);   \
1865 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1866 6ea83fed bellard
}                         \
1867 6ea83fed bellard
FLOAT_OP(name, s)         \
1868 6ea83fed bellard
{                         \
1869 6ea83fed bellard
    FST2 = float32_ ## name(FST0, &env->fp_status);   \
1870 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1871 6ea83fed bellard
}
1872 6ea83fed bellard
FLOAT_UNOP(sqrt)
1873 6ea83fed bellard
#undef FLOAT_UNOP
1874 6ea83fed bellard
1875 6ea83fed bellard
/* unary operations, not modifying fp status  */
1876 6ea83fed bellard
#define FLOAT_UNOP(name)  \
1877 6ea83fed bellard
FLOAT_OP(name, d)         \
1878 6ea83fed bellard
{                         \
1879 6ea83fed bellard
    FDT2 = float64_ ## name(FDT0);   \
1880 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1881 6ea83fed bellard
}                         \
1882 6ea83fed bellard
FLOAT_OP(name, s)         \
1883 6ea83fed bellard
{                         \
1884 6ea83fed bellard
    FST2 = float32_ ## name(FST0);   \
1885 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1886 6ea83fed bellard
}
1887 6ea83fed bellard
FLOAT_UNOP(abs)
1888 6ea83fed bellard
FLOAT_UNOP(chs)
1889 6ea83fed bellard
#undef FLOAT_UNOP
1890 6ea83fed bellard
1891 6ea83fed bellard
FLOAT_OP(mov, d)
1892 6ea83fed bellard
{
1893 6ea83fed bellard
    FDT2 = FDT0;
1894 6ea83fed bellard
    DEBUG_FPU_STATE();
1895 6ea83fed bellard
    RETURN();
1896 6ea83fed bellard
}
1897 6ea83fed bellard
FLOAT_OP(mov, s)
1898 6ea83fed bellard
{
1899 6ea83fed bellard
    FST2 = FST0;
1900 6ea83fed bellard
    DEBUG_FPU_STATE();
1901 6ea83fed bellard
    RETURN();
1902 6ea83fed bellard
}
1903 6ea83fed bellard
1904 6ea83fed bellard
#ifdef CONFIG_SOFTFLOAT
1905 6ea83fed bellard
#define clear_invalid() do {                                \
1906 6ea83fed bellard
    int flags = get_float_exception_flags(&env->fp_status); \
1907 6ea83fed bellard
    flags &= ~float_flag_invalid;                           \
1908 6ea83fed bellard
    set_float_exception_flags(flags, &env->fp_status);      \
1909 6ea83fed bellard
} while(0)
1910 6ea83fed bellard
#else
1911 6ea83fed bellard
#define clear_invalid() do { } while(0)
1912 6ea83fed bellard
#endif
1913 6ea83fed bellard
1914 6ea83fed bellard
extern void dump_fpu_s(CPUState *env);
1915 6ea83fed bellard
1916 6ea83fed bellard
#define FOP_COND(fmt, op, sig, cond)           \
1917 6ea83fed bellard
void op_cmp_ ## fmt ## _ ## op (void)          \
1918 6ea83fed bellard
{                                              \
1919 6ea83fed bellard
    if (cond)                                  \
1920 6ea83fed bellard
        SET_FP_COND(env->fcr31);               \
1921 6ea83fed bellard
    else                                       \
1922 6ea83fed bellard
        CLEAR_FP_COND(env->fcr31);             \
1923 6ea83fed bellard
    if (!sig)                                  \
1924 6ea83fed bellard
        clear_invalid();                       \
1925 6ea83fed bellard
    /*CALL_FROM_TB1(dump_fpu_s, env);*/ \
1926 6ea83fed bellard
    DEBUG_FPU_STATE();                         \
1927 6ea83fed bellard
    RETURN();                                  \
1928 6ea83fed bellard
}
1929 6ea83fed bellard
1930 569f5d66 bellard
int float64_is_unordered(float64 a, float64 b STATUS_PARAM)
1931 6ea83fed bellard
{
1932 6ea83fed bellard
    if (float64_is_nan(a) || float64_is_nan(b)) {
1933 6ea83fed bellard
        float_raise(float_flag_invalid, status);
1934 6ea83fed bellard
        return 1;
1935 6ea83fed bellard
    }
1936 6ea83fed bellard
    else {
1937 6ea83fed bellard
        return 0;
1938 6ea83fed bellard
    }
1939 6ea83fed bellard
}
1940 6ea83fed bellard
1941 6ea83fed bellard
FOP_COND(d, f,   0,                                                      0) 
1942 6ea83fed bellard
FOP_COND(d, un,  0, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1943 6ea83fed bellard
FOP_COND(d, eq,  0,                                                      float64_eq(FDT0, FDT1, &env->fp_status))
1944 6ea83fed bellard
FOP_COND(d, ueq, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1945 6ea83fed bellard
FOP_COND(d, olt, 0,                                                      float64_lt(FDT0, FDT1, &env->fp_status))
1946 6ea83fed bellard
FOP_COND(d, ult, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1947 6ea83fed bellard
FOP_COND(d, ole, 0,                                                      float64_le(FDT0, FDT1, &env->fp_status))
1948 6ea83fed bellard
FOP_COND(d, ule, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1949 6ea83fed bellard
/* NOTE: the comma operator will make "cond" to eval to false,
1950 6ea83fed bellard
 * but float*_is_unordered() is still called
1951 6ea83fed bellard
 */
1952 6ea83fed bellard
FOP_COND(d, sf,  1,                                                      (float64_is_unordered(FDT0, FDT1, &env->fp_status), 0))
1953 6ea83fed bellard
FOP_COND(d, ngle,1, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1954 6ea83fed bellard
FOP_COND(d, seq, 1,                                                      float64_eq(FDT0, FDT1, &env->fp_status))
1955 6ea83fed bellard
FOP_COND(d, ngl, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1956 6ea83fed bellard
FOP_COND(d, lt,  1,                                                      float64_lt(FDT0, FDT1, &env->fp_status))
1957 6ea83fed bellard
FOP_COND(d, nge, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1958 6ea83fed bellard
FOP_COND(d, le,  1,                                                      float64_le(FDT0, FDT1, &env->fp_status))
1959 6ea83fed bellard
FOP_COND(d, ngt, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1960 6ea83fed bellard
1961 6ea83fed bellard
flag float32_is_unordered(float32 a, float32 b STATUS_PARAM)
1962 6ea83fed bellard
{
1963 6ea83fed bellard
    extern flag float32_is_nan( float32 a );
1964 6ea83fed bellard
    if (float32_is_nan(a) || float32_is_nan(b)) {
1965 6ea83fed bellard
        float_raise(float_flag_invalid, status);
1966 6ea83fed bellard
        return 1;
1967 6ea83fed bellard
    }
1968 6ea83fed bellard
    else {
1969 6ea83fed bellard
        return 0;
1970 6ea83fed bellard
    }
1971 6ea83fed bellard
}
1972 6ea83fed bellard
1973 6ea83fed bellard
/* NOTE: the comma operator will make "cond" to eval to false,
1974 6ea83fed bellard
 * but float*_is_unordered() is still called
1975 6ea83fed bellard
 */
1976 6ea83fed bellard
FOP_COND(s, f,   0,                                                      0) 
1977 6ea83fed bellard
FOP_COND(s, un,  0, float32_is_unordered(FST1, FST0, &env->fp_status))
1978 6ea83fed bellard
FOP_COND(s, eq,  0,                                                      float32_eq(FST0, FST1, &env->fp_status))
1979 6ea83fed bellard
FOP_COND(s, ueq, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1980 6ea83fed bellard
FOP_COND(s, olt, 0,                                                      float32_lt(FST0, FST1, &env->fp_status))
1981 6ea83fed bellard
FOP_COND(s, ult, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1982 6ea83fed bellard
FOP_COND(s, ole, 0,                                                      float32_le(FST0, FST1, &env->fp_status))
1983 6ea83fed bellard
FOP_COND(s, ule, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
1984 6ea83fed bellard
/* NOTE: the comma operator will make "cond" to eval to false,
1985 6ea83fed bellard
 * but float*_is_unordered() is still called
1986 6ea83fed bellard
 */
1987 6ea83fed bellard
FOP_COND(s, sf,  1,                                                      (float32_is_unordered(FST0, FST1, &env->fp_status), 0))
1988 6ea83fed bellard
FOP_COND(s, ngle,1, float32_is_unordered(FST1, FST0, &env->fp_status))
1989 6ea83fed bellard
FOP_COND(s, seq, 1,                                                      float32_eq(FST0, FST1, &env->fp_status))
1990 6ea83fed bellard
FOP_COND(s, ngl, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1991 6ea83fed bellard
FOP_COND(s, lt,  1,                                                      float32_lt(FST0, FST1, &env->fp_status))
1992 6ea83fed bellard
FOP_COND(s, nge, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1993 6ea83fed bellard
FOP_COND(s, le,  1,                                                      float32_le(FST0, FST1, &env->fp_status))
1994 6ea83fed bellard
FOP_COND(s, ngt, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
1995 6ea83fed bellard
1996 6ea83fed bellard
void op_bc1f (void)
1997 6ea83fed bellard
{
1998 6ea83fed bellard
    T0 = ! IS_FP_COND_SET(env->fcr31);
1999 6ea83fed bellard
    DEBUG_FPU_STATE();
2000 6ea83fed bellard
    RETURN();
2001 6ea83fed bellard
}
2002 6ea83fed bellard
2003 6ea83fed bellard
void op_bc1t (void)
2004 6ea83fed bellard
{
2005 6ea83fed bellard
    T0 = IS_FP_COND_SET(env->fcr31);
2006 6ea83fed bellard
    DEBUG_FPU_STATE();
2007 6ea83fed bellard
    RETURN();
2008 6ea83fed bellard
}
2009 6ea83fed bellard
2010 6af0bf9c bellard
#if defined(MIPS_USES_R4K_TLB)
2011 6af0bf9c bellard
void op_tlbwi (void)
2012 6af0bf9c bellard
{
2013 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbwi);
2014 6af0bf9c bellard
    RETURN();
2015 6af0bf9c bellard
}
2016 6af0bf9c bellard
2017 6af0bf9c bellard
void op_tlbwr (void)
2018 6af0bf9c bellard
{
2019 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbwr);
2020 6af0bf9c bellard
    RETURN();
2021 6af0bf9c bellard
}
2022 6af0bf9c bellard
2023 6af0bf9c bellard
void op_tlbp (void)
2024 6af0bf9c bellard
{
2025 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbp);
2026 6af0bf9c bellard
    RETURN();
2027 6af0bf9c bellard
}
2028 6af0bf9c bellard
2029 6af0bf9c bellard
void op_tlbr (void)
2030 6af0bf9c bellard
{
2031 6af0bf9c bellard
    CALL_FROM_TB0(do_tlbr);
2032 6af0bf9c bellard
    RETURN();
2033 6af0bf9c bellard
}
2034 6af0bf9c bellard
#endif
2035 6af0bf9c bellard
2036 6af0bf9c bellard
/* Specials */
2037 6f5b89a0 ths
#if defined (CONFIG_USER_ONLY)
2038 6f5b89a0 ths
void op_tls_value (void)
2039 6f5b89a0 ths
{
2040 6f5b89a0 ths
  T0 = env->tls_value;
2041 6f5b89a0 ths
}
2042 6f5b89a0 ths
#endif
2043 6f5b89a0 ths
2044 6af0bf9c bellard
void op_pmon (void)
2045 6af0bf9c bellard
{
2046 6af0bf9c bellard
    CALL_FROM_TB1(do_pmon, PARAM1);
2047 7a387fff ths
    RETURN();
2048 7a387fff ths
}
2049 7a387fff ths
2050 7a387fff ths
void op_di (void)
2051 7a387fff ths
{
2052 7a387fff ths
    T0 = env->CP0_Status;
2053 4de9b249 ths
    env->CP0_Status = T0 & ~(1 << CP0St_IE);
2054 4de9b249 ths
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2055 7a387fff ths
    RETURN();
2056 7a387fff ths
}
2057 7a387fff ths
2058 7a387fff ths
void op_ei (void)
2059 7a387fff ths
{
2060 7a387fff ths
    T0 = env->CP0_Status;
2061 4de9b249 ths
    env->CP0_Status = T0 | (1 << CP0St_IE);
2062 4de9b249 ths
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2063 7a387fff ths
    RETURN();
2064 6af0bf9c bellard
}
2065 6af0bf9c bellard
2066 6af0bf9c bellard
void op_trap (void)
2067 6af0bf9c bellard
{
2068 6af0bf9c bellard
    if (T0) {
2069 1579a72e ths
        CALL_FROM_TB1(do_raise_exception, EXCP_TRAP);
2070 6af0bf9c bellard
    }
2071 6af0bf9c bellard
    RETURN();
2072 6af0bf9c bellard
}
2073 6af0bf9c bellard
2074 4ad40f36 bellard
void op_debug (void)
2075 4ad40f36 bellard
{
2076 7a387fff ths
    CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
2077 7a387fff ths
    RETURN();
2078 4ad40f36 bellard
}
2079 4ad40f36 bellard
2080 6af0bf9c bellard
void op_set_lladdr (void)
2081 6af0bf9c bellard
{
2082 6af0bf9c bellard
    env->CP0_LLAddr = T2;
2083 7a387fff ths
    RETURN();
2084 6af0bf9c bellard
}
2085 6af0bf9c bellard
2086 f41c52f1 ths
void debug_pre_eret (void);
2087 f41c52f1 ths
void debug_post_eret (void);
2088 6af0bf9c bellard
void op_eret (void)
2089 6af0bf9c bellard
{
2090 f41c52f1 ths
    if (loglevel & CPU_LOG_EXEC)
2091 f41c52f1 ths
        CALL_FROM_TB0(debug_pre_eret);
2092 24c7b0e3 ths
    if (env->CP0_Status & (1 << CP0St_ERL)) {
2093 6af0bf9c bellard
        env->PC = env->CP0_ErrorEPC;
2094 24c7b0e3 ths
        env->CP0_Status &= ~(1 << CP0St_ERL);
2095 51e11d9e bellard
    } else {
2096 6af0bf9c bellard
        env->PC = env->CP0_EPC;
2097 24c7b0e3 ths
        env->CP0_Status &= ~(1 << CP0St_EXL);
2098 51e11d9e bellard
    }
2099 24c7b0e3 ths
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
2100 24c7b0e3 ths
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
2101 24c7b0e3 ths
        !(env->hflags & MIPS_HFLAG_DM) &&
2102 24c7b0e3 ths
        (env->CP0_Status & (1 << CP0St_UM)))
2103 24c7b0e3 ths
        env->hflags |= MIPS_HFLAG_UM;
2104 f41c52f1 ths
    if (loglevel & CPU_LOG_EXEC)
2105 f41c52f1 ths
        CALL_FROM_TB0(debug_post_eret);
2106 6af0bf9c bellard
    env->CP0_LLAddr = 1;
2107 7a387fff ths
    RETURN();
2108 6af0bf9c bellard
}
2109 6af0bf9c bellard
2110 6af0bf9c bellard
void op_deret (void)
2111 6af0bf9c bellard
{
2112 f41c52f1 ths
    if (loglevel & CPU_LOG_EXEC)
2113 f41c52f1 ths
        CALL_FROM_TB0(debug_pre_eret);
2114 6af0bf9c bellard
    env->PC = env->CP0_DEPC;
2115 24c7b0e3 ths
    env->hflags |= MIPS_HFLAG_DM;
2116 24c7b0e3 ths
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
2117 24c7b0e3 ths
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
2118 24c7b0e3 ths
        !(env->hflags & MIPS_HFLAG_DM) &&
2119 24c7b0e3 ths
        (env->CP0_Status & (1 << CP0St_UM)))
2120 24c7b0e3 ths
        env->hflags |= MIPS_HFLAG_UM;
2121 f41c52f1 ths
    if (loglevel & CPU_LOG_EXEC)
2122 f41c52f1 ths
        CALL_FROM_TB0(debug_post_eret);
2123 24c7b0e3 ths
    env->CP0_LLAddr = 1;
2124 7a387fff ths
    RETURN();
2125 7a387fff ths
}
2126 7a387fff ths
2127 7a387fff ths
void op_rdhwr_cpunum(void)
2128 7a387fff ths
{
2129 1579a72e ths
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2130 97428a4d ths
        (env->CP0_HWREna & (1 << 0)) ||
2131 1579a72e ths
        (env->CP0_Status & (1 << CP0St_CU0)))
2132 1579a72e ths
        T0 = env->CP0_EBase & 0x3ff;
2133 7a387fff ths
    else
2134 1579a72e ths
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2135 7a387fff ths
    RETURN();
2136 7a387fff ths
}
2137 7a387fff ths
2138 7a387fff ths
void op_rdhwr_synci_step(void)
2139 7a387fff ths
{
2140 1579a72e ths
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2141 97428a4d ths
        (env->CP0_HWREna & (1 << 1)) ||
2142 1579a72e ths
        (env->CP0_Status & (1 << CP0St_CU0)))
2143 1579a72e ths
        T0 = env->SYNCI_Step;
2144 7a387fff ths
    else
2145 1579a72e ths
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2146 7a387fff ths
    RETURN();
2147 7a387fff ths
}
2148 7a387fff ths
2149 7a387fff ths
void op_rdhwr_cc(void)
2150 7a387fff ths
{
2151 1579a72e ths
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2152 97428a4d ths
        (env->CP0_HWREna & (1 << 2)) ||
2153 1579a72e ths
        (env->CP0_Status & (1 << CP0St_CU0)))
2154 1579a72e ths
        T0 = env->CP0_Count;
2155 7a387fff ths
    else
2156 1579a72e ths
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2157 7a387fff ths
    RETURN();
2158 7a387fff ths
}
2159 7a387fff ths
2160 7a387fff ths
void op_rdhwr_ccres(void)
2161 7a387fff ths
{
2162 1579a72e ths
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2163 97428a4d ths
        (env->CP0_HWREna & (1 << 3)) ||
2164 1579a72e ths
        (env->CP0_Status & (1 << CP0St_CU0)))
2165 1579a72e ths
        T0 = env->CCRes;
2166 7a387fff ths
    else
2167 1579a72e ths
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2168 1579a72e ths
    RETURN();
2169 1579a72e ths
}
2170 1579a72e ths
2171 6af0bf9c bellard
void op_save_state (void)
2172 6af0bf9c bellard
{
2173 6af0bf9c bellard
    env->hflags = PARAM1;
2174 6af0bf9c bellard
    RETURN();
2175 6af0bf9c bellard
}
2176 6af0bf9c bellard
2177 6af0bf9c bellard
void op_save_pc (void)
2178 6af0bf9c bellard
{
2179 6af0bf9c bellard
    env->PC = PARAM1;
2180 6af0bf9c bellard
    RETURN();
2181 6af0bf9c bellard
}
2182 6af0bf9c bellard
2183 16c00cb2 ths
void op_interrupt_restart (void)
2184 16c00cb2 ths
{
2185 16c00cb2 ths
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
2186 16c00cb2 ths
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
2187 16c00cb2 ths
        !(env->hflags & MIPS_HFLAG_DM) &&
2188 16c00cb2 ths
        (env->CP0_Status & (1 << CP0St_IE)) &&
2189 16c00cb2 ths
        (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
2190 16c00cb2 ths
        env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
2191 16c00cb2 ths
        CALL_FROM_TB1(do_raise_exception, EXCP_EXT_INTERRUPT);
2192 16c00cb2 ths
    }
2193 16c00cb2 ths
    RETURN();
2194 16c00cb2 ths
}
2195 16c00cb2 ths
2196 6af0bf9c bellard
void op_raise_exception (void)
2197 6af0bf9c bellard
{
2198 6af0bf9c bellard
    CALL_FROM_TB1(do_raise_exception, PARAM1);
2199 6af0bf9c bellard
    RETURN();
2200 6af0bf9c bellard
}
2201 6af0bf9c bellard
2202 6af0bf9c bellard
void op_raise_exception_err (void)
2203 6af0bf9c bellard
{
2204 6af0bf9c bellard
    CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2);
2205 6af0bf9c bellard
    RETURN();
2206 6af0bf9c bellard
}
2207 6af0bf9c bellard
2208 6af0bf9c bellard
void op_exit_tb (void)
2209 6af0bf9c bellard
{
2210 6af0bf9c bellard
    EXIT_TB();
2211 7a387fff ths
    RETURN();
2212 6af0bf9c bellard
}
2213 6af0bf9c bellard
2214 4ad40f36 bellard
void op_wait (void)
2215 4ad40f36 bellard
{
2216 4ad40f36 bellard
    env->halted = 1;
2217 4ad40f36 bellard
    CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
2218 7a387fff ths
    RETURN();
2219 7a387fff ths
}
2220 7a387fff ths
2221 7a387fff ths
/* Bitfield operations. */
2222 7a387fff ths
void op_ext(void)
2223 7a387fff ths
{
2224 7a387fff ths
    unsigned int pos = PARAM1;
2225 7a387fff ths
    unsigned int size = PARAM2;
2226 7a387fff ths
2227 f757d6ff ths
    T0 = ((uint32_t)T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
2228 7a387fff ths
    RETURN();
2229 7a387fff ths
}
2230 7a387fff ths
2231 7a387fff ths
void op_ins(void)
2232 7a387fff ths
{
2233 7a387fff ths
    unsigned int pos = PARAM1;
2234 7a387fff ths
    unsigned int size = PARAM2;
2235 f757d6ff ths
    target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
2236 7a387fff ths
2237 171b31e7 ths
    T0 = (T0 & ~mask) | (((uint32_t)T1 << pos) & mask);
2238 7a387fff ths
    RETURN();
2239 7a387fff ths
}
2240 7a387fff ths
2241 7a387fff ths
void op_wsbh(void)
2242 7a387fff ths
{
2243 7a387fff ths
    T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
2244 7a387fff ths
    RETURN();
2245 7a387fff ths
}
2246 7a387fff ths
2247 60aa19ab ths
#ifdef TARGET_MIPS64
2248 c570fd16 ths
void op_dext(void)
2249 c570fd16 ths
{
2250 c570fd16 ths
    unsigned int pos = PARAM1;
2251 c570fd16 ths
    unsigned int size = PARAM2;
2252 c570fd16 ths
2253 f757d6ff ths
    T0 = (T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
2254 c570fd16 ths
    RETURN();
2255 c570fd16 ths
}
2256 c570fd16 ths
2257 c570fd16 ths
void op_dins(void)
2258 c570fd16 ths
{
2259 c570fd16 ths
    unsigned int pos = PARAM1;
2260 c570fd16 ths
    unsigned int size = PARAM2;
2261 f757d6ff ths
    target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
2262 c570fd16 ths
2263 171b31e7 ths
    T0 = (T0 & ~mask) | ((T1 << pos) & mask);
2264 c570fd16 ths
    RETURN();
2265 c570fd16 ths
}
2266 c570fd16 ths
2267 7a387fff ths
void op_dsbh(void)
2268 7a387fff ths
{
2269 7a387fff ths
    T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
2270 7a387fff ths
    RETURN();
2271 7a387fff ths
}
2272 7a387fff ths
2273 7a387fff ths
void op_dshd(void)
2274 7a387fff ths
{
2275 7a387fff ths
    T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
2276 7a387fff ths
    RETURN();
2277 7a387fff ths
}
2278 c570fd16 ths
#endif
2279 7a387fff ths
2280 7a387fff ths
void op_seb(void)
2281 7a387fff ths
{
2282 7a387fff ths
    T0 = ((T1 & 0xFF) ^ 0x80) - 0x80;
2283 7a387fff ths
    RETURN();
2284 7a387fff ths
}
2285 7a387fff ths
2286 7a387fff ths
void op_seh(void)
2287 7a387fff ths
{
2288 7a387fff ths
    T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000;
2289 7a387fff ths
    RETURN();
2290 4ad40f36 bellard
}