Revision fcb4a419 target-mips/translate_init.c

b/target-mips/translate_init.c
28 28 
   (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) |    \
29 29 
   (0x2 << CP0C0_K0))
30 30 

  		





  31
  
  
    
/* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line,


  		





  
  31
  
    
/* Have config2, 64 sets Icache, 16 bytes Icache line,


  		





  32
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   2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,


  		





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  33
  
    
   no coprocessor2 attached, no MDMX support attached,


  		





  34
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   no performance counters, watch registers present,


  		





  35
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   no code compression, EJTAG present, no FPU */


  		





  36
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#define MIPS_CONFIG1                                              \


  		





  37
  
  
    
((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) |              \


  		





  
  37
  
    
((1 << CP0C1_M) |                                                 \


  		





  38
  38
  
    
 (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) |      \


  		





  39
  39
  
    
 (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) |      \


  		





  40
  40
  
    
 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \


  		





  ......




  81
  81
  
    
        .name = "4Kc",


  		





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        .CP0_PRid = 0x00018000,


  		





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        .CP0_Config0 = MIPS_CONFIG0,


  		





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        .CP0_Config1 = MIPS_CONFIG1,


  		





  
  84
  
    
        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),


  		





  85
  85
  
    
        .CP0_Config2 = MIPS_CONFIG2,


  		





  86
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        .CP0_Config3 = MIPS_CONFIG3,


  		





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        .SYNCI_Step = 32,


  		





  ......




  92
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        .name = "4KEcR1",


  		





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        .CP0_PRid = 0x00018400,


  		





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  94
  
    
        .CP0_Config0 = MIPS_CONFIG0,


  		





  95
  
  
    
        .CP0_Config1 = MIPS_CONFIG1,


  		





  
  95
  
    
        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),


  		





  96
  96
  
    
        .CP0_Config2 = MIPS_CONFIG2,


  		





  97
  97
  
    
        .CP0_Config3 = MIPS_CONFIG3,


  		





  98
  98
  
    
        .SYNCI_Step = 32,


  		





  ......




  103
  103
  
    
        .name = "4KEc",


  		





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        .CP0_PRid = 0x00019000,


  		





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        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),


  		





  106
  
  
    
        .CP0_Config1 = MIPS_CONFIG1,


  		





  
  106
  
    
        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),


  		





  107
  107
  
    
        .CP0_Config2 = MIPS_CONFIG2,


  		





  108
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        .CP0_Config3 = MIPS_CONFIG3,


  		





  109
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        .SYNCI_Step = 32,


  		





  ......




  114
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        .name = "24Kc",


  		





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        .CP0_PRid = 0x00019300,


  		





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        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),


  		





  117
  
  
    
        .CP0_Config1 = MIPS_CONFIG1,


  		





  
  117
  
    
        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),


  		





  118
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        .CP0_Config2 = MIPS_CONFIG2,


  		





  119
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        .CP0_Config3 = MIPS_CONFIG3,


  		





  120
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        .SYNCI_Step = 32,


  		





  ......




  125
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        .name = "24Kf",


  		





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        .CP0_PRid = 0x00019300,


  		





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        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),


  		





  128
  
  
    
        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),


  		





  
  128
  
    
        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU),


  		





  129
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        .CP0_Config2 = MIPS_CONFIG2,


  		





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        .CP0_Config3 = MIPS_CONFIG3,


  		





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        .SYNCI_Step = 32,


  		





  ......




  137
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        .name = "R4000",


  		





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        .CP0_PRid = 0x00000400,


  		





  139
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        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),


  		





  140
  
  
    
        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),


  		





  
  140
  
    
        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU),


  		





  141
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        .CP0_Config2 = MIPS_CONFIG2,


  		





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        .CP0_Config3 = MIPS_CONFIG3,


  		





  143
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        .SYNCI_Step = 16,


  		





  ......




  192
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    env->SYNCI_Step = def->SYNCI_Step;


  		





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    env->CCRes = def->CCRes;


  		





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    env->fcr0 = def->CP1_fcr0;


  		





  
  195
  
    
#if defined (MIPS_USES_R4K_TLB)


  		





  
  196
  
    
    env->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);


  		





  
  197
  
    
    env->CP0_Random = env->nb_tlb - 1;


  		





  
  198
  
    
    env->tlb_in_use = env->nb_tlb;


  		





  
  199
  
    
#endif


  		





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    return 0;


  		





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}


  		












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