root / target-mips / op_helper.c @ fcb4a419
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/*
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* MIPS emulation helpers for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdlib.h> |
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#include "exec.h" |
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#define GETPC() (__builtin_return_address(0)) |
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/*****************************************************************************/
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/* Exceptions processing helpers */
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void cpu_loop_exit(void) |
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{
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longjmp(env->jmp_env, 1);
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} |
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void do_raise_exception_err (uint32_t exception, int error_code) |
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{
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#if 1 |
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if (logfile && exception < 0x100) |
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fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
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#endif
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env->exception_index = exception; |
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env->error_code = error_code; |
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T0 = 0;
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cpu_loop_exit(); |
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} |
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void do_raise_exception (uint32_t exception)
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{
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do_raise_exception_err(exception, 0);
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} |
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void do_restore_state (void *pc_ptr) |
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{
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TranslationBlock *tb; |
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unsigned long pc = (unsigned long) pc_ptr; |
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tb = tb_find_pc (pc); |
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cpu_restore_state (tb, env, pc, NULL);
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} |
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void do_raise_exception_direct_err (uint32_t exception, int error_code) |
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{
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do_restore_state (GETPC ()); |
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do_raise_exception_err (exception, error_code); |
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} |
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void do_raise_exception_direct (uint32_t exception)
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{
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do_raise_exception_direct_err (exception, 0);
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} |
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#define MEMSUFFIX _raw
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#include "op_helper_mem.c" |
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#undef MEMSUFFIX
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_helper_mem.c" |
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#undef MEMSUFFIX
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#define MEMSUFFIX _kernel
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#include "op_helper_mem.c" |
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#undef MEMSUFFIX
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#endif
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#ifdef TARGET_MIPS64
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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/* Those might call libgcc functions. */
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void do_dsll (void) |
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{
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T0 = T0 << T1; |
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} |
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void do_dsll32 (void) |
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{
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T0 = T0 << (T1 + 32);
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} |
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void do_dsra (void) |
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{
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T0 = (int64_t)T0 >> T1; |
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} |
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void do_dsra32 (void) |
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{
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T0 = (int64_t)T0 >> (T1 + 32);
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} |
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void do_dsrl (void) |
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{
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T0 = T0 >> T1; |
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} |
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void do_dsrl32 (void) |
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{
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T0 = T0 >> (T1 + 32);
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} |
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void do_drotr (void) |
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{
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target_ulong tmp; |
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if (T1) {
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tmp = T0 << (0x40 - T1);
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T0 = (T0 >> T1) | tmp; |
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} |
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} |
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void do_drotr32 (void) |
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{
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target_ulong tmp; |
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if (T1) {
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tmp = T0 << (0x40 - (32 + T1)); |
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T0 = (T0 >> (32 + T1)) | tmp;
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} |
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} |
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void do_dsllv (void) |
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{
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T0 = T1 << (T0 & 0x3F);
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} |
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void do_dsrav (void) |
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{
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T0 = (int64_t)T1 >> (T0 & 0x3F);
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} |
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void do_dsrlv (void) |
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{
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T0 = T1 >> (T0 & 0x3F);
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} |
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void do_drotrv (void) |
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{
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target_ulong tmp; |
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T0 &= 0x3F;
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if (T0) {
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tmp = T1 << (0x40 - T0);
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T0 = (T1 >> T0) | tmp; |
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} else
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T0 = T1; |
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} |
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#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
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#endif /* TARGET_MIPS64 */ |
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/* 64 bits arithmetic for 32 bits hosts */
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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static inline uint64_t get_HILO (void) |
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{
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return (env->HI << 32) | (uint32_t)env->LO; |
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} |
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static inline void set_HILO (uint64_t HILO) |
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{
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env->LO = (int32_t)HILO; |
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env->HI = (int32_t)(HILO >> 32);
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} |
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void do_mult (void) |
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{
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set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
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} |
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void do_multu (void) |
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{
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set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
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} |
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void do_madd (void) |
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{
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int64_t tmp; |
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tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
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set_HILO((int64_t)get_HILO() + tmp); |
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} |
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void do_maddu (void) |
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{
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uint64_t tmp; |
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tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
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set_HILO(get_HILO() + tmp); |
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} |
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void do_msub (void) |
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{
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int64_t tmp; |
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tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
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set_HILO((int64_t)get_HILO() - tmp); |
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} |
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void do_msubu (void) |
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{
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uint64_t tmp; |
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tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
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set_HILO(get_HILO() - tmp); |
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} |
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#endif
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#if HOST_LONG_BITS < 64 |
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void do_div (void) |
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{
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/* 64bit datatypes because we may see overflow/underflow. */
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if (T1 != 0) { |
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env->LO = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1); |
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env->HI = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1); |
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} |
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} |
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#endif
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#ifdef TARGET_MIPS64
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void do_dmult (void) |
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{
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env->LO = (int64_t)T0 * (int64_t)T1; |
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/* XXX */
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env->HI = (env->LO | (1ULL << 63)) ? ~0ULL : 0ULL; |
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} |
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void do_dmultu (void) |
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{
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env->LO = T0 * T1; |
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/* XXX */
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env->HI = 0;
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} |
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void do_ddiv (void) |
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{
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if (T1 != 0) { |
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lldiv_t res = lldiv((int64_t)T0, (int64_t)T1); |
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env->LO = res.quot; |
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env->HI = res.rem; |
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} |
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} |
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void do_ddivu (void) |
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{
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if (T1 != 0) { |
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/* XXX: lldivu? */
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lldiv_t res = lldiv(T0, T1); |
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env->LO = (uint64_t)res.quot; |
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env->HI = (uint64_t)res.rem; |
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} |
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} |
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#endif
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#if defined(CONFIG_USER_ONLY)
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void do_mfc0_random (void) |
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{
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cpu_abort(env, "mfc0 random\n");
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} |
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void do_mfc0_count (void) |
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{
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cpu_abort(env, "mfc0 count\n");
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} |
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void cpu_mips_store_count(CPUState *env, uint32_t value)
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{
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cpu_abort(env, "mtc0 count\n");
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} |
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void cpu_mips_store_compare(CPUState *env, uint32_t value)
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{
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cpu_abort(env, "mtc0 compare\n");
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} |
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void cpu_mips_update_irq(CPUState *env)
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{
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cpu_abort(env, "mtc0 status / mtc0 cause\n");
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} |
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void do_mtc0_status_debug(uint32_t old, uint32_t val)
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{
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cpu_abort(env, "mtc0 status debug\n");
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} |
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void do_mtc0_status_irqraise_debug (void) |
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{
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cpu_abort(env, "mtc0 status irqraise debug\n");
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} |
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void do_tlbwi (void) |
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{
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cpu_abort(env, "tlbwi\n");
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} |
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void do_tlbwr (void) |
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{
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cpu_abort(env, "tlbwr\n");
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} |
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void do_tlbp (void) |
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{
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cpu_abort(env, "tlbp\n");
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} |
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void do_tlbr (void) |
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{
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cpu_abort(env, "tlbr\n");
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} |
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void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
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{
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cpu_abort(env, "mips_tlb_flush\n");
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} |
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#else
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/* CP0 helpers */
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void do_mfc0_random (void) |
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{
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T0 = (int32_t)cpu_mips_get_random(env); |
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} |
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void do_mfc0_count (void) |
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{
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T0 = (int32_t)cpu_mips_get_count(env); |
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} |
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void do_mtc0_status_debug(uint32_t old, uint32_t val)
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{
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fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
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old, old & env->CP0_Cause & CP0Ca_IP_mask, |
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val, val & env->CP0_Cause & CP0Ca_IP_mask, |
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env->CP0_Cause); |
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(env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
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: fputs("\n", logfile);
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} |
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void do_mtc0_status_irqraise_debug(void) |
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{
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fprintf(logfile, "Raise pending IRQs\n");
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} |
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void fpu_handle_exception(void) |
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{
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#ifdef CONFIG_SOFTFLOAT
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int flags = get_float_exception_flags(&env->fp_status);
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unsigned int cpuflags = 0, enable, cause = 0; |
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enable = GET_FP_ENABLE(env->fcr31); |
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/* determine current flags */
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if (flags & float_flag_invalid) {
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cpuflags |= FP_INVALID; |
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cause |= FP_INVALID & enable; |
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} |
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if (flags & float_flag_divbyzero) {
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cpuflags |= FP_DIV0; |
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cause |= FP_DIV0 & enable; |
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} |
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if (flags & float_flag_overflow) {
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cpuflags |= FP_OVERFLOW; |
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cause |= FP_OVERFLOW & enable; |
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} |
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if (flags & float_flag_underflow) {
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cpuflags |= FP_UNDERFLOW; |
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cause |= FP_UNDERFLOW & enable; |
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} |
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if (flags & float_flag_inexact) {
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cpuflags |= FP_INEXACT; |
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cause |= FP_INEXACT & enable; |
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} |
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SET_FP_FLAGS(env->fcr31, cpuflags); |
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SET_FP_CAUSE(env->fcr31, cause); |
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#else
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SET_FP_FLAGS(env->fcr31, 0);
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SET_FP_CAUSE(env->fcr31, 0);
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#endif
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} |
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/* TLB management */
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#if defined(MIPS_USES_R4K_TLB)
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void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
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{
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/* Flush qemu's TLB and discard all shadowed entries. */
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tlb_flush (env, flush_global); |
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env->tlb_in_use = env->nb_tlb; |
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} |
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static void mips_tlb_flush_extra (CPUState *env, int first) |
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{
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/* Discard entries from env->tlb[first] onwards. */
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while (env->tlb_in_use > first) {
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invalidate_tlb(env, --env->tlb_in_use, 0);
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} |
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} |
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static void fill_tlb (int idx) |
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{
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tlb_t *tlb; |
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|
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/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
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tlb = &env->tlb[idx]; |
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tlb->VPN = env->CP0_EntryHi & ~(target_ulong)0x1FFF;
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tlb->ASID = env->CP0_EntryHi & 0xFF;
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tlb->PageMask = env->CP0_PageMask; |
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tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
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tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
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tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
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tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
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tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
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tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
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tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
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tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
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tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
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} |
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|
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void do_tlbwi (void) |
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{
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/* Discard cached TLB entries. We could avoid doing this if the
|
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tlbwi is just upgrading access permissions on the current entry;
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that might be a further win. */
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mips_tlb_flush_extra (env, env->nb_tlb); |
| 434 |
|
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invalidate_tlb(env, env->CP0_Index % env->nb_tlb, 0);
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fill_tlb(env->CP0_Index % env->nb_tlb); |
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} |
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|
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void do_tlbwr (void) |
| 440 |
{
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int r = cpu_mips_get_random(env);
|
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|
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invalidate_tlb(env, r, 1);
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fill_tlb(r); |
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} |
| 446 |
|
| 447 |
void do_tlbp (void) |
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{
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tlb_t *tlb; |
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target_ulong tag; |
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uint8_t ASID; |
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int i;
|
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|
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tag = env->CP0_EntryHi & (int32_t)0xFFFFE000;
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ASID = env->CP0_EntryHi & 0xFF;
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for (i = 0; i < env->nb_tlb; i++) { |
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tlb = &env->tlb[i]; |
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/* Check ASID, virtual page number & size */
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if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { |
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/* TLB match */
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env->CP0_Index = i; |
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break;
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} |
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} |
| 465 |
if (i == env->nb_tlb) {
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/* No match. Discard any shadow entries, if any of them match. */
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for (i = env->nb_tlb; i < env->tlb_in_use; i++) {
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tlb = &env->tlb[i]; |
| 469 |
|
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/* Check ASID, virtual page number & size */
|
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if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { |
| 472 |
mips_tlb_flush_extra (env, i); |
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break;
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} |
| 475 |
} |
| 476 |
|
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env->CP0_Index |= 0x80000000;
|
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} |
| 479 |
} |
| 480 |
|
| 481 |
void do_tlbr (void) |
| 482 |
{
|
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tlb_t *tlb; |
| 484 |
uint8_t ASID; |
| 485 |
|
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ASID = env->CP0_EntryHi & 0xFF;
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tlb = &env->tlb[env->CP0_Index % env->nb_tlb]; |
| 488 |
|
| 489 |
/* If this will change the current ASID, flush qemu's TLB. */
|
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if (ASID != tlb->ASID)
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cpu_mips_tlb_flush (env, 1);
|
| 492 |
|
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mips_tlb_flush_extra(env, env->nb_tlb); |
| 494 |
|
| 495 |
env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
| 496 |
env->CP0_PageMask = tlb->PageMask; |
| 497 |
env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
| 498 |
(tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
| 499 |
env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
| 500 |
(tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
| 501 |
} |
| 502 |
#endif
|
| 503 |
|
| 504 |
#endif /* !CONFIG_USER_ONLY */ |
| 505 |
|
| 506 |
void dump_ldst (const unsigned char *func) |
| 507 |
{
|
| 508 |
if (loglevel)
|
| 509 |
fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1); |
| 510 |
} |
| 511 |
|
| 512 |
void dump_sc (void) |
| 513 |
{
|
| 514 |
if (loglevel) {
|
| 515 |
fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__, |
| 516 |
T1, T0, env->CP0_LLAddr); |
| 517 |
} |
| 518 |
} |
| 519 |
|
| 520 |
void debug_pre_eret (void) |
| 521 |
{
|
| 522 |
fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
| 523 |
env->PC, env->CP0_EPC); |
| 524 |
if (env->CP0_Status & (1 << CP0St_ERL)) |
| 525 |
fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
| 526 |
if (env->hflags & MIPS_HFLAG_DM)
|
| 527 |
fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
| 528 |
fputs("\n", logfile);
|
| 529 |
} |
| 530 |
|
| 531 |
void debug_post_eret (void) |
| 532 |
{
|
| 533 |
fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
| 534 |
env->PC, env->CP0_EPC); |
| 535 |
if (env->CP0_Status & (1 << CP0St_ERL)) |
| 536 |
fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
| 537 |
if (env->hflags & MIPS_HFLAG_DM)
|
| 538 |
fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
| 539 |
if (env->hflags & MIPS_HFLAG_UM)
|
| 540 |
fputs(", UM\n", logfile);
|
| 541 |
else
|
| 542 |
fputs("\n", logfile);
|
| 543 |
} |
| 544 |
|
| 545 |
void do_pmon (int function) |
| 546 |
{
|
| 547 |
function /= 2;
|
| 548 |
switch (function) {
|
| 549 |
case 2: /* TODO: char inbyte(int waitflag); */ |
| 550 |
if (env->gpr[4] == 0) |
| 551 |
env->gpr[2] = -1; |
| 552 |
/* Fall through */
|
| 553 |
case 11: /* TODO: char inbyte (void); */ |
| 554 |
env->gpr[2] = -1; |
| 555 |
break;
|
| 556 |
case 3: |
| 557 |
case 12: |
| 558 |
printf("%c", (char)(env->gpr[4] & 0xFF)); |
| 559 |
break;
|
| 560 |
case 17: |
| 561 |
break;
|
| 562 |
case 158: |
| 563 |
{
|
| 564 |
unsigned char *fmt = (void *)(unsigned long)env->gpr[4]; |
| 565 |
printf("%s", fmt);
|
| 566 |
} |
| 567 |
break;
|
| 568 |
} |
| 569 |
} |
| 570 |
|
| 571 |
#if !defined(CONFIG_USER_ONLY)
|
| 572 |
|
| 573 |
static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
| 574 |
|
| 575 |
#define MMUSUFFIX _mmu
|
| 576 |
#define ALIGNED_ONLY
|
| 577 |
|
| 578 |
#define SHIFT 0 |
| 579 |
#include "softmmu_template.h" |
| 580 |
|
| 581 |
#define SHIFT 1 |
| 582 |
#include "softmmu_template.h" |
| 583 |
|
| 584 |
#define SHIFT 2 |
| 585 |
#include "softmmu_template.h" |
| 586 |
|
| 587 |
#define SHIFT 3 |
| 588 |
#include "softmmu_template.h" |
| 589 |
|
| 590 |
static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
| 591 |
{
|
| 592 |
env->CP0_BadVAddr = addr; |
| 593 |
do_restore_state (retaddr); |
| 594 |
do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
| 595 |
} |
| 596 |
|
| 597 |
void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr) |
| 598 |
{
|
| 599 |
TranslationBlock *tb; |
| 600 |
CPUState *saved_env; |
| 601 |
unsigned long pc; |
| 602 |
int ret;
|
| 603 |
|
| 604 |
/* XXX: hack to restore env in all cases, even if not called from
|
| 605 |
generated code */
|
| 606 |
saved_env = env; |
| 607 |
env = cpu_single_env; |
| 608 |
ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
| 609 |
if (ret) {
|
| 610 |
if (retaddr) {
|
| 611 |
/* now we have a real cpu fault */
|
| 612 |
pc = (unsigned long)retaddr; |
| 613 |
tb = tb_find_pc(pc); |
| 614 |
if (tb) {
|
| 615 |
/* the PC is inside the translated code. It means that we have
|
| 616 |
a virtual CPU fault */
|
| 617 |
cpu_restore_state(tb, env, pc, NULL);
|
| 618 |
} |
| 619 |
} |
| 620 |
do_raise_exception_err(env->exception_index, env->error_code); |
| 621 |
} |
| 622 |
env = saved_env; |
| 623 |
} |
| 624 |
|
| 625 |
#endif
|