Revision fcc72045

b/target-sparc/cpu.h
40 40
#define TT_TOVF     0x0a
41 41
#define TT_EXTINT   0x10
42 42
#define TT_DIV_ZERO 0x2a
43
#define TT_NCP_INSN 0x24
43 44
#define TT_TRAP     0x80
44 45
#else
45 46
#define TT_TFAULT   0x08
b/target-sparc/translate.c
1746 1746
		    gen_op_sra();
1747 1747
		gen_movl_T0_reg(rd);
1748 1748
#endif
1749
	    } else if (xop < 0x38) {
1749
            } else if (xop < 0x36) {
1750 1750
                rs1 = GET_FIELD(insn, 13, 17);
1751 1751
		gen_movl_reg_T0(rs1);
1752 1752
		if (IS_IMM) {	/* immediate */
......
2162 2162
			goto illegal_insn;
2163 2163
		    }
2164 2164
		}
2165
            } else if (xop == 0x36 || xop == 0x37) { /* CPop1 & CPop2,
2166
                                                        V9 impdep1 &
2167
                                                        impdep2 */
2168
#ifdef TARGET_SPARC64
2169
	        goto illegal_insn;
2170
#else
2171
	        goto ncp_insn;
2172
#endif
2165 2173
#ifdef TARGET_SPARC64
2166 2174
	    } else if (xop == 0x39) { /* V9 return */
2167 2175
                rs1 = GET_FIELD(insn, 13, 17);
......
2410 2418
		    break;
2411 2419

  
2412 2420
#ifndef TARGET_SPARC64
2421
		case 0x30: /* ldc */
2422
		case 0x31: /* ldcsr */
2423
		case 0x33: /* lddc */
2424
		case 0x34: /* stc */
2425
		case 0x35: /* stcsr */
2426
		case 0x36: /* stdcq */
2427
		case 0x37: /* stdc */
2428
		    goto ncp_insn;
2429
		    break;
2413 2430
                    /* avoid warnings */
2414 2431
                    (void) &gen_op_stfa;
2415 2432
                    (void) &gen_op_stdfa;
......
2618 2635
    save_state(dc);
2619 2636
    gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
2620 2637
    dc->is_br = 1;
2638
    return;
2639
#ifndef TARGET_SPARC64
2640
 ncp_insn:
2641
    save_state(dc);
2642
    gen_op_exception(TT_NCP_INSN);
2643
    dc->is_br = 1;
2644
    return;
2645
#endif
2621 2646
}
2622 2647

  
2623 2648
static inline int gen_intermediate_code_internal(TranslationBlock * tb,

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