Revision fd4a04eb target-mips/cpu.h

b/target-mips/cpu.h
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#define FCR0_REV 0
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    /* fcsr */
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    uint32_t fcr31;
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#define SET_FP_COND(num,env)     do { (env->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << ((num) + 23))); } while(0)
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#define CLEAR_FP_COND(num,env)   do { (env->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << ((num) + 23))); } while(0)
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#define IS_FP_COND_SET(num,env)  (((env->fcr31) & ((num) ? (1 << ((num) + 24)) : (1 << ((num) + 23)))) != 0)
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#define SET_FP_COND(num,env)     do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
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#define CLEAR_FP_COND(num,env)   do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
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#define GET_FP_COND(env)         ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1))
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#define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
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#define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
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#define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)

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