Revision fd4a04eb target-mips/translate.c
| b/target-mips/translate.c | ||
|---|---|---|
| 491 | 491 |
FGEN32(gen_op_store_fpr_WTH2, gen_op_store_fpr_WTH2_fpr); |
| 492 | 492 |
|
| 493 | 493 |
#define FOP_CONDS(type, fmt) \ |
| 494 |
static GenOpFunc1 * cond ## type ## _ ## fmt ## _table[16] = { \
|
|
| 494 |
static GenOpFunc1 * gen_op_cmp ## type ## _ ## fmt ## _table[16] = { \
|
|
| 495 | 495 |
gen_op_cmp ## type ## _ ## fmt ## _f, \ |
| 496 | 496 |
gen_op_cmp ## type ## _ ## fmt ## _un, \ |
| 497 | 497 |
gen_op_cmp ## type ## _ ## fmt ## _eq, \ |
| ... | ... | |
| 511 | 511 |
}; \ |
| 512 | 512 |
static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \ |
| 513 | 513 |
{ \
|
| 514 |
cond ## type ## _ ## fmt ## _table[n](cc); \
|
|
| 514 |
gen_op_cmp ## type ## _ ## fmt ## _table[n](cc); \
|
|
| 515 | 515 |
} |
| 516 | 516 |
|
| 517 | 517 |
FOP_CONDS(, d) |
| ... | ... | |
| 525 | 525 |
struct TranslationBlock *tb; |
| 526 | 526 |
target_ulong pc, saved_pc; |
| 527 | 527 |
uint32_t opcode; |
| 528 |
uint32_t fp_status, saved_fp_status;
|
|
| 528 |
uint32_t fp_status; |
|
| 529 | 529 |
/* Routine used to access memory */ |
| 530 | 530 |
int mem_idx; |
| 531 | 531 |
uint32_t hflags, saved_hflags; |
| 532 |
uint32_t CP0_Status; |
|
| 533 | 532 |
int bstate; |
| 534 | 533 |
target_ulong btarget; |
| 535 | 534 |
} DisasContext; |
| ... | ... | |
| 628 | 627 |
} |
| 629 | 628 |
} |
| 630 | 629 |
|
| 631 |
static inline void save_fpu_state (DisasContext *ctx)
|
|
| 630 |
static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
|
|
| 632 | 631 |
{
|
| 633 |
if (ctx->fp_status != ctx->saved_fp_status) {
|
|
| 634 |
gen_op_save_fp_status(ctx->fp_status); |
|
| 635 |
ctx->saved_fp_status = ctx->fp_status; |
|
| 632 |
ctx->saved_hflags = ctx->hflags; |
|
| 633 |
switch (ctx->hflags & MIPS_HFLAG_BMASK) {
|
|
| 634 |
case MIPS_HFLAG_BR: |
|
| 635 |
gen_op_restore_breg_target(); |
|
| 636 |
break; |
|
| 637 |
case MIPS_HFLAG_B: |
|
| 638 |
ctx->btarget = env->btarget; |
|
| 639 |
break; |
|
| 640 |
case MIPS_HFLAG_BC: |
|
| 641 |
case MIPS_HFLAG_BL: |
|
| 642 |
ctx->btarget = env->btarget; |
|
| 643 |
gen_op_restore_bcond(); |
|
| 644 |
break; |
|
| 636 | 645 |
} |
| 637 | 646 |
} |
| 638 | 647 |
|
| ... | ... | |
| 4293 | 4302 |
gen_op_save_bcond(); |
| 4294 | 4303 |
break; |
| 4295 | 4304 |
case OPC_BC1FANY2: |
| 4296 |
gen_op_bc1fany2(cc);
|
|
| 4297 |
opn = "bc1fany2";
|
|
| 4305 |
gen_op_bc1any2f(cc);
|
|
| 4306 |
opn = "bc1any2f";
|
|
| 4298 | 4307 |
goto not_likely; |
| 4299 | 4308 |
case OPC_BC1TANY2: |
| 4300 |
gen_op_bc1tany2(cc);
|
|
| 4301 |
opn = "bc1tany2";
|
|
| 4309 |
gen_op_bc1any2t(cc);
|
|
| 4310 |
opn = "bc1any2t";
|
|
| 4302 | 4311 |
goto not_likely; |
| 4303 | 4312 |
case OPC_BC1FANY4: |
| 4304 |
gen_op_bc1fany4(cc);
|
|
| 4305 |
opn = "bc1fany4";
|
|
| 4313 |
gen_op_bc1any4f(cc);
|
|
| 4314 |
opn = "bc1any4f";
|
|
| 4306 | 4315 |
goto not_likely; |
| 4307 | 4316 |
case OPC_BC1TANY4: |
| 4308 |
gen_op_bc1tany4(cc);
|
|
| 4309 |
opn = "bc1tany4";
|
|
| 4317 |
gen_op_bc1any4t(cc);
|
|
| 4318 |
opn = "bc1any4t";
|
|
| 4310 | 4319 |
not_likely: |
| 4311 | 4320 |
ctx->hflags |= MIPS_HFLAG_BC; |
| 4312 | 4321 |
gen_op_set_bcond(); |
| ... | ... | |
| 4323 | 4332 |
|
| 4324 | 4333 |
/* Coprocessor 1 (FPU) */ |
| 4325 | 4334 |
|
| 4326 |
/* verify if floating point register is valid; an operation is not defined |
|
| 4327 |
* if bit 0 of any register specification is set and the FR bit in the |
|
| 4328 |
* Status register equals zero, since the register numbers specify an |
|
| 4329 |
* even-odd pair of adjacent coprocessor general registers. When the FR bit |
|
| 4330 |
* in the Status register equals one, both even and odd register numbers |
|
| 4331 |
* are valid. This limitation exists only for 64 bit wide (d,l,ps) registers. |
|
| 4332 |
* |
|
| 4333 |
* Multiple 64 bit wide registers can be checked by calling |
|
| 4334 |
* CHECK_FR(ctx, freg1 | freg2 | ... | fregN); |
|
| 4335 |
* |
|
| 4336 |
* FIXME: This is broken for R2, it needs to be checked at runtime, not |
|
| 4337 |
* at translation time. |
|
| 4338 |
*/ |
|
| 4339 |
#define CHECK_FR(ctx, freg) do { \
|
|
| 4340 |
if (!((ctx)->CP0_Status & (1 << CP0St_FR)) && ((freg) & 1)) { \
|
|
| 4341 |
MIPS_INVAL("FPU mode"); \
|
|
| 4342 |
generate_exception (ctx, EXCP_RI); \ |
|
| 4343 |
return; \ |
|
| 4344 |
} \ |
|
| 4345 |
} while(0) |
|
| 4346 |
|
|
| 4347 | 4335 |
#define FOP(func, fmt) (((fmt) << 21) | (func)) |
| 4348 | 4336 |
|
| 4349 | 4337 |
static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) |
| ... | ... | |
| 4388 | 4376 |
opn = "dmtc1"; |
| 4389 | 4377 |
break; |
| 4390 | 4378 |
case OPC_MFHC1: |
| 4391 |
CHECK_FR(ctx, fs);
|
|
| 4379 |
gen_op_cp1_registers(fs);
|
|
| 4392 | 4380 |
GEN_LOAD_FREG_FTN(WTH0, fs); |
| 4393 | 4381 |
gen_op_mfhc1(); |
| 4394 | 4382 |
GEN_STORE_TN_REG(rt, T0); |
| 4395 | 4383 |
opn = "mfhc1"; |
| 4396 | 4384 |
break; |
| 4397 | 4385 |
case OPC_MTHC1: |
| 4398 |
CHECK_FR(ctx, fs);
|
|
| 4386 |
gen_op_cp1_registers(fs);
|
|
| 4399 | 4387 |
GEN_LOAD_REG_TN(T0, rt); |
| 4400 | 4388 |
gen_op_mthc1(); |
| 4401 | 4389 |
GEN_STORE_FTN_FREG(fs, WTH0); |
| ... | ... | |
| 4546 | 4534 |
opn = "neg.s"; |
| 4547 | 4535 |
break; |
| 4548 | 4536 |
case FOP(8, 16): |
| 4549 |
CHECK_FR(ctx, fs);
|
|
| 4537 |
gen_op_cp1_registers(fs);
|
|
| 4550 | 4538 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 4551 | 4539 |
gen_op_float_roundl_s(); |
| 4552 | 4540 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4553 | 4541 |
opn = "round.l.s"; |
| 4554 | 4542 |
break; |
| 4555 | 4543 |
case FOP(9, 16): |
| 4556 |
CHECK_FR(ctx, fs);
|
|
| 4544 |
gen_op_cp1_registers(fs);
|
|
| 4557 | 4545 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 4558 | 4546 |
gen_op_float_truncl_s(); |
| 4559 | 4547 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4560 | 4548 |
opn = "trunc.l.s"; |
| 4561 | 4549 |
break; |
| 4562 | 4550 |
case FOP(10, 16): |
| 4563 |
CHECK_FR(ctx, fs);
|
|
| 4551 |
gen_op_cp1_registers(fs);
|
|
| 4564 | 4552 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 4565 | 4553 |
gen_op_float_ceill_s(); |
| 4566 | 4554 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4567 | 4555 |
opn = "ceil.l.s"; |
| 4568 | 4556 |
break; |
| 4569 | 4557 |
case FOP(11, 16): |
| 4570 |
CHECK_FR(ctx, fs);
|
|
| 4558 |
gen_op_cp1_registers(fs);
|
|
| 4571 | 4559 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 4572 | 4560 |
gen_op_float_floorl_s(); |
| 4573 | 4561 |
GEN_STORE_FTN_FREG(fd, DT2); |
| ... | ... | |
| 4622 | 4610 |
opn = "movn.s"; |
| 4623 | 4611 |
break; |
| 4624 | 4612 |
case FOP(33, 16): |
| 4625 |
CHECK_FR(ctx, fd);
|
|
| 4613 |
gen_op_cp1_registers(fd);
|
|
| 4626 | 4614 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 4627 | 4615 |
gen_op_float_cvtd_s(); |
| 4628 | 4616 |
GEN_STORE_FTN_FREG(fd, DT2); |
| ... | ... | |
| 4635 | 4623 |
opn = "cvt.w.s"; |
| 4636 | 4624 |
break; |
| 4637 | 4625 |
case FOP(37, 16): |
| 4638 |
CHECK_FR(ctx, fs | fd);
|
|
| 4626 |
gen_op_cp1_registers(fs | fd);
|
|
| 4639 | 4627 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 4640 | 4628 |
gen_op_float_cvtl_s(); |
| 4641 | 4629 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4642 | 4630 |
opn = "cvt.l.s"; |
| 4643 | 4631 |
break; |
| 4644 | 4632 |
case FOP(38, 16): |
| 4645 |
CHECK_FR(ctx, fs | ft | fd);
|
|
| 4633 |
gen_op_cp1_registers(fs | ft | fd);
|
|
| 4646 | 4634 |
GEN_LOAD_FREG_FTN(WT1, fs); |
| 4647 | 4635 |
GEN_LOAD_FREG_FTN(WT0, ft); |
| 4648 | 4636 |
gen_op_float_cvtps_s(); |
| ... | ... | |
| 4676 | 4664 |
} |
| 4677 | 4665 |
break; |
| 4678 | 4666 |
case FOP(0, 17): |
| 4679 |
CHECK_FR(ctx, fs | ft | fd);
|
|
| 4667 |
gen_op_cp1_registers(fs | ft | fd);
|
|
| 4680 | 4668 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4681 | 4669 |
GEN_LOAD_FREG_FTN(DT1, ft); |
| 4682 | 4670 |
gen_op_float_add_d(); |
| ... | ... | |
| 4685 | 4673 |
optype = BINOP; |
| 4686 | 4674 |
break; |
| 4687 | 4675 |
case FOP(1, 17): |
| 4688 |
CHECK_FR(ctx, fs | ft | fd);
|
|
| 4676 |
gen_op_cp1_registers(fs | ft | fd);
|
|
| 4689 | 4677 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4690 | 4678 |
GEN_LOAD_FREG_FTN(DT1, ft); |
| 4691 | 4679 |
gen_op_float_sub_d(); |
| ... | ... | |
| 4694 | 4682 |
optype = BINOP; |
| 4695 | 4683 |
break; |
| 4696 | 4684 |
case FOP(2, 17): |
| 4697 |
CHECK_FR(ctx, fs | ft | fd);
|
|
| 4685 |
gen_op_cp1_registers(fs | ft | fd);
|
|
| 4698 | 4686 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4699 | 4687 |
GEN_LOAD_FREG_FTN(DT1, ft); |
| 4700 | 4688 |
gen_op_float_mul_d(); |
| ... | ... | |
| 4703 | 4691 |
optype = BINOP; |
| 4704 | 4692 |
break; |
| 4705 | 4693 |
case FOP(3, 17): |
| 4706 |
CHECK_FR(ctx, fs | ft | fd);
|
|
| 4694 |
gen_op_cp1_registers(fs | ft | fd);
|
|
| 4707 | 4695 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4708 | 4696 |
GEN_LOAD_FREG_FTN(DT1, ft); |
| 4709 | 4697 |
gen_op_float_div_d(); |
| ... | ... | |
| 4712 | 4700 |
optype = BINOP; |
| 4713 | 4701 |
break; |
| 4714 | 4702 |
case FOP(4, 17): |
| 4715 |
CHECK_FR(ctx, fs | fd);
|
|
| 4703 |
gen_op_cp1_registers(fs | fd);
|
|
| 4716 | 4704 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4717 | 4705 |
gen_op_float_sqrt_d(); |
| 4718 | 4706 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4719 | 4707 |
opn = "sqrt.d"; |
| 4720 | 4708 |
break; |
| 4721 | 4709 |
case FOP(5, 17): |
| 4722 |
CHECK_FR(ctx, fs | fd);
|
|
| 4710 |
gen_op_cp1_registers(fs | fd);
|
|
| 4723 | 4711 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4724 | 4712 |
gen_op_float_abs_d(); |
| 4725 | 4713 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4726 | 4714 |
opn = "abs.d"; |
| 4727 | 4715 |
break; |
| 4728 | 4716 |
case FOP(6, 17): |
| 4729 |
CHECK_FR(ctx, fs | fd);
|
|
| 4717 |
gen_op_cp1_registers(fs | fd);
|
|
| 4730 | 4718 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4731 | 4719 |
gen_op_float_mov_d(); |
| 4732 | 4720 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4733 | 4721 |
opn = "mov.d"; |
| 4734 | 4722 |
break; |
| 4735 | 4723 |
case FOP(7, 17): |
| 4736 |
CHECK_FR(ctx, fs | fd);
|
|
| 4724 |
gen_op_cp1_registers(fs | fd);
|
|
| 4737 | 4725 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4738 | 4726 |
gen_op_float_chs_d(); |
| 4739 | 4727 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4740 | 4728 |
opn = "neg.d"; |
| 4741 | 4729 |
break; |
| 4742 | 4730 |
case FOP(8, 17): |
| 4743 |
CHECK_FR(ctx, fs);
|
|
| 4731 |
gen_op_cp1_registers(fs);
|
|
| 4744 | 4732 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4745 | 4733 |
gen_op_float_roundl_d(); |
| 4746 | 4734 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4747 | 4735 |
opn = "round.l.d"; |
| 4748 | 4736 |
break; |
| 4749 | 4737 |
case FOP(9, 17): |
| 4750 |
CHECK_FR(ctx, fs);
|
|
| 4738 |
gen_op_cp1_registers(fs);
|
|
| 4751 | 4739 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4752 | 4740 |
gen_op_float_truncl_d(); |
| 4753 | 4741 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4754 | 4742 |
opn = "trunc.l.d"; |
| 4755 | 4743 |
break; |
| 4756 | 4744 |
case FOP(10, 17): |
| 4757 |
CHECK_FR(ctx, fs);
|
|
| 4745 |
gen_op_cp1_registers(fs);
|
|
| 4758 | 4746 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4759 | 4747 |
gen_op_float_ceill_d(); |
| 4760 | 4748 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4761 | 4749 |
opn = "ceil.l.d"; |
| 4762 | 4750 |
break; |
| 4763 | 4751 |
case FOP(11, 17): |
| 4764 |
CHECK_FR(ctx, fs);
|
|
| 4752 |
gen_op_cp1_registers(fs);
|
|
| 4765 | 4753 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4766 | 4754 |
gen_op_float_floorl_d(); |
| 4767 | 4755 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4768 | 4756 |
opn = "floor.l.d"; |
| 4769 | 4757 |
break; |
| 4770 | 4758 |
case FOP(12, 17): |
| 4771 |
CHECK_FR(ctx, fs);
|
|
| 4759 |
gen_op_cp1_registers(fs);
|
|
| 4772 | 4760 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4773 | 4761 |
gen_op_float_roundw_d(); |
| 4774 | 4762 |
GEN_STORE_FTN_FREG(fd, WT2); |
| 4775 | 4763 |
opn = "round.w.d"; |
| 4776 | 4764 |
break; |
| 4777 | 4765 |
case FOP(13, 17): |
| 4778 |
CHECK_FR(ctx, fs);
|
|
| 4766 |
gen_op_cp1_registers(fs);
|
|
| 4779 | 4767 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4780 | 4768 |
gen_op_float_truncw_d(); |
| 4781 | 4769 |
GEN_STORE_FTN_FREG(fd, WT2); |
| 4782 | 4770 |
opn = "trunc.w.d"; |
| 4783 | 4771 |
break; |
| 4784 | 4772 |
case FOP(14, 17): |
| 4785 |
CHECK_FR(ctx, fs);
|
|
| 4773 |
gen_op_cp1_registers(fs);
|
|
| 4786 | 4774 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4787 | 4775 |
gen_op_float_ceilw_d(); |
| 4788 | 4776 |
GEN_STORE_FTN_FREG(fd, WT2); |
| 4789 | 4777 |
opn = "ceil.w.d"; |
| 4790 | 4778 |
break; |
| 4791 | 4779 |
case FOP(15, 17): |
| 4792 |
CHECK_FR(ctx, fs);
|
|
| 4780 |
gen_op_cp1_registers(fs);
|
|
| 4793 | 4781 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4794 | 4782 |
gen_op_float_floorw_d(); |
| 4795 | 4783 |
GEN_STORE_FTN_FREG(fd, WT2); |
| ... | ... | |
| 4835 | 4823 |
case FOP(61, 17): |
| 4836 | 4824 |
case FOP(62, 17): |
| 4837 | 4825 |
case FOP(63, 17): |
| 4838 |
CHECK_FR(ctx, fs | ft);
|
|
| 4826 |
gen_op_cp1_registers(fs | ft);
|
|
| 4839 | 4827 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4840 | 4828 |
GEN_LOAD_FREG_FTN(DT1, ft); |
| 4841 | 4829 |
if (ctx->opcode & (1 << 6)) {
|
| ... | ... | |
| 4847 | 4835 |
} |
| 4848 | 4836 |
break; |
| 4849 | 4837 |
case FOP(32, 17): |
| 4850 |
CHECK_FR(ctx, fs);
|
|
| 4838 |
gen_op_cp1_registers(fs);
|
|
| 4851 | 4839 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4852 | 4840 |
gen_op_float_cvts_d(); |
| 4853 | 4841 |
GEN_STORE_FTN_FREG(fd, WT2); |
| 4854 | 4842 |
opn = "cvt.s.d"; |
| 4855 | 4843 |
break; |
| 4856 | 4844 |
case FOP(36, 17): |
| 4857 |
CHECK_FR(ctx, fs);
|
|
| 4845 |
gen_op_cp1_registers(fs);
|
|
| 4858 | 4846 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4859 | 4847 |
gen_op_float_cvtw_d(); |
| 4860 | 4848 |
GEN_STORE_FTN_FREG(fd, WT2); |
| 4861 | 4849 |
opn = "cvt.w.d"; |
| 4862 | 4850 |
break; |
| 4863 | 4851 |
case FOP(37, 17): |
| 4864 |
CHECK_FR(ctx, fs | fd);
|
|
| 4852 |
gen_op_cp1_registers(fs | fd);
|
|
| 4865 | 4853 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4866 | 4854 |
gen_op_float_cvtl_d(); |
| 4867 | 4855 |
GEN_STORE_FTN_FREG(fd, DT2); |
| ... | ... | |
| 4874 | 4862 |
opn = "cvt.s.w"; |
| 4875 | 4863 |
break; |
| 4876 | 4864 |
case FOP(33, 20): |
| 4877 |
CHECK_FR(ctx, fd);
|
|
| 4865 |
gen_op_cp1_registers(fd);
|
|
| 4878 | 4866 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 4879 | 4867 |
gen_op_float_cvtd_w(); |
| 4880 | 4868 |
GEN_STORE_FTN_FREG(fd, DT2); |
| 4881 | 4869 |
opn = "cvt.d.w"; |
| 4882 | 4870 |
break; |
| 4883 | 4871 |
case FOP(32, 21): |
| 4884 |
CHECK_FR(ctx, fs);
|
|
| 4872 |
gen_op_cp1_registers(fs);
|
|
| 4885 | 4873 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4886 | 4874 |
gen_op_float_cvts_l(); |
| 4887 | 4875 |
GEN_STORE_FTN_FREG(fd, WT2); |
| 4888 | 4876 |
opn = "cvt.s.l"; |
| 4889 | 4877 |
break; |
| 4890 | 4878 |
case FOP(33, 21): |
| 4891 |
CHECK_FR(ctx, fs | fd);
|
|
| 4879 |
gen_op_cp1_registers(fs | fd);
|
|
| 4892 | 4880 |
GEN_LOAD_FREG_FTN(DT0, fs); |
| 4893 | 4881 |
gen_op_float_cvtd_l(); |
| 4894 | 4882 |
GEN_STORE_FTN_FREG(fd, DT2); |
| ... | ... | |
| 4896 | 4884 |
break; |
| 4897 | 4885 |
case FOP(38, 20): |
| 4898 | 4886 |
case FOP(38, 21): |
| 4899 |
CHECK_FR(ctx, fs | fd);
|
|
| 4887 |
gen_op_cp1_registers(fs | fd);
|
|
| 4900 | 4888 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 4901 | 4889 |
GEN_LOAD_FREG_FTN(WTH0, fs); |
| 4902 | 4890 |
gen_op_float_cvtps_pw(); |
| ... | ... | |
| 4905 | 4893 |
opn = "cvt.ps.pw"; |
| 4906 | 4894 |
break; |
| 4907 | 4895 |
case FOP(0, 22): |
| 4908 |
CHECK_FR(ctx, fs | ft | fd);
|
|
| 4896 |
gen_op_cp1_registers(fs | ft | fd);
|
|
| 4909 | 4897 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 4910 | 4898 |
GEN_LOAD_FREG_FTN(WTH0, fs); |
| 4911 | 4899 |
GEN_LOAD_FREG_FTN(WT1, ft); |
| ... | ... | |
| 4916 | 4904 |
opn = "add.ps"; |
| 4917 | 4905 |
break; |
| 4918 | 4906 |
case FOP(1, 22): |
| 4919 |
CHECK_FR(ctx, fs | ft | fd);
|
|
| 4907 |
gen_op_cp1_registers(fs | ft | fd);
|
|
| 4920 | 4908 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 4921 | 4909 |
GEN_LOAD_FREG_FTN(WTH0, fs); |
| 4922 | 4910 |
GEN_LOAD_FREG_FTN(WT1, ft); |
| ... | ... | |
| 4927 | 4915 |
opn = "sub.ps"; |
| 4928 | 4916 |
break; |
| 4929 | 4917 |
case FOP(2, 22): |
| 4930 |
CHECK_FR(ctx, fs | ft | fd);
|
|
| 4918 |
gen_op_cp1_registers(fs | ft | fd);
|
|
| 4931 | 4919 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 4932 | 4920 |
GEN_LOAD_FREG_FTN(WTH0, fs); |
| 4933 | 4921 |
GEN_LOAD_FREG_FTN(WT1, ft); |
| ... | ... | |
| 4938 | 4926 |
opn = "mul.ps"; |
| 4939 | 4927 |
break; |
| 4940 | 4928 |
case FOP(5, 22): |
| 4941 |
CHECK_FR(ctx, fs | fd);
|
|
| 4929 |
gen_op_cp1_registers(fs | fd);
|
|
| 4942 | 4930 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 4943 | 4931 |
GEN_LOAD_FREG_FTN(WTH0, fs); |
| 4944 | 4932 |
gen_op_float_abs_ps(); |
| ... | ... | |
| 4947 | 4935 |
opn = "abs.ps"; |
| 4948 | 4936 |
break; |
| 4949 | 4937 |
case FOP(6, 22): |
| 4950 |
CHECK_FR(ctx, fs | fd);
|
|
| 4938 |
gen_op_cp1_registers(fs | fd);
|
|
| 4951 | 4939 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 4952 | 4940 |
GEN_LOAD_FREG_FTN(WTH0, fs); |
| 4953 | 4941 |
gen_op_float_mov_ps(); |
| ... | ... | |
| 4956 | 4944 |
opn = "mov.ps"; |
| 4957 | 4945 |
break; |
| 4958 | 4946 |
case FOP(7, 22): |
| 4959 |
CHECK_FR(ctx, fs | fd);
|
|
| 4947 |
gen_op_cp1_registers(fs | fd);
|
|
| 4960 | 4948 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 4961 | 4949 |
GEN_LOAD_FREG_FTN(WTH0, fs); |
| 4962 | 4950 |
gen_op_float_chs_ps(); |
| ... | ... | |
| 4998 | 4986 |
opn = "movn.ps"; |
| 4999 | 4987 |
break; |
| 5000 | 4988 |
case FOP(24, 22): |
| 5001 |
CHECK_FR(ctx, fs | fd | ft);
|
|
| 4989 |
gen_op_cp1_registers(fs | fd | ft);
|
|
| 5002 | 4990 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 5003 | 4991 |
GEN_LOAD_FREG_FTN(WTH0, fs); |
| 5004 | 4992 |
GEN_LOAD_FREG_FTN(WT1, ft); |
| ... | ... | |
| 5009 | 4997 |
opn = "addr.ps"; |
| 5010 | 4998 |
break; |
| 5011 | 4999 |
case FOP(32, 22): |
| 5012 |
CHECK_FR(ctx, fs);
|
|
| 5000 |
gen_op_cp1_registers(fs);
|
|
| 5013 | 5001 |
GEN_LOAD_FREG_FTN(WTH0, fs); |
| 5014 | 5002 |
gen_op_float_cvts_pu(); |
| 5015 | 5003 |
GEN_STORE_FTN_FREG(fd, WT2); |
| 5016 | 5004 |
opn = "cvt.s.pu"; |
| 5017 | 5005 |
break; |
| 5018 | 5006 |
case FOP(36, 22): |
| 5019 |
CHECK_FR(ctx, fs | fd);
|
|
| 5007 |
gen_op_cp1_registers(fs | fd);
|
|
| 5020 | 5008 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 5021 | 5009 |
GEN_LOAD_FREG_FTN(WTH0, fs); |
| 5022 | 5010 |
gen_op_float_cvtpw_ps(); |
| ... | ... | |
| 5025 | 5013 |
opn = "cvt.pw.ps"; |
| 5026 | 5014 |
break; |
| 5027 | 5015 |
case FOP(40, 22): |
| 5028 |
CHECK_FR(ctx, fs);
|
|
| 5016 |
gen_op_cp1_registers(fs);
|
|
| 5029 | 5017 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 5030 | 5018 |
gen_op_float_cvts_pl(); |
| 5031 | 5019 |
GEN_STORE_FTN_FREG(fd, WT2); |
| 5032 | 5020 |
opn = "cvt.s.pl"; |
| 5033 | 5021 |
break; |
| 5034 | 5022 |
case FOP(44, 22): |
| 5035 |
CHECK_FR(ctx, fs | ft | fd);
|
|
| 5023 |
gen_op_cp1_registers(fs | ft | fd);
|
|
| 5036 | 5024 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 5037 | 5025 |
GEN_LOAD_FREG_FTN(WT1, ft); |
| 5038 | 5026 |
gen_op_float_pll_ps(); |
| ... | ... | |
| 5040 | 5028 |
opn = "pll.ps"; |
| 5041 | 5029 |
break; |
| 5042 | 5030 |
case FOP(45, 22): |
| 5043 |
CHECK_FR(ctx, fs | ft | fd);
|
|
| 5031 |
gen_op_cp1_registers(fs | ft | fd);
|
|
| 5044 | 5032 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 5045 | 5033 |
GEN_LOAD_FREG_FTN(WTH1, ft); |
| 5046 | 5034 |
gen_op_float_plu_ps(); |
| ... | ... | |
| 5048 | 5036 |
opn = "plu.ps"; |
| 5049 | 5037 |
break; |
| 5050 | 5038 |
case FOP(46, 22): |
| 5051 |
CHECK_FR(ctx, fs | ft | fd);
|
|
| 5039 |
gen_op_cp1_registers(fs | ft | fd);
|
|
| 5052 | 5040 |
GEN_LOAD_FREG_FTN(WTH0, fs); |
| 5053 | 5041 |
GEN_LOAD_FREG_FTN(WT1, ft); |
| 5054 | 5042 |
gen_op_float_pul_ps(); |
| ... | ... | |
| 5056 | 5044 |
opn = "pul.ps"; |
| 5057 | 5045 |
break; |
| 5058 | 5046 |
case FOP(47, 22): |
| 5059 |
CHECK_FR(ctx, fs | ft | fd);
|
|
| 5047 |
gen_op_cp1_registers(fs | ft | fd);
|
|
| 5060 | 5048 |
GEN_LOAD_FREG_FTN(WTH0, fs); |
| 5061 | 5049 |
GEN_LOAD_FREG_FTN(WTH1, ft); |
| 5062 | 5050 |
gen_op_float_puu_ps(); |
| ... | ... | |
| 5079 | 5067 |
case FOP(61, 22): |
| 5080 | 5068 |
case FOP(62, 22): |
| 5081 | 5069 |
case FOP(63, 22): |
| 5082 |
CHECK_FR(ctx, fs | ft);
|
|
| 5070 |
gen_op_cp1_registers(fs | ft);
|
|
| 5083 | 5071 |
GEN_LOAD_FREG_FTN(WT0, fs); |
| 5084 | 5072 |
GEN_LOAD_FREG_FTN(WTH0, fs); |
| 5085 | 5073 |
GEN_LOAD_FREG_FTN(WT1, ft); |
| ... | ... | |
| 5166 | 5154 |
const char *opn = "flt3_arith"; |
| 5167 | 5155 |
|
| 5168 | 5156 |
/* All of those work only on 64bit FPUs. */ |
| 5169 |
CHECK_FR(ctx, fd | fr | fs | ft);
|
|
| 5157 |
gen_op_cp1_registers(fd | fr | fs | ft);
|
|
| 5170 | 5158 |
switch (opc) {
|
| 5171 | 5159 |
case OPC_ALNV_PS: |
| 5172 | 5160 |
GEN_LOAD_REG_TN(T0, fr); |
| ... | ... | |
| 5874 | 5862 |
ctx.bstate = BS_NONE; |
| 5875 | 5863 |
/* Restore delay slot state from the tb context. */ |
| 5876 | 5864 |
ctx.hflags = tb->flags; |
| 5877 |
ctx.saved_hflags = ctx.hflags; |
|
| 5878 |
switch (ctx.hflags & MIPS_HFLAG_BMASK) {
|
|
| 5879 |
case MIPS_HFLAG_BR: |
|
| 5880 |
gen_op_restore_breg_target(); |
|
| 5881 |
break; |
|
| 5882 |
case MIPS_HFLAG_B: |
|
| 5883 |
ctx.btarget = env->btarget; |
|
| 5884 |
break; |
|
| 5885 |
case MIPS_HFLAG_BC: |
|
| 5886 |
case MIPS_HFLAG_BL: |
|
| 5887 |
ctx.btarget = env->btarget; |
|
| 5888 |
gen_op_restore_bcond(); |
|
| 5889 |
break; |
|
| 5890 |
} |
|
| 5865 |
restore_cpu_state(env, &ctx); |
|
| 5891 | 5866 |
#if defined(CONFIG_USER_ONLY) |
| 5892 | 5867 |
ctx.mem_idx = 0; |
| 5893 | 5868 |
#else |
| 5894 | 5869 |
ctx.mem_idx = !((ctx.hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM); |
| 5895 | 5870 |
#endif |
| 5896 |
ctx.CP0_Status = env->CP0_Status; |
|
| 5897 | 5871 |
#ifdef DEBUG_DISAS |
| 5898 | 5872 |
if (loglevel & CPU_LOG_TB_CPU) {
|
| 5899 | 5873 |
fprintf(logfile, "------------------------------------------------\n"); |
Also available in: Unified diff