Revision fd6dc90b hw/etraxfs_pic.c
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* THE SOFTWARE. |
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*/ |
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#include <stdio.h>
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#include "sysbus.h"
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#include "hw.h" |
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#include "pc.h" |
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#include "etraxfs.h" |
| ... | ... | |
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#define R_R_GURU 4 |
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#define R_MAX 5 |
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struct fs_pic_state
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struct etrax_pic
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{
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CPUState *env; |
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SysBusDevice busdev; |
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uint32_t *interrupt_vector; |
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qemu_irq parent_irq; |
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qemu_irq parent_nmi; |
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uint32_t regs[R_MAX]; |
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}; |
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static void pic_update(struct fs_pic_state *fs)
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static void pic_update(struct etrax_pic *fs)
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{
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CPUState *env = fs->env; |
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uint32_t vector = 0; |
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int i; |
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|
| ... | ... | |
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} |
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mv >>= 1; |
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} |
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if (vector) {
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env->interrupt_vector = vector; |
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D(printf("%s vector=%x\n", __func__, vector));
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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} else {
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env->interrupt_vector = 0; |
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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D(printf("%s reset irqs\n", __func__));
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} |
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if (fs->interrupt_vector) {
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*fs->interrupt_vector = vector; |
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} |
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qemu_set_irq(fs->parent_irq, !!vector); |
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} |
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static uint32_t pic_readl (void *opaque, target_phys_addr_t addr) |
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{
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struct fs_pic_state *fs = opaque;
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struct etrax_pic *fs = opaque;
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uint32_t rval; |
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rval = fs->regs[addr >> 2]; |
| ... | ... | |
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static void |
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pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
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{
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struct fs_pic_state *fs = opaque;
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struct etrax_pic *fs = opaque;
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D(printf("%s addr=%x val=%x\n", __func__, addr, value));
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if (addr == R_RW_MASK) {
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| ... | ... | |
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&pic_writel, |
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}; |
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void pic_info(Monitor *mon) |
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{
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} |
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void irq_info(Monitor *mon) |
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{
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} |
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static void nmi_handler(void *opaque, int irq, int level) |
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{
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struct fs_pic_state *fs = (void *)opaque; |
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CPUState *env = fs->env; |
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struct etrax_pic *fs = (void *)opaque; |
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uint32_t mask; |
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mask = 1 << irq; |
| ... | ... | |
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else |
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fs->regs[R_R_NMI] &= ~mask; |
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if (fs->regs[R_R_NMI]) |
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cpu_interrupt(env, CPU_INTERRUPT_NMI); |
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else |
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cpu_reset_interrupt(env, CPU_INTERRUPT_NMI); |
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qemu_set_irq(fs->parent_nmi, !!fs->regs[R_R_NMI]); |
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} |
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static void irq_handler(void *opaque, int irq, int level) |
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{
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struct fs_pic_state *fs = (void *)opaque;
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struct etrax_pic *fs = (void *)opaque;
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if (irq >= 30) |
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return nmi_handler(opaque, irq, level); |
| ... | ... | |
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pic_update(fs); |
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} |
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qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
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static void etraxfs_pic_init(SysBusDevice *dev)
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{
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struct fs_pic_state *fs = NULL; |
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qemu_irq *irq; |
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struct etrax_pic *s = FROM_SYSBUS(typeof (*s), dev); |
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int intr_vect_regs; |
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fs = qemu_mallocz(sizeof *fs); |
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fs->env = env; |
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irq = qemu_allocate_irqs(irq_handler, fs, 32); |
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s->interrupt_vector = qdev_get_prop_ptr(&dev->qdev, "interrupt_vector"); |
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qdev_init_irq_sink(&dev->qdev, irq_handler, 32); |
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sysbus_init_irq(dev, &s->parent_irq); |
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sysbus_init_irq(dev, &s->parent_nmi); |
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intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs); |
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cpu_register_physical_memory(base, R_MAX * 4, intr_vect_regs); |
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return irq; |
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intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, s); |
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sysbus_init_mmio(dev, R_MAX * 4, intr_vect_regs); |
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} |
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static void etraxfs_pic_register(void) |
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{
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sysbus_register_dev("etraxfs,pic", sizeof (struct etrax_pic),
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etraxfs_pic_init); |
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} |
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device_init(etraxfs_pic_register) |
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