root / tcg / hppa / tcg-target.h @ fd76e73a
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1 | f54b3f92 | aurel32 | /*
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2 | f54b3f92 | aurel32 | * Tiny Code Generator for QEMU
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3 | f54b3f92 | aurel32 | *
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4 | f54b3f92 | aurel32 | * Copyright (c) 2008 Fabrice Bellard
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5 | f54b3f92 | aurel32 | *
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6 | f54b3f92 | aurel32 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | f54b3f92 | aurel32 | * of this software and associated documentation files (the "Software"), to deal
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8 | f54b3f92 | aurel32 | * in the Software without restriction, including without limitation the rights
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9 | f54b3f92 | aurel32 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | f54b3f92 | aurel32 | * copies of the Software, and to permit persons to whom the Software is
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11 | f54b3f92 | aurel32 | * furnished to do so, subject to the following conditions:
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12 | f54b3f92 | aurel32 | *
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13 | f54b3f92 | aurel32 | * The above copyright notice and this permission notice shall be included in
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14 | f54b3f92 | aurel32 | * all copies or substantial portions of the Software.
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15 | f54b3f92 | aurel32 | *
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16 | f54b3f92 | aurel32 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | f54b3f92 | aurel32 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | f54b3f92 | aurel32 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | f54b3f92 | aurel32 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | f54b3f92 | aurel32 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | f54b3f92 | aurel32 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | f54b3f92 | aurel32 | * THE SOFTWARE.
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23 | f54b3f92 | aurel32 | */
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24 | f54b3f92 | aurel32 | |
25 | f54b3f92 | aurel32 | #define TCG_TARGET_HPPA 1 |
26 | f54b3f92 | aurel32 | |
27 | f54b3f92 | aurel32 | #if defined(_PA_RISC1_1)
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28 | f54b3f92 | aurel32 | #define TCG_TARGET_REG_BITS 32 |
29 | f54b3f92 | aurel32 | #else
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30 | f54b3f92 | aurel32 | #error unsupported
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31 | f54b3f92 | aurel32 | #endif
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32 | f54b3f92 | aurel32 | |
33 | f54b3f92 | aurel32 | #define TCG_TARGET_WORDS_BIGENDIAN
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34 | f54b3f92 | aurel32 | |
35 | f54b3f92 | aurel32 | #define TCG_TARGET_NB_REGS 32 |
36 | f54b3f92 | aurel32 | |
37 | f54b3f92 | aurel32 | enum {
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38 | f54b3f92 | aurel32 | TCG_REG_R0 = 0,
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39 | f54b3f92 | aurel32 | TCG_REG_R1, |
40 | f54b3f92 | aurel32 | TCG_REG_RP, |
41 | f54b3f92 | aurel32 | TCG_REG_R3, |
42 | f54b3f92 | aurel32 | TCG_REG_R4, |
43 | f54b3f92 | aurel32 | TCG_REG_R5, |
44 | f54b3f92 | aurel32 | TCG_REG_R6, |
45 | f54b3f92 | aurel32 | TCG_REG_R7, |
46 | f54b3f92 | aurel32 | TCG_REG_R8, |
47 | f54b3f92 | aurel32 | TCG_REG_R9, |
48 | f54b3f92 | aurel32 | TCG_REG_R10, |
49 | f54b3f92 | aurel32 | TCG_REG_R11, |
50 | f54b3f92 | aurel32 | TCG_REG_R12, |
51 | f54b3f92 | aurel32 | TCG_REG_R13, |
52 | f54b3f92 | aurel32 | TCG_REG_R14, |
53 | f54b3f92 | aurel32 | TCG_REG_R15, |
54 | f54b3f92 | aurel32 | TCG_REG_R16, |
55 | f54b3f92 | aurel32 | TCG_REG_R17, |
56 | f54b3f92 | aurel32 | TCG_REG_R18, |
57 | f54b3f92 | aurel32 | TCG_REG_R19, |
58 | f54b3f92 | aurel32 | TCG_REG_R20, |
59 | f54b3f92 | aurel32 | TCG_REG_R21, |
60 | f54b3f92 | aurel32 | TCG_REG_R22, |
61 | f54b3f92 | aurel32 | TCG_REG_R23, |
62 | f54b3f92 | aurel32 | TCG_REG_R24, |
63 | f54b3f92 | aurel32 | TCG_REG_R25, |
64 | f54b3f92 | aurel32 | TCG_REG_R26, |
65 | f54b3f92 | aurel32 | TCG_REG_DP, |
66 | f54b3f92 | aurel32 | TCG_REG_RET0, |
67 | f54b3f92 | aurel32 | TCG_REG_RET1, |
68 | f54b3f92 | aurel32 | TCG_REG_SP, |
69 | f54b3f92 | aurel32 | TCG_REG_R31, |
70 | f54b3f92 | aurel32 | }; |
71 | f54b3f92 | aurel32 | |
72 | fd76e73a | Richard Henderson | #define TCG_CT_CONST_0 0x0100 |
73 | fd76e73a | Richard Henderson | #define TCG_CT_CONST_S5 0x0200 |
74 | fd76e73a | Richard Henderson | #define TCG_CT_CONST_S11 0x0400 |
75 | fd76e73a | Richard Henderson | |
76 | f54b3f92 | aurel32 | /* used for function call generation */
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77 | f54b3f92 | aurel32 | #define TCG_REG_CALL_STACK TCG_REG_SP
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78 | fd76e73a | Richard Henderson | #define TCG_TARGET_STACK_ALIGN 64 |
79 | fd76e73a | Richard Henderson | #define TCG_TARGET_CALL_STACK_OFFSET -48 |
80 | fd76e73a | Richard Henderson | #define TCG_TARGET_STATIC_CALL_ARGS_SIZE 8*4 |
81 | fd76e73a | Richard Henderson | #define TCG_TARGET_CALL_ALIGN_ARGS 1 |
82 | f54b3f92 | aurel32 | #define TCG_TARGET_STACK_GROWSUP
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83 | f54b3f92 | aurel32 | |
84 | f54b3f92 | aurel32 | /* optional instructions */
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85 | fd76e73a | Richard Henderson | // #define TCG_TARGET_HAS_div_i32
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86 | fd76e73a | Richard Henderson | #define TCG_TARGET_HAS_rot_i32
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87 | fd76e73a | Richard Henderson | #define TCG_TARGET_HAS_ext8s_i32
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88 | fd76e73a | Richard Henderson | #define TCG_TARGET_HAS_ext16s_i32
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89 | fd76e73a | Richard Henderson | #define TCG_TARGET_HAS_ext8u_i32
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90 | fd76e73a | Richard Henderson | #define TCG_TARGET_HAS_ext16u_i32
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91 | fd76e73a | Richard Henderson | #define TCG_TARGET_HAS_bswap16_i32
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92 | fd76e73a | Richard Henderson | #define TCG_TARGET_HAS_bswap32_i32
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93 | fd76e73a | Richard Henderson | #define TCG_TARGET_HAS_not_i32
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94 | fd76e73a | Richard Henderson | #define TCG_TARGET_HAS_neg_i32
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95 | fd76e73a | Richard Henderson | #define TCG_TARGET_HAS_andc_i32
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96 | fd76e73a | Richard Henderson | // #define TCG_TARGET_HAS_orc_i32
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97 | fd76e73a | Richard Henderson | |
98 | fd76e73a | Richard Henderson | #define TCG_TARGET_HAS_GUEST_BASE
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99 | f54b3f92 | aurel32 | |
100 | f54b3f92 | aurel32 | /* Note: must be synced with dyngen-exec.h */
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101 | f54b3f92 | aurel32 | #define TCG_AREG0 TCG_REG_R17
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102 | f54b3f92 | aurel32 | |
103 | f54b3f92 | aurel32 | static inline void flush_icache_range(unsigned long start, unsigned long stop) |
104 | f54b3f92 | aurel32 | { |
105 | f54b3f92 | aurel32 | start &= ~31;
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106 | fd76e73a | Richard Henderson | while (start <= stop) {
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107 | fd76e73a | Richard Henderson | asm volatile ("fdc 0(%0)\n\t" |
108 | fd76e73a | Richard Henderson | "sync\n\t"
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109 | fd76e73a | Richard Henderson | "fic 0(%%sr4, %0)\n\t"
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110 | fd76e73a | Richard Henderson | "sync"
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111 | f54b3f92 | aurel32 | : : "r"(start) : "memory"); |
112 | f54b3f92 | aurel32 | start += 32;
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113 | f54b3f92 | aurel32 | } |
114 | f54b3f92 | aurel32 | } |