Revision fd76e73a tcg/hppa/tcg-target.h

b/tcg/hppa/tcg-target.h
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    TCG_REG_R31,
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};
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#define TCG_CT_CONST_0    0x0100
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#define TCG_CT_CONST_S5   0x0200
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#define TCG_CT_CONST_S11  0x0400
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_SP
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#define TCG_TARGET_STACK_ALIGN 16
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#define TCG_TARGET_STACK_ALIGN 64
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#define TCG_TARGET_CALL_STACK_OFFSET -48
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#define TCG_TARGET_STATIC_CALL_ARGS_SIZE 8*4
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#define TCG_TARGET_CALL_ALIGN_ARGS 1
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#define TCG_TARGET_STACK_GROWSUP
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/* optional instructions */
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#define TCG_TARGET_HAS_div2_i32
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//#define TCG_TARGET_HAS_ext8s_i32
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//#define TCG_TARGET_HAS_ext16s_i32
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//#define TCG_TARGET_HAS_bswap16_i32
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//#define TCG_TARGET_HAS_bswap32_i32
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// #define TCG_TARGET_HAS_div_i32
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#define TCG_TARGET_HAS_rot_i32
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#define TCG_TARGET_HAS_ext8s_i32
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#define TCG_TARGET_HAS_ext16s_i32
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#define TCG_TARGET_HAS_ext8u_i32
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#define TCG_TARGET_HAS_ext16u_i32
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#define TCG_TARGET_HAS_bswap16_i32
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#define TCG_TARGET_HAS_bswap32_i32
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#define TCG_TARGET_HAS_not_i32
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#define TCG_TARGET_HAS_neg_i32
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#define TCG_TARGET_HAS_andc_i32
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// #define TCG_TARGET_HAS_orc_i32
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#define TCG_TARGET_HAS_GUEST_BASE
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/* Note: must be synced with dyngen-exec.h */
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#define TCG_AREG0 TCG_REG_R17
......
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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    start &= ~31;
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    while (start <= stop)
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    {
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        asm volatile ("fdc 0(%0)\n"
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                      "sync\n"
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                      "fic 0(%%sr4, %0)\n"
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                      "sync\n"
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    while (start <= stop) {
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        asm volatile ("fdc 0(%0)\n\t"
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                      "sync\n\t"
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                      "fic 0(%%sr4, %0)\n\t"
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                      "sync"
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                      : : "r"(start) : "memory");
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        start += 32;
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    }
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}
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/* supplied by libgcc */
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extern void *__canonicalize_funcptr_for_compare(void *);
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/* Field selection types defined by hppa */
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#define rnd(x)                  (((x)+0x1000)&~0x1fff)
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/* lsel: select left 21 bits */
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#define lsel(v,a)               (((v)+(a))>>11)
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/* rsel: select right 11 bits */
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#define rsel(v,a)               (((v)+(a))&0x7ff)
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/* lrsel with rounding of addend to nearest 8k */
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#define lrsel(v,a)              (((v)+rnd(a))>>11)
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/* rrsel with rounding of addend to nearest 8k */
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#define rrsel(v,a)              ((((v)+rnd(a))&0x7ff)+((a)-rnd(a)))
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#define mask(x,sz)              ((x) & ~((1<<(sz))-1))
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static inline int reassemble_12(int as12)
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{
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    return (((as12 & 0x800) >> 11) |
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            ((as12 & 0x400) >> 8) |
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            ((as12 & 0x3ff) << 3));
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}
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static inline int reassemble_14(int as14)
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{
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    return (((as14 & 0x1fff) << 1) |
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            ((as14 & 0x2000) >> 13));
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}
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static inline int reassemble_17(int as17)
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{
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    return (((as17 & 0x10000) >> 16) |
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            ((as17 & 0x0f800) << 5) |
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            ((as17 & 0x00400) >> 8) |
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            ((as17 & 0x003ff) << 3));
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}
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static inline int reassemble_21(int as21)
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{
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    return (((as21 & 0x100000) >> 20) |
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            ((as21 & 0x0ffe00) >> 8) |
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            ((as21 & 0x000180) << 7) |
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            ((as21 & 0x00007c) << 14) |
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            ((as21 & 0x000003) << 12));
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}
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static inline void hppa_patch21l(uint32_t *insn, int val, int addend)
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{
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    val = lrsel(val, addend);
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    *insn = mask(*insn, 21) | reassemble_21(val);
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}
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static inline void hppa_patch14r(uint32_t *insn, int val, int addend)
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{
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    val = rrsel(val, addend);
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    *insn = mask(*insn, 14) | reassemble_14(val);
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}
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static inline void hppa_patch17r(uint32_t *insn, int val, int addend)
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{
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    val = rrsel(val, addend);
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    *insn = (*insn & ~0x1f1ffd) | reassemble_17(val);
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}
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static inline void hppa_patch21l_dprel(uint32_t *insn, int val, int addend)
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{
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    register unsigned int dp asm("r27");
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    hppa_patch21l(insn, val - dp, addend);
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}
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static inline void hppa_patch14r_dprel(uint32_t *insn, int val, int addend)
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{
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    register unsigned int dp asm("r27");
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    hppa_patch14r(insn, val - dp, addend);
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}
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static inline void hppa_patch17f(uint32_t *insn, int val, int addend)
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{
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    int dot = (int)insn & ~0x3;
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    int v = ((val + addend) - dot - 8) / 4;
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    if (v > (1 << 16) || v < -(1 << 16)) {
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        printf("cannot fit branch to offset %d [%08x->%08x]\n", v, dot, val);
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        abort();
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    }
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    *insn = (*insn & ~0x1f1ffd) | reassemble_17(v);
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}
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static inline void hppa_load_imm21l(uint32_t *insn, int val, int addend)
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{
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    /* Transform addil L'sym(%dp) to ldil L'val, %r1 */
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    *insn = 0x20200000 | reassemble_21(lrsel(val, 0));
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}
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static inline void hppa_load_imm14r(uint32_t *insn, int val, int addend)
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{
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    /* Transform ldw R'sym(%r1), %rN to ldo R'sym(%r1), %rN */
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    hppa_patch14r(insn, val, addend);
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    /* HACK */
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    if (addend == 0)
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        *insn = (*insn & ~0xfc000000) | (0x0d << 26);
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}

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