Archipelago » qemu

/*

 *  PowerPC emulation helpers for qemu.

 *

 *  Copyright (c) 2003-2007 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, see <http://www.gnu.org/licenses/>.

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include <signal.h>

#include "cpu.h"

#include "exec-all.h"

#include "helper_regs.h"

#include "qemu-common.h"

#include "kvm.h"

//#define DEBUG_MMU

//#define DEBUG_BATS

//#define DEBUG_SLB

//#define DEBUG_SOFTWARE_TLB

//#define DUMP_PAGE_TABLES

//#define DEBUG_EXCEPTIONS

//#define FLUSH_ALL_TLBS

#ifdef DEBUG_MMU

#  define LOG_MMU(...) qemu_log(__VA_ARGS__)

#  define LOG_MMU_STATE(env) log_cpu_state((env), 0)

#else

#  define LOG_MMU(...) do { } while (0)

#  define LOG_MMU_STATE(...) do { } while (0)

#endif

#ifdef DEBUG_SOFTWARE_TLB

#  define LOG_SWTLB(...) qemu_log(__VA_ARGS__)

#else

#  define LOG_SWTLB(...) do { } while (0)

#endif

#ifdef DEBUG_BATS

#  define LOG_BATS(...) qemu_log(__VA_ARGS__)

#else

#  define LOG_BATS(...) do { } while (0)

#endif

#ifdef DEBUG_SLB

#  define LOG_SLB(...) qemu_log(__VA_ARGS__)

#else

#  define LOG_SLB(...) do { } while (0)

#endif

#ifdef DEBUG_EXCEPTIONS

#  define LOG_EXCP(...) qemu_log(__VA_ARGS__)

#else

#  define LOG_EXCP(...) do { } while (0)

#endif

/*****************************************************************************/

/* PowerPC Hypercall emulation */

void (*cpu_ppc_hypercall)(CPUState *);

/*****************************************************************************/

/* PowerPC MMU emulation */

#if defined(CONFIG_USER_ONLY)

int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,

                              int mmu_idx, int is_softmmu)

{

    int exception, error_code;

    if (rw == 2) {

        exception = POWERPC_EXCP_ISI;

        error_code = 0x40000000;

    } else {

        exception = POWERPC_EXCP_DSI;

        error_code = 0x40000000;

        if (rw)

            error_code |= 0x02000000;

        env->spr[SPR_DAR] = address;

        env->spr[SPR_DSISR] = error_code;

    }

    env->exception_index = exception;

    env->error_code = error_code;

    return 1;

}

#else

/* Common routines used by software and hardware TLBs emulation */

static inline int pte_is_valid(target_ulong pte0)

{

    return pte0 & 0x80000000 ? 1 : 0;

}

static inline void pte_invalidate(target_ulong *pte0)

{

    *pte0 &= ~0x80000000;

}

#if defined(TARGET_PPC64)

static inline int pte64_is_valid(target_ulong pte0)

{

    return pte0 & 0x0000000000000001ULL ? 1 : 0;

}

static inline void pte64_invalidate(target_ulong *pte0)

{

    *pte0 &= ~0x0000000000000001ULL;

}

#endif

#define PTE_PTEM_MASK 0x7FFFFFBF

#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)

#if defined(TARGET_PPC64)

#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL

#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)

#endif

static inline int pp_check(int key, int pp, int nx)

{

    int access;

    /* Compute access rights */

    /* When pp is 3/7, the result is undefined. Set it to noaccess */

    access = 0;

    if (key == 0) {

        switch (pp) {

        case 0x0:

        case 0x1:

        case 0x2:

            access |= PAGE_WRITE;

            /* No break here */

        case 0x3:

        case 0x6:

            access |= PAGE_READ;

            break;

        }

    } else {

        switch (pp) {

        case 0x0:

        case 0x6:

            access = 0;

            break;

        case 0x1:

        case 0x3:

            access = PAGE_READ;

            break;

        case 0x2:

            access = PAGE_READ | PAGE_WRITE;

            break;

        }

    }

    if (nx == 0)

        access |= PAGE_EXEC;

    return access;

}

static inline int check_prot(int prot, int rw, int access_type)

{

    int ret;

    if (access_type == ACCESS_CODE) {

        if (prot & PAGE_EXEC)

            ret = 0;

        else

            ret = -2;

    } else if (rw) {

        if (prot & PAGE_WRITE)

            ret = 0;

        else

            ret = -2;

    } else {

        if (prot & PAGE_READ)

            ret = 0;

        else

            ret = -2;

    }

    return ret;

}

static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0,

                             target_ulong pte1, int h, int rw, int type)

{

    target_ulong ptem, mmask;

    int access, ret, pteh, ptev, pp;

    ret = -1;

    /* Check validity and table match */

#if defined(TARGET_PPC64)

    if (is_64b) {

        ptev = pte64_is_valid(pte0);

        pteh = (pte0 >> 1) & 1;

    } else

#endif

    {

        ptev = pte_is_valid(pte0);

        pteh = (pte0 >> 6) & 1;

    }

    if (ptev && h == pteh) {

        /* Check vsid & api */

#if defined(TARGET_PPC64)

        if (is_64b) {

            ptem = pte0 & PTE64_PTEM_MASK;

            mmask = PTE64_CHECK_MASK;

            pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004);

            ctx->nx  = (pte1 >> 2) & 1; /* No execute bit */

            ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit    */

        } else

#endif

        {

            ptem = pte0 & PTE_PTEM_MASK;

            mmask = PTE_CHECK_MASK;

            pp = pte1 & 0x00000003;

        }

        if (ptem == ctx->ptem) {

            if (ctx->raddr != (target_phys_addr_t)-1ULL) {

                /* all matches should have equal RPN, WIMG & PP */

                if ((ctx->raddr & mmask) != (pte1 & mmask)) {

                    qemu_log("Bad RPN/WIMG/PP\n");

                    return -3;

                }

            }

            /* Compute access rights */

            access = pp_check(ctx->key, pp, ctx->nx);

            /* Keep the matching PTE informations */

            ctx->raddr = pte1;

            ctx->prot = access;

            ret = check_prot(ctx->prot, rw, type);

            if (ret == 0) {

                /* Access granted */

                LOG_MMU("PTE access granted !\n");

            } else {

                /* Access right violation */

                LOG_MMU("PTE access rejected\n");

            }

        }

    }

    return ret;

}

static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0,

                              target_ulong pte1, int h, int rw, int type)

{

    return _pte_check(ctx, 0, pte0, pte1, h, rw, type);

}

#if defined(TARGET_PPC64)

static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0,

                              target_ulong pte1, int h, int rw, int type)

{

    return _pte_check(ctx, 1, pte0, pte1, h, rw, type);

}

#endif

static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,

                                   int ret, int rw)

{

    int store = 0;

    /* Update page flags */

    if (!(*pte1p & 0x00000100)) {

        /* Update accessed flag */

        *pte1p |= 0x00000100;

        store = 1;

    }

    if (!(*pte1p & 0x00000080)) {

        if (rw == 1 && ret == 0) {

            /* Update changed flag */

            *pte1p |= 0x00000080;

            store = 1;

        } else {

            /* Force page fault for first write access */

            ctx->prot &= ~PAGE_WRITE;

        }

    }

    return store;

}

/* Software driven TLB helpers */

static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way,

                                    int is_code)

{

    int nr;

    /* Select TLB num in a way from address */

    nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);

    /* Select TLB way */

    nr += env->tlb_per_way * way;

    /* 6xx have separate TLBs for instructions and data */

    if (is_code && env->id_tlbs == 1)

        nr += env->nb_tlb;

    return nr;

}

static inline void ppc6xx_tlb_invalidate_all(CPUState *env)

{

    ppc6xx_tlb_t *tlb;

    int nr, max;

    //LOG_SWTLB("Invalidate all TLBs\n");

    /* Invalidate all defined software TLB */

    max = env->nb_tlb;

    if (env->id_tlbs == 1)

        max *= 2;

    for (nr = 0; nr < max; nr++) {

        tlb = &env->tlb[nr].tlb6;

        pte_invalidate(&tlb->pte0);

    }

    tlb_flush(env, 1);

}

static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env,

                                                target_ulong eaddr,

                                                int is_code, int match_epn)

{

#if !defined(FLUSH_ALL_TLBS)

    ppc6xx_tlb_t *tlb;

    int way, nr;

    /* Invalidate ITLB + DTLB, all ways */

    for (way = 0; way < env->nb_ways; way++) {

        nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);

        tlb = &env->tlb[nr].tlb6;

        if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {

            LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,

                      env->nb_tlb, eaddr);

            pte_invalidate(&tlb->pte0);

            tlb_flush_page(env, tlb->EPN);

        }

    }

#else

    /* XXX: PowerPC specification say this is valid as well */

    ppc6xx_tlb_invalidate_all(env);

#endif

}

static inline void ppc6xx_tlb_invalidate_virt(CPUState *env,

                                              target_ulong eaddr, int is_code)

{

    __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);

}

void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,

                       target_ulong pte0, target_ulong pte1)

{

    ppc6xx_tlb_t *tlb;

    int nr;

    nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);

    tlb = &env->tlb[nr].tlb6;

    LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx

              " PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1);

    /* Invalidate any pending reference in Qemu for this virtual address */

    __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);

    tlb->pte0 = pte0;

    tlb->pte1 = pte1;

    tlb->EPN = EPN;

    /* Store last way for LRU mechanism */

    env->last_way = way;

}

static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx,

                                   target_ulong eaddr, int rw, int access_type)

{

    ppc6xx_tlb_t *tlb;

    int nr, best, way;

    int ret;

    best = -1;

    ret = -1; /* No TLB found */

    for (way = 0; way < env->nb_ways; way++) {

        nr = ppc6xx_tlb_getnum(env, eaddr, way,

                               access_type == ACCESS_CODE ? 1 : 0);

        tlb = &env->tlb[nr].tlb6;

        /* This test "emulates" the PTE index match for hardware TLBs */

        if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {

            LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx

                      "] <> " TARGET_FMT_lx "\n", nr, env->nb_tlb,

                      pte_is_valid(tlb->pte0) ? "valid" : "inval",

                      tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);

            continue;

        }

        LOG_SWTLB("TLB %d/%d %s " TARGET_FMT_lx " <> " TARGET_FMT_lx " "

                  TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb,

                  pte_is_valid(tlb->pte0) ? "valid" : "inval",

                  tlb->EPN, eaddr, tlb->pte1,

                  rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');

        switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {

        case -3:

            /* TLB inconsistency */

            return -1;

        case -2:

            /* Access violation */

            ret = -2;

            best = nr;

            break;

        case -1:

        default:

            /* No match */

            break;

        case 0:

            /* access granted */

            /* XXX: we should go on looping to check all TLBs consistency

             *      but we can speed-up the whole thing as the

             *      result would be undefined if TLBs are not consistent.

             */

            ret = 0;

            best = nr;

            goto done;

        }

    }

    if (best != -1) {

    done:

        LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n",

                  ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);

        /* Update page flags */

        pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);

    }

    return ret;

}

/* Perform BAT hit & translation */

static inline void bat_size_prot(CPUState *env, target_ulong *blp, int *validp,

                                 int *protp, target_ulong *BATu,

                                 target_ulong *BATl)

{

    target_ulong bl;

    int pp, valid, prot;

    bl = (*BATu & 0x00001FFC) << 15;

    valid = 0;

    prot = 0;

    if (((msr_pr == 0) && (*BATu & 0x00000002)) ||

        ((msr_pr != 0) && (*BATu & 0x00000001))) {

        valid = 1;

        pp = *BATl & 0x00000003;

        if (pp != 0) {

            prot = PAGE_READ | PAGE_EXEC;

            if (pp == 0x2)

                prot |= PAGE_WRITE;

        }

    }

    *blp = bl;

    *validp = valid;

    *protp = prot;

}

static inline void bat_601_size_prot(CPUState *env, target_ulong *blp,

                                     int *validp, int *protp,

                                     target_ulong *BATu, target_ulong *BATl)

{

    target_ulong bl;

    int key, pp, valid, prot;

    bl = (*BATl & 0x0000003F) << 17;

    LOG_BATS("b %02x ==> bl " TARGET_FMT_lx " msk " TARGET_FMT_lx "\n",

             (uint8_t)(*BATl & 0x0000003F), bl, ~bl);

    prot = 0;

    valid = (*BATl >> 6) & 1;

    if (valid) {

        pp = *BATu & 0x00000003;

        if (msr_pr == 0)

            key = (*BATu >> 3) & 1;

        else

            key = (*BATu >> 2) & 1;

        prot = pp_check(key, pp, 0);

    }

    *blp = bl;

    *validp = valid;

    *protp = prot;

}

static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,

                          int rw, int type)

{

    target_ulong *BATlt, *BATut, *BATu, *BATl;

    target_ulong BEPIl, BEPIu, bl;

    int i, valid, prot;

    int ret = -1;

    LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,

             type == ACCESS_CODE ? 'I' : 'D', virtual);

    switch (type) {

    case ACCESS_CODE:

        BATlt = env->IBAT[1];

        BATut = env->IBAT[0];

        break;

    default:

        BATlt = env->DBAT[1];

        BATut = env->DBAT[0];

        break;

    }

    for (i = 0; i < env->nb_BATs; i++) {

        BATu = &BATut[i];

        BATl = &BATlt[i];

        BEPIu = *BATu & 0xF0000000;

        BEPIl = *BATu & 0x0FFE0000;

        if (unlikely(env->mmu_model == POWERPC_MMU_601)) {

            bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl);

        } else {

            bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);

        }

        LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx

                 " BATl " TARGET_FMT_lx "\n", __func__,

                 type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);

        if ((virtual & 0xF0000000) == BEPIu &&

            ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {

            /* BAT matches */

            if (valid != 0) {

                /* Get physical address */

                ctx->raddr = (*BATl & 0xF0000000) |

                    ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |

                    (virtual & 0x0001F000);

                /* Compute access rights */

                ctx->prot = prot;

                ret = check_prot(ctx->prot, rw, type);

                if (ret == 0)

                    LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n",

                             i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',

                             ctx->prot & PAGE_WRITE ? 'W' : '-');

                break;

            }

        }

    }

    if (ret < 0) {

#if defined(DEBUG_BATS)

        if (qemu_log_enabled()) {

            LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", virtual);

            for (i = 0; i < 4; i++) {

                BATu = &BATut[i];

                BATl = &BATlt[i];

                BEPIu = *BATu & 0xF0000000;

                BEPIl = *BATu & 0x0FFE0000;

                bl = (*BATu & 0x00001FFC) << 15;

                LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx

                         " BATl " TARGET_FMT_lx " \n\t" TARGET_FMT_lx " "

                         TARGET_FMT_lx " " TARGET_FMT_lx "\n",

                         __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,

                         *BATu, *BATl, BEPIu, BEPIl, bl);

            }

        }

#endif

    }

    /* No hit */

    return ret;

}

static inline target_phys_addr_t get_pteg_offset(CPUState *env,

                                                 target_phys_addr_t hash,

                                                 int pte_size)

{

    return (hash * pte_size * 8) & env->htab_mask;

}

/* PTE table lookup */

static inline int _find_pte(CPUState *env, mmu_ctx_t *ctx, int is_64b, int h,

                            int rw, int type, int target_page_bits)

{

    target_phys_addr_t pteg_off;

    target_ulong pte0, pte1;

    int i, good = -1;

    int ret, r;

    ret = -1; /* No entry found */

    pteg_off = get_pteg_offset(env, ctx->hash[h],

                               is_64b ? HASH_PTE_SIZE_64 : HASH_PTE_SIZE_32);

    for (i = 0; i < 8; i++) {

#if defined(TARGET_PPC64)

        if (is_64b) {

            pte0 = ldq_phys(env->htab_base + pteg_off + (i * 16));

            pte1 = ldq_phys(env->htab_base + pteg_off + (i * 16) + 8);

            /* We have a TLB that saves 4K pages, so let's

             * split a huge page to 4k chunks */

            if (target_page_bits != TARGET_PAGE_BITS)

                pte1 |= (ctx->eaddr & (( 1 << target_page_bits ) - 1))

                        & TARGET_PAGE_MASK;

            r = pte64_check(ctx, pte0, pte1, h, rw, type);

            LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "

                    TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",

                    pteg_base + (i * 16), pte0, pte1, (int)(pte0 & 1), h,

                    (int)((pte0 >> 1) & 1), ctx->ptem);

        } else

#endif

        {

            pte0 = ldl_phys(env->htab_base + pteg_off + (i * 8));

            pte1 =  ldl_phys(env->htab_base + pteg_off + (i * 8) + 4);

            r = pte32_check(ctx, pte0, pte1, h, rw, type);

            LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "

                    TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",

                    pteg_base + (i * 8), pte0, pte1, (int)(pte0 >> 31), h,

                    (int)((pte0 >> 6) & 1), ctx->ptem);

        }

        switch (r) {

        case -3:

            /* PTE inconsistency */

            return -1;

        case -2:

            /* Access violation */

            ret = -2;

            good = i;

            break;

        case -1:

        default:

            /* No PTE match */

            break;

        case 0:

            /* access granted */

            /* XXX: we should go on looping to check all PTEs consistency

             *      but if we can speed-up the whole thing as the

             *      result would be undefined if PTEs are not consistent.

             */

            ret = 0;

            good = i;

            goto done;

        }

    }

    if (good != -1) {

    done:

        LOG_MMU("found PTE at addr " TARGET_FMT_lx " prot=%01x ret=%d\n",

                ctx->raddr, ctx->prot, ret);

        /* Update page flags */

        pte1 = ctx->raddr;

        if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {

#if defined(TARGET_PPC64)

            if (is_64b) {

                stq_phys_notdirty(env->htab_base + pteg_off + (good * 16) + 8,

                                  pte1);

            } else

#endif

            {

                stl_phys_notdirty(env->htab_base + pteg_off + (good * 8) + 4,

                                  pte1);

            }

        }

    }

    return ret;

}

static inline int find_pte32(CPUState *env, mmu_ctx_t *ctx, int h, int rw,

                             int type, int target_page_bits)

{

    return _find_pte(env, ctx, 0, h, rw, type, target_page_bits);

}

#if defined(TARGET_PPC64)

static inline int find_pte64(CPUState *env, mmu_ctx_t *ctx, int h, int rw,

                             int type, int target_page_bits)

{

    return _find_pte(env, ctx, 1, h, rw, type, target_page_bits);

}

#endif

static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw,

                           int type, int target_page_bits)

{

#if defined(TARGET_PPC64)

    if (env->mmu_model & POWERPC_MMU_64)

        return find_pte64(env, ctx, h, rw, type, target_page_bits);

#endif

    return find_pte32(env, ctx, h, rw, type, target_page_bits);

}

#if defined(TARGET_PPC64)

static inline ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)

{

    uint64_t esid;

    int n;

    LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);

    esid = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;

    for (n = 0; n < env->slb_nr; n++) {

        ppc_slb_t *slb = &env->slb[n];

        LOG_SLB("%s: slot %d %016" PRIx64 " %016"

                    PRIx64 "\n", __func__, n, slb->esid, slb->vsid);

        if (slb->esid == esid) {

            return slb;

        }

    }

    return NULL;

}

void ppc_slb_invalidate_all (CPUPPCState *env)

{

    int n, do_invalidate;

    do_invalidate = 0;

    /* XXX: Warning: slbia never invalidates the first segment */

    for (n = 1; n < env->slb_nr; n++) {

        ppc_slb_t *slb = &env->slb[n];

        if (slb->esid & SLB_ESID_V) {

            slb->esid &= ~SLB_ESID_V;

            /* XXX: given the fact that segment size is 256 MB or 1TB,

             *      and we still don't have a tlb_flush_mask(env, n, mask)

             *      in Qemu, we just invalidate all TLBs

             */

            do_invalidate = 1;

        }

    }

    if (do_invalidate)

        tlb_flush(env, 1);

}

void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)

{

    ppc_slb_t *slb;

    slb = slb_lookup(env, T0);

    if (!slb) {

        return;

    }

    if (slb->esid & SLB_ESID_V) {

        slb->esid &= ~SLB_ESID_V;

        /* XXX: given the fact that segment size is 256 MB or 1TB,

         *      and we still don't have a tlb_flush_mask(env, n, mask)

         *      in Qemu, we just invalidate all TLBs

         */

        tlb_flush(env, 1);

    }

}

int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs)

{

    int slot = rb & 0xfff;

    uint64_t esid = rb & ~0xfff;

    ppc_slb_t *slb = &env->slb[slot];

    if (slot >= env->slb_nr) {

        return -1;

    }

    slb->esid = esid;

    slb->vsid = rs;

    LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64

            " %016" PRIx64 "\n", __func__, slot, rb, rs,

            slb->esid, slb->vsid);

    return 0;

}

int ppc_load_slb_esid (CPUPPCState *env, target_ulong rb, target_ulong *rt)

{

    int slot = rb & 0xfff;

    ppc_slb_t *slb = &env->slb[slot];

    if (slot >= env->slb_nr) {

        return -1;

    }

    *rt = slb->esid;

    return 0;

}

int ppc_load_slb_vsid (CPUPPCState *env, target_ulong rb, target_ulong *rt)

{

    int slot = rb & 0xfff;

    ppc_slb_t *slb = &env->slb[slot];

    if (slot >= env->slb_nr) {

        return -1;

    }

    *rt = slb->vsid;

    return 0;

}

#endif /* defined(TARGET_PPC64) */

/* Perform segment based translation */

static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,

                              target_ulong eaddr, int rw, int type)

{

    target_phys_addr_t hash;

    target_ulong sr, vsid, pgidx, page_mask;

    int ds, pr, target_page_bits;

    int ret, ret2;

    pr = msr_pr;

#if defined(TARGET_PPC64)

    if (env->mmu_model & POWERPC_MMU_64) {

        ppc_slb_t *slb;

        LOG_MMU("Check SLBs\n");

        slb = slb_lookup(env, eaddr);

        if (!slb) {

            return -5;

        }

        vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;

        page_mask = ~SEGMENT_MASK_256M;

        target_page_bits = (slb->vsid & SLB_VSID_L)

            ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;

        ctx->key = !!(pr ? (slb->vsid & SLB_VSID_KP)

                      : (slb->vsid & SLB_VSID_KS));

        ds = 0;

        ctx->nx = !!(slb->vsid & SLB_VSID_N);

        ctx->eaddr = eaddr;

    } else

#endif /* defined(TARGET_PPC64) */

    {

        sr = env->sr[eaddr >> 28];

        page_mask = 0x0FFFFFFF;

        ctx->key = (((sr & 0x20000000) && (pr != 0)) ||

                    ((sr & 0x40000000) && (pr == 0))) ? 1 : 0;

        ds = sr & 0x80000000 ? 1 : 0;

        ctx->nx = sr & 0x10000000 ? 1 : 0;

        vsid = sr & 0x00FFFFFF;

        target_page_bits = TARGET_PAGE_BITS;

        LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="

                TARGET_FMT_lx " lr=" TARGET_FMT_lx

                " ir=%d dr=%d pr=%d %d t=%d\n",

                eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,

                (int)msr_dr, pr != 0 ? 1 : 0, rw, type);

    }

    LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",

            ctx->key, ds, ctx->nx, vsid);

    ret = -1;

    if (!ds) {

        /* Check if instruction fetch is allowed, if needed */

        if (type != ACCESS_CODE || ctx->nx == 0) {

            /* Page address translation */

            pgidx = (eaddr & page_mask) >> target_page_bits;

#if defined(TARGET_PPC64)

            if (env->mmu_model & POWERPC_MMU_64) {

                /* XXX: this is false for 1 TB segments */

                hash = vsid ^ pgidx;

            } else