Revision fdabc366 target-ppc/cpu.h

b/target-ppc/cpu.h
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#define TARGET_HAS_ICE 1


  		





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/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC


  		





  
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 *                              have different cache line sizes


  		





  
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 */


  		





  
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#define ICACHE_LINE_SIZE 32


  		





  
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#define DCACHE_LINE_SIZE 32


  		





  
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/* XXX: put this in a common place */


  		





  
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#define likely(x)   __builtin_expect(!!(x), 1)


  		





  
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/*****************************************************************************/


  		





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/* PVR definitions for most known PowerPC */


  		





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enum {


  		












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