Revision fdf9b3e8 cpu-exec.c
b/cpu-exec.c | ||
---|---|---|
190 | 190 |
flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); |
191 | 191 |
cs_base = 0; |
192 | 192 |
pc = env->PC; |
193 |
#elif defined(TARGET_SH4) |
|
194 |
flags = env->sr & (SR_MD | SR_RB); |
|
195 |
cs_base = 0; /* XXXXX */ |
|
196 |
pc = env->pc; |
|
193 | 197 |
#else |
194 | 198 |
#error unsupported CPU |
195 | 199 |
#endif |
... | ... | |
363 | 367 |
#endif |
364 | 368 |
#elif defined(TARGET_PPC) |
365 | 369 |
#elif defined(TARGET_MIPS) |
370 |
#elif defined(TARGET_SH4) |
|
371 |
/* XXXXX */ |
|
366 | 372 |
#else |
367 | 373 |
#error unsupported target CPU |
368 | 374 |
#endif |
... | ... | |
407 | 413 |
do_interrupt(env->exception_index); |
408 | 414 |
#elif defined(TARGET_ARM) |
409 | 415 |
do_interrupt(env); |
416 |
#elif defined(TARGET_SH4) |
|
417 |
do_interrupt(env); |
|
410 | 418 |
#endif |
411 | 419 |
} |
412 | 420 |
env->exception_index = -1; |
... | ... | |
550 | 558 |
env->exception_index = EXCP_IRQ; |
551 | 559 |
do_interrupt(env); |
552 | 560 |
} |
561 |
#elif defined(TARGET_SH4) |
|
562 |
/* XXXXX */ |
|
553 | 563 |
#endif |
554 | 564 |
if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { |
555 | 565 |
env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
... | ... | |
608 | 618 |
cpu_dump_state(env, logfile, fprintf, 0); |
609 | 619 |
#elif defined(TARGET_MIPS) |
610 | 620 |
cpu_dump_state(env, logfile, fprintf, 0); |
621 |
#elif defined(TARGET_SH4) |
|
622 |
cpu_dump_state(env, logfile, fprintf, 0); |
|
611 | 623 |
#else |
612 | 624 |
#error unsupported target CPU |
613 | 625 |
#endif |
... | ... | |
817 | 829 |
#endif |
818 | 830 |
#elif defined(TARGET_PPC) |
819 | 831 |
#elif defined(TARGET_MIPS) |
832 |
#elif defined(TARGET_SH4) |
|
833 |
/* XXXXX */ |
|
820 | 834 |
#else |
821 | 835 |
#error unsupported target CPU |
822 | 836 |
#endif |
... | ... | |
1121 | 1135 |
return 1; |
1122 | 1136 |
} |
1123 | 1137 |
|
1138 |
#elif defined (TARGET_SH4) |
|
1139 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
|
1140 |
int is_write, sigset_t *old_set, |
|
1141 |
void *puc) |
|
1142 |
{ |
|
1143 |
TranslationBlock *tb; |
|
1144 |
int ret; |
|
1145 |
|
|
1146 |
if (cpu_single_env) |
|
1147 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */ |
|
1148 |
#if defined(DEBUG_SIGNAL) |
|
1149 |
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", |
|
1150 |
pc, address, is_write, *(unsigned long *)old_set); |
|
1151 |
#endif |
|
1152 |
/* XXX: locking issue */ |
|
1153 |
if (is_write && page_unprotect(h2g(address), pc, puc)) { |
|
1154 |
return 1; |
|
1155 |
} |
|
1156 |
|
|
1157 |
/* see if it is an MMU fault */ |
|
1158 |
ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0); |
|
1159 |
if (ret < 0) |
|
1160 |
return 0; /* not an MMU fault */ |
|
1161 |
if (ret == 0) |
|
1162 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
|
1163 |
|
|
1164 |
/* now we have a real cpu fault */ |
|
1165 |
tb = tb_find_pc(pc); |
|
1166 |
if (tb) { |
|
1167 |
/* the PC is inside the translated code. It means that we have |
|
1168 |
a virtual CPU fault */ |
|
1169 |
cpu_restore_state(tb, env, pc, puc); |
|
1170 |
} |
|
1171 |
if (ret == 1) { |
|
1172 |
#if 0 |
|
1173 |
printf("PF exception: NIP=0x%08x error=0x%x %p\n", |
|
1174 |
env->nip, env->error_code, tb); |
|
1175 |
#endif |
|
1176 |
/* we restore the process signal mask as the sigreturn should |
|
1177 |
do it (XXX: use sigsetjmp) */ |
|
1178 |
sigprocmask(SIG_SETMASK, old_set, NULL); |
|
1179 |
// do_raise_exception_err(env->exception_index, env->error_code); |
|
1180 |
} else { |
|
1181 |
/* activate soft MMU for this block */ |
|
1182 |
cpu_resume_from_signal(env, puc); |
|
1183 |
} |
|
1184 |
/* never comes here */ |
|
1185 |
return 1; |
|
1186 |
} |
|
1124 | 1187 |
#else |
1125 | 1188 |
#error unsupported target CPU |
1126 | 1189 |
#endif |
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