Revision fe1479c3 target-arm/translate.c
| b/target-arm/translate.c | ||
|---|---|---|
| 5536 | 5536 |
return 0; |
| 5537 | 5537 |
} |
| 5538 | 5538 |
|
| 5539 |
static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn) |
|
| 5540 |
{
|
|
| 5541 |
int crn = (insn >> 16) & 0xf; |
|
| 5542 |
int crm = insn & 0xf; |
|
| 5543 |
int op1 = (insn >> 21) & 7; |
|
| 5544 |
int op2 = (insn >> 5) & 7; |
|
| 5545 |
int rt = (insn >> 12) & 0xf; |
|
| 5546 |
TCGv tmp; |
|
| 5547 |
|
|
| 5548 |
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
|
|
| 5549 |
if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
|
|
| 5550 |
/* TEECR */ |
|
| 5551 |
if (IS_USER(s)) |
|
| 5552 |
return 1; |
|
| 5553 |
tmp = load_cpu_field(teecr); |
|
| 5554 |
store_reg(s, rt, tmp); |
|
| 5555 |
return 0; |
|
| 5556 |
} |
|
| 5557 |
if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
|
|
| 5558 |
/* TEEHBR */ |
|
| 5559 |
if (IS_USER(s) && (env->teecr & 1)) |
|
| 5560 |
return 1; |
|
| 5561 |
tmp = load_cpu_field(teehbr); |
|
| 5562 |
store_reg(s, rt, tmp); |
|
| 5563 |
return 0; |
|
| 5564 |
} |
|
| 5565 |
} |
|
| 5566 |
fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n", |
|
| 5567 |
op1, crn, crm, op2); |
|
| 5568 |
return 1; |
|
| 5569 |
} |
|
| 5570 |
|
|
| 5571 |
static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn) |
|
| 5572 |
{
|
|
| 5573 |
int crn = (insn >> 16) & 0xf; |
|
| 5574 |
int crm = insn & 0xf; |
|
| 5575 |
int op1 = (insn >> 21) & 7; |
|
| 5576 |
int op2 = (insn >> 5) & 7; |
|
| 5577 |
int rt = (insn >> 12) & 0xf; |
|
| 5578 |
TCGv tmp; |
|
| 5579 |
|
|
| 5580 |
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
|
|
| 5581 |
if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
|
|
| 5582 |
/* TEECR */ |
|
| 5583 |
if (IS_USER(s)) |
|
| 5584 |
return 1; |
|
| 5585 |
tmp = load_reg(s, rt); |
|
| 5586 |
gen_helper_set_teecr(cpu_env, tmp); |
|
| 5587 |
dead_tmp(tmp); |
|
| 5588 |
return 0; |
|
| 5589 |
} |
|
| 5590 |
if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
|
|
| 5591 |
/* TEEHBR */ |
|
| 5592 |
if (IS_USER(s) && (env->teecr & 1)) |
|
| 5593 |
return 1; |
|
| 5594 |
tmp = load_reg(s, rt); |
|
| 5595 |
store_cpu_field(tmp, teehbr); |
|
| 5596 |
return 0; |
|
| 5597 |
} |
|
| 5598 |
} |
|
| 5599 |
fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n", |
|
| 5600 |
op1, crn, crm, op2); |
|
| 5601 |
return 1; |
|
| 5602 |
} |
|
| 5603 |
|
|
| 5539 | 5604 |
static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn) |
| 5540 | 5605 |
{
|
| 5541 | 5606 |
int cpnum; |
| ... | ... | |
| 5557 | 5622 |
case 10: |
| 5558 | 5623 |
case 11: |
| 5559 | 5624 |
return disas_vfp_insn (env, s, insn); |
| 5625 |
case 14: |
|
| 5626 |
/* Coprocessors 7-15 are architecturally reserved by ARM. |
|
| 5627 |
Unfortunately Intel decided to ignore this. */ |
|
| 5628 |
if (arm_feature(env, ARM_FEATURE_XSCALE)) |
|
| 5629 |
goto board; |
|
| 5630 |
if (insn & (1 << 20)) |
|
| 5631 |
return disas_cp14_read(env, s, insn); |
|
| 5632 |
else |
|
| 5633 |
return disas_cp14_write(env, s, insn); |
|
| 5560 | 5634 |
case 15: |
| 5561 | 5635 |
return disas_cp15_insn (env, s, insn); |
| 5562 | 5636 |
default: |
| 5637 |
board: |
|
| 5563 | 5638 |
/* Unknown coprocessor. See if the board has hooked it. */ |
| 5564 | 5639 |
return disas_cp_insn (env, s, insn); |
| 5565 | 5640 |
} |
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