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/*
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 * S/390 virtual CPU header
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 *
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 *  Copyright (c) 2009 Ulrich Hecht
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#ifndef CPU_S390X_H
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#define CPU_S390X_H
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#define TARGET_LONG_BITS 64
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#define ELF_MACHINE        EM_S390
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#define CPUState struct CPUS390XState
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#include "cpu-defs.h"
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#define TARGET_PAGE_BITS 12
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#define TARGET_PHYS_ADDR_SPACE_BITS 64
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#define TARGET_VIRT_ADDR_SPACE_BITS 64
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#include "cpu-all.h"
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#include "softfloat.h"
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#define NB_MMU_MODES 3
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#define MMU_MODE0_SUFFIX _primary
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#define MMU_MODE1_SUFFIX _secondary
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#define MMU_MODE2_SUFFIX _home
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#define MMU_USER_IDX 1
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#define MAX_EXT_QUEUE 16
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typedef struct PSW {
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    uint64_t mask;
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    uint64_t addr;
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} PSW;
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typedef struct ExtQueue {
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    uint32_t code;
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    uint32_t param;
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    uint32_t param64;
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} ExtQueue;
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typedef struct CPUS390XState {
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    uint64_t regs[16];        /* GP registers */
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    uint32_t aregs[16];        /* access registers */
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    uint32_t fpc;        /* floating-point control register */
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    CPU_DoubleU fregs[16]; /* FP registers */
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    float_status fpu_status; /* passed to softfloat lib */
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    PSW psw;
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    uint32_t cc_op;
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    uint64_t cc_src;
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    uint64_t cc_dst;
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    uint64_t cc_vr;
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    uint64_t __excp_addr;
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    uint64_t psa;
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    uint32_t int_pgm_code;
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    uint32_t int_pgm_ilc;
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    uint32_t int_svc_code;
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    uint32_t int_svc_ilc;
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    uint64_t cregs[16]; /* control registers */
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    int pending_int;
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    ExtQueue ext_queue[MAX_EXT_QUEUE];
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    int ext_index;
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    CPU_COMMON
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    /* reset does memset(0) up to here */
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    int cpu_num;
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    uint8_t *storage_keys;
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    uint64_t tod_offset;
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    uint64_t tod_basetime;
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    QEMUTimer *tod_timer;
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    QEMUTimer *cpu_timer;
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} CPUS390XState;
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#if defined(CONFIG_USER_ONLY)
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static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
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{
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    if (newsp) {
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        env->regs[15] = newsp;
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    }
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    env->regs[0] = 0;
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}
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#endif
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/* Interrupt Codes */
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/* Program Interrupts */
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#define PGM_OPERATION                   0x0001
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#define PGM_PRIVILEGED                  0x0002
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#define PGM_EXECUTE                     0x0003
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#define PGM_PROTECTION                  0x0004
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#define PGM_ADDRESSING                  0x0005
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#define PGM_SPECIFICATION               0x0006
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#define PGM_DATA                        0x0007
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#define PGM_FIXPT_OVERFLOW              0x0008
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#define PGM_FIXPT_DIVIDE                0x0009
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#define PGM_DEC_OVERFLOW                0x000a
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#define PGM_DEC_DIVIDE                  0x000b
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#define PGM_HFP_EXP_OVERFLOW            0x000c
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#define PGM_HFP_EXP_UNDERFLOW           0x000d
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#define PGM_HFP_SIGNIFICANCE            0x000e
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#define PGM_HFP_DIVIDE                  0x000f
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#define PGM_SEGMENT_TRANS               0x0010
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#define PGM_PAGE_TRANS                  0x0011
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#define PGM_TRANS_SPEC                  0x0012
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#define PGM_SPECIAL_OP                  0x0013
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#define PGM_OPERAND                     0x0015
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#define PGM_TRACE_TABLE                 0x0016
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#define PGM_SPACE_SWITCH                0x001c
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#define PGM_HFP_SQRT                    0x001d
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#define PGM_PC_TRANS_SPEC               0x001f
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#define PGM_AFX_TRANS                   0x0020
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#define PGM_ASX_TRANS                   0x0021
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#define PGM_LX_TRANS                    0x0022
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#define PGM_EX_TRANS                    0x0023
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#define PGM_PRIM_AUTH                   0x0024
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#define PGM_SEC_AUTH                    0x0025
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#define PGM_ALET_SPEC                   0x0028
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#define PGM_ALEN_SPEC                   0x0029
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#define PGM_ALE_SEQ                     0x002a
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#define PGM_ASTE_VALID                  0x002b
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#define PGM_ASTE_SEQ                    0x002c
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#define PGM_EXT_AUTH                    0x002d
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#define PGM_STACK_FULL                  0x0030
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#define PGM_STACK_EMPTY                 0x0031
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#define PGM_STACK_SPEC                  0x0032
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#define PGM_STACK_TYPE                  0x0033
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#define PGM_STACK_OP                    0x0034
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#define PGM_ASCE_TYPE                   0x0038
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#define PGM_REG_FIRST_TRANS             0x0039
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#define PGM_REG_SEC_TRANS               0x003a
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#define PGM_REG_THIRD_TRANS             0x003b
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#define PGM_MONITOR                     0x0040
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#define PGM_PER                         0x0080
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#define PGM_CRYPTO                      0x0119
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/* External Interrupts */
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#define EXT_INTERRUPT_KEY               0x0040
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#define EXT_CLOCK_COMP                  0x1004
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#define EXT_CPU_TIMER                   0x1005
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#define EXT_MALFUNCTION                 0x1200
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#define EXT_EMERGENCY                   0x1201
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#define EXT_EXTERNAL_CALL               0x1202
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#define EXT_ETR                         0x1406
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#define EXT_SERVICE                     0x2401
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#define EXT_VIRTIO                      0x2603
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/* PSW defines */
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#undef PSW_MASK_PER
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#undef PSW_MASK_DAT
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#undef PSW_MASK_IO
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#undef PSW_MASK_EXT
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#undef PSW_MASK_KEY
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#undef PSW_SHIFT_KEY
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#undef PSW_MASK_MCHECK
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#undef PSW_MASK_WAIT
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#undef PSW_MASK_PSTATE
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#undef PSW_MASK_ASC
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#undef PSW_MASK_CC
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#undef PSW_MASK_PM
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#undef PSW_MASK_64
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#define PSW_MASK_PER            0x4000000000000000ULL
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#define PSW_MASK_DAT            0x0400000000000000ULL
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#define PSW_MASK_IO             0x0200000000000000ULL
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#define PSW_MASK_EXT            0x0100000000000000ULL
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#define PSW_MASK_KEY            0x00F0000000000000ULL
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#define PSW_SHIFT_KEY           56
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#define PSW_MASK_MCHECK         0x0004000000000000ULL
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#define PSW_MASK_WAIT           0x0002000000000000ULL
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#define PSW_MASK_PSTATE         0x0001000000000000ULL
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#define PSW_MASK_ASC            0x0000C00000000000ULL
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#define PSW_MASK_CC             0x0000300000000000ULL
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#define PSW_MASK_PM             0x00000F0000000000ULL
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#define PSW_MASK_64             0x0000000100000000ULL
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#define PSW_MASK_32             0x0000000080000000ULL
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#undef PSW_ASC_PRIMARY
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#undef PSW_ASC_ACCREG
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#undef PSW_ASC_SECONDARY
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#undef PSW_ASC_HOME
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#define PSW_ASC_PRIMARY         0x0000000000000000ULL
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#define PSW_ASC_ACCREG          0x0000400000000000ULL
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#define PSW_ASC_SECONDARY       0x0000800000000000ULL
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#define PSW_ASC_HOME            0x0000C00000000000ULL
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/* tb flags */
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#define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
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#define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
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#define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
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#define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
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#define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
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#define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
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#define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
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#define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
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#define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
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#define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
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#define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
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#define FLAG_MASK_64            (PSW_MASK_64     >> 32)
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#define FLAG_MASK_32            0x00001000
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static inline int cpu_mmu_index (CPUState *env)
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{
235
    if (env->psw.mask & PSW_MASK_PSTATE) {
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        return 1;
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    }
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    return 0;
240
}
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static inline void cpu_get_tb_cpu_state(CPUState* env, target_ulong *pc,
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                                        target_ulong *cs_base, int *flags)
244
{
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    *pc = env->psw.addr;
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    *cs_base = 0;
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    *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
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             ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
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}
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static inline int get_ilc(uint8_t opc)
252
{
253
    switch (opc >> 6) {
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    case 0:
255
        return 1;
256
    case 1:
257
    case 2:
258
        return 2;
259
    case 3:
260
        return 3;
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    }
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263
    return 0;
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}
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#define ILC_LATER       0x20
267
#define ILC_LATER_INC   0x21
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#define ILC_LATER_INC_2 0x22
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CPUS390XState *cpu_s390x_init(const char *cpu_model);
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void s390x_translate_init(void);
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int cpu_s390x_exec(CPUS390XState *s);
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void cpu_s390x_close(CPUS390XState *s);
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void do_interrupt (CPUState *env);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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   signal handlers to inform the virtual CPU of exceptions. non zero
279
   is returned if the signal was handled by the virtual CPU.  */
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int cpu_s390x_signal_handler(int host_signum, void *pinfo,
281
                           void *puc);
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int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
283
                              int mmu_idx, int is_softmuu);
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#define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
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#ifndef CONFIG_USER_ONLY
288
int s390_virtio_hypercall(CPUState *env, uint64_t mem, uint64_t hypercall);
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#ifdef CONFIG_KVM
291
void kvm_s390_interrupt(CPUState *env, int type, uint32_t code);
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void kvm_s390_virtio_irq(CPUState *env, int config_change, uint64_t token);
293
void kvm_s390_interrupt_internal(CPUState *env, int type, uint32_t parm,
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                                 uint64_t parm64, int vm);
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#else
296
static inline void kvm_s390_interrupt(CPUState *env, int type, uint32_t code)
297
{
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}
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static inline void kvm_s390_virtio_irq(CPUState *env, int config_change,
301
                                       uint64_t token)
302
{
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}
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static inline void kvm_s390_interrupt_internal(CPUState *env, int type,
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                                               uint32_t parm, uint64_t parm64,
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                                               int vm)
308
{
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}
310
#endif
311
CPUState *s390_cpu_addr2state(uint16_t cpu_addr);
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/* from s390-virtio-bus */
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extern const target_phys_addr_t virtio_size;
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#ifndef KVM_S390_SIGP_STOP
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#define KVM_S390_SIGP_STOP              0
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#define KVM_S390_PROGRAM_INT            0
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#define KVM_S390_SIGP_SET_PREFIX        0
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#define KVM_S390_RESTART                0
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#define KVM_S390_INT_VIRTIO             0
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#define KVM_S390_INT_SERVICE            0
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#define KVM_S390_INT_EMERGENCY          0
324
#endif
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326
#endif
327
void cpu_lock(void);
328
void cpu_unlock(void);
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static inline void cpu_set_tls(CPUS390XState *env, target_ulong newtls)
331
{
332
    env->aregs[0] = newtls >> 32;
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    env->aregs[1] = newtls & 0xffffffffULL;
334
}
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#define cpu_init cpu_s390x_init
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#define cpu_exec cpu_s390x_exec
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#define cpu_gen_code cpu_s390x_gen_code
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#define cpu_signal_handler cpu_s390x_signal_handler
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#include "exec-all.h"
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#ifdef CONFIG_USER_ONLY
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#define EXCP_OPEX 1 /* operation exception (sigill) */
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#define EXCP_SVC 2 /* supervisor call (syscall) */
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#define EXCP_ADDR 5 /* addressing exception */
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#define EXCP_SPEC 6 /* specification exception */
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#else
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#define EXCP_EXT 1 /* external interrupt */
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#define EXCP_SVC 2 /* supervisor call (syscall) */
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#define EXCP_PGM 3 /* program interruption */
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#endif /* CONFIG_USER_ONLY */
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#define INTERRUPT_EXT        (1 << 0)
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#define INTERRUPT_TOD        (1 << 1)
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#define INTERRUPT_CPUTIMER   (1 << 2)
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/* Program Status Word.  */
363
#define S390_PSWM_REGNUM 0
364
#define S390_PSWA_REGNUM 1
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/* General Purpose Registers.  */
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#define S390_R0_REGNUM 2
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#define S390_R1_REGNUM 3
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#define S390_R2_REGNUM 4
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#define S390_R3_REGNUM 5
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#define S390_R4_REGNUM 6
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#define S390_R5_REGNUM 7
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#define S390_R6_REGNUM 8
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#define S390_R7_REGNUM 9
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#define S390_R8_REGNUM 10
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#define S390_R9_REGNUM 11
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#define S390_R10_REGNUM 12
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#define S390_R11_REGNUM 13
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#define S390_R12_REGNUM 14
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#define S390_R13_REGNUM 15
380
#define S390_R14_REGNUM 16
381
#define S390_R15_REGNUM 17
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/* Access Registers.  */
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#define S390_A0_REGNUM 18
384
#define S390_A1_REGNUM 19
385
#define S390_A2_REGNUM 20
386
#define S390_A3_REGNUM 21
387
#define S390_A4_REGNUM 22
388
#define S390_A5_REGNUM 23
389
#define S390_A6_REGNUM 24
390
#define S390_A7_REGNUM 25
391
#define S390_A8_REGNUM 26
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#define S390_A9_REGNUM 27
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#define S390_A10_REGNUM 28
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#define S390_A11_REGNUM 29
395
#define S390_A12_REGNUM 30
396
#define S390_A13_REGNUM 31
397
#define S390_A14_REGNUM 32
398
#define S390_A15_REGNUM 33
399
/* Floating Point Control Word.  */
400
#define S390_FPC_REGNUM 34
401
/* Floating Point Registers.  */
402
#define S390_F0_REGNUM 35
403
#define S390_F1_REGNUM 36
404
#define S390_F2_REGNUM 37
405
#define S390_F3_REGNUM 38
406
#define S390_F4_REGNUM 39
407
#define S390_F5_REGNUM 40
408
#define S390_F6_REGNUM 41
409
#define S390_F7_REGNUM 42
410
#define S390_F8_REGNUM 43
411
#define S390_F9_REGNUM 44
412
#define S390_F10_REGNUM 45
413
#define S390_F11_REGNUM 46
414
#define S390_F12_REGNUM 47
415
#define S390_F13_REGNUM 48
416
#define S390_F14_REGNUM 49
417
#define S390_F15_REGNUM 50
418
/* Total.  */
419
#define S390_NUM_REGS 51
420

    
421
/* Pseudo registers -- PC and condition code.  */
422
#define S390_PC_REGNUM S390_NUM_REGS
423
#define S390_CC_REGNUM (S390_NUM_REGS+1)
424
#define S390_NUM_PSEUDO_REGS 2
425
#define S390_NUM_TOTAL_REGS (S390_NUM_REGS+2)
426

    
427

    
428

    
429
/* Program Status Word.  */
430
#define S390_PSWM_REGNUM 0
431
#define S390_PSWA_REGNUM 1
432
/* General Purpose Registers.  */
433
#define S390_R0_REGNUM 2
434
#define S390_R1_REGNUM 3
435
#define S390_R2_REGNUM 4
436
#define S390_R3_REGNUM 5
437
#define S390_R4_REGNUM 6
438
#define S390_R5_REGNUM 7
439
#define S390_R6_REGNUM 8
440
#define S390_R7_REGNUM 9
441
#define S390_R8_REGNUM 10
442
#define S390_R9_REGNUM 11
443
#define S390_R10_REGNUM 12
444
#define S390_R11_REGNUM 13
445
#define S390_R12_REGNUM 14
446
#define S390_R13_REGNUM 15
447
#define S390_R14_REGNUM 16
448
#define S390_R15_REGNUM 17
449
/* Access Registers.  */
450
#define S390_A0_REGNUM 18
451
#define S390_A1_REGNUM 19
452
#define S390_A2_REGNUM 20
453
#define S390_A3_REGNUM 21
454
#define S390_A4_REGNUM 22
455
#define S390_A5_REGNUM 23
456
#define S390_A6_REGNUM 24
457
#define S390_A7_REGNUM 25
458
#define S390_A8_REGNUM 26
459
#define S390_A9_REGNUM 27
460
#define S390_A10_REGNUM 28
461
#define S390_A11_REGNUM 29
462
#define S390_A12_REGNUM 30
463
#define S390_A13_REGNUM 31
464
#define S390_A14_REGNUM 32
465
#define S390_A15_REGNUM 33
466
/* Floating Point Control Word.  */
467
#define S390_FPC_REGNUM 34
468
/* Floating Point Registers.  */
469
#define S390_F0_REGNUM 35
470
#define S390_F1_REGNUM 36
471
#define S390_F2_REGNUM 37
472
#define S390_F3_REGNUM 38
473
#define S390_F4_REGNUM 39
474
#define S390_F5_REGNUM 40
475
#define S390_F6_REGNUM 41
476
#define S390_F7_REGNUM 42
477
#define S390_F8_REGNUM 43
478
#define S390_F9_REGNUM 44
479
#define S390_F10_REGNUM 45
480
#define S390_F11_REGNUM 46
481
#define S390_F12_REGNUM 47
482
#define S390_F13_REGNUM 48
483
#define S390_F14_REGNUM 49
484
#define S390_F15_REGNUM 50
485
/* Total.  */
486
#define S390_NUM_REGS 51
487

    
488
/* Pseudo registers -- PC and condition code.  */
489
#define S390_PC_REGNUM S390_NUM_REGS
490
#define S390_CC_REGNUM (S390_NUM_REGS+1)
491
#define S390_NUM_PSEUDO_REGS 2
492
#define S390_NUM_TOTAL_REGS (S390_NUM_REGS+2)
493

    
494
/* CC optimization */
495

    
496
enum cc_op {
497
    CC_OP_CONST0 = 0,           /* CC is 0 */
498
    CC_OP_CONST1,               /* CC is 1 */
499
    CC_OP_CONST2,               /* CC is 2 */
500
    CC_OP_CONST3,               /* CC is 3 */
501

    
502
    CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
503
    CC_OP_STATIC,               /* CC value is env->cc_op */
504

    
505
    CC_OP_NZ,                   /* env->cc_dst != 0 */
506
    CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
507
    CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
508
    CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
509
    CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
510
    CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
511
    CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
512

    
513
    CC_OP_ADD_64,               /* overflow on add (64bit) */
514
    CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
515
    CC_OP_SUB_64,               /* overflow on substraction (64bit) */
516
    CC_OP_SUBU_64,              /* overflow on unsigned substraction (64bit) */
517
    CC_OP_ABS_64,               /* sign eval on abs (64bit) */
518
    CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
519

    
520
    CC_OP_ADD_32,               /* overflow on add (32bit) */
521
    CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
522
    CC_OP_SUB_32,               /* overflow on substraction (32bit) */
523
    CC_OP_SUBU_32,              /* overflow on unsigned substraction (32bit) */
524
    CC_OP_ABS_32,               /* sign eval on abs (64bit) */
525
    CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
526

    
527
    CC_OP_COMP_32,              /* complement */
528
    CC_OP_COMP_64,              /* complement */
529

    
530
    CC_OP_TM_32,                /* test under mask (32bit) */
531
    CC_OP_TM_64,                /* test under mask (64bit) */
532

    
533
    CC_OP_LTGT_F32,             /* FP compare (32bit) */
534
    CC_OP_LTGT_F64,             /* FP compare (64bit) */
535

    
536
    CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
537
    CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
538

    
539
    CC_OP_ICM,                  /* insert characters under mask */
540
    CC_OP_SLAG,                 /* Calculate shift left signed */
541
    CC_OP_MAX
542
};
543

    
544
static const char *cc_names[] = {
545
    [CC_OP_CONST0]    = "CC_OP_CONST0",
546
    [CC_OP_CONST1]    = "CC_OP_CONST1",
547
    [CC_OP_CONST2]    = "CC_OP_CONST2",
548
    [CC_OP_CONST3]    = "CC_OP_CONST3",
549
    [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
550
    [CC_OP_STATIC]    = "CC_OP_STATIC",
551
    [CC_OP_NZ]        = "CC_OP_NZ",
552
    [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
553
    [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
554
    [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
555
    [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
556
    [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
557
    [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
558
    [CC_OP_ADD_64]    = "CC_OP_ADD_64",
559
    [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
560
    [CC_OP_SUB_64]    = "CC_OP_SUB_64",
561
    [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
562
    [CC_OP_ABS_64]    = "CC_OP_ABS_64",
563
    [CC_OP_NABS_64]   = "CC_OP_NABS_64",
564
    [CC_OP_ADD_32]    = "CC_OP_ADD_32",
565
    [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
566
    [CC_OP_SUB_32]    = "CC_OP_SUB_32",
567
    [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
568
    [CC_OP_ABS_32]    = "CC_OP_ABS_32",
569
    [CC_OP_NABS_32]   = "CC_OP_NABS_32",
570
    [CC_OP_COMP_32]   = "CC_OP_COMP_32",
571
    [CC_OP_COMP_64]   = "CC_OP_COMP_64",
572
    [CC_OP_TM_32]     = "CC_OP_TM_32",
573
    [CC_OP_TM_64]     = "CC_OP_TM_64",
574
    [CC_OP_LTGT_F32]  = "CC_OP_LTGT_F32",
575
    [CC_OP_LTGT_F64]  = "CC_OP_LTGT_F64",
576
    [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
577
    [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
578
    [CC_OP_ICM]       = "CC_OP_ICM",
579
    [CC_OP_SLAG]      = "CC_OP_SLAG",
580
};
581

    
582
static inline const char *cc_name(int cc_op)
583
{
584
    return cc_names[cc_op];
585
}
586

    
587
/* SCLP PV interface defines */
588
#define SCLP_CMDW_READ_SCP_INFO         0x00020001
589
#define SCLP_CMDW_READ_SCP_INFO_FORCED  0x00120001
590

    
591
#define SCP_LENGTH                      0x00
592
#define SCP_FUNCTION_CODE               0x02
593
#define SCP_CONTROL_MASK                0x03
594
#define SCP_RESPONSE_CODE               0x06
595
#define SCP_MEM_CODE                    0x08
596
#define SCP_INCREMENT                   0x0a
597

    
598
typedef struct LowCore
599
{
600
    /* prefix area: defined by architecture */
601
    uint32_t        ccw1[2];                  /* 0x000 */
602
    uint32_t        ccw2[4];                  /* 0x008 */
603
    uint8_t         pad1[0x80-0x18];          /* 0x018 */
604
    uint32_t        ext_params;               /* 0x080 */
605
    uint16_t        cpu_addr;                 /* 0x084 */
606
    uint16_t        ext_int_code;             /* 0x086 */
607
    uint16_t        svc_ilc;                  /* 0x088 */
608
    uint16_t        svc_code;                 /* 0x08a */
609
    uint16_t        pgm_ilc;                  /* 0x08c */
610
    uint16_t        pgm_code;                 /* 0x08e */
611
    uint32_t        data_exc_code;            /* 0x090 */
612
    uint16_t        mon_class_num;            /* 0x094 */
613
    uint16_t        per_perc_atmid;           /* 0x096 */
614
    uint64_t        per_address;              /* 0x098 */
615
    uint8_t         exc_access_id;            /* 0x0a0 */
616
    uint8_t         per_access_id;            /* 0x0a1 */
617
    uint8_t         op_access_id;             /* 0x0a2 */
618
    uint8_t         ar_access_id;             /* 0x0a3 */
619
    uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
620
    uint64_t        trans_exc_code;           /* 0x0a8 */
621
    uint64_t        monitor_code;             /* 0x0b0 */
622
    uint16_t        subchannel_id;            /* 0x0b8 */
623
    uint16_t        subchannel_nr;            /* 0x0ba */
624
    uint32_t        io_int_parm;              /* 0x0bc */
625
    uint32_t        io_int_word;              /* 0x0c0 */
626
    uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
627
    uint32_t        stfl_fac_list;            /* 0x0c8 */
628
    uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
629
    uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
630
    uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
631
    uint32_t        external_damage_code;     /* 0x0f4 */
632
    uint64_t        failing_storage_address;  /* 0x0f8 */
633
    uint8_t         pad6[0x120-0x100];        /* 0x100 */
634
    PSW             restart_old_psw;          /* 0x120 */
635
    PSW             external_old_psw;         /* 0x130 */
636
    PSW             svc_old_psw;              /* 0x140 */
637
    PSW             program_old_psw;          /* 0x150 */
638
    PSW             mcck_old_psw;             /* 0x160 */
639
    PSW             io_old_psw;               /* 0x170 */
640
    uint8_t         pad7[0x1a0-0x180];        /* 0x180 */
641
    PSW             restart_psw;              /* 0x1a0 */
642
    PSW             external_new_psw;         /* 0x1b0 */
643
    PSW             svc_new_psw;              /* 0x1c0 */
644
    PSW             program_new_psw;          /* 0x1d0 */
645
    PSW             mcck_new_psw;             /* 0x1e0 */
646
    PSW             io_new_psw;               /* 0x1f0 */
647
    PSW             return_psw;               /* 0x200 */
648
    uint8_t         irb[64];                  /* 0x210 */
649
    uint64_t        sync_enter_timer;         /* 0x250 */
650
    uint64_t        async_enter_timer;        /* 0x258 */
651
    uint64_t        exit_timer;               /* 0x260 */
652
    uint64_t        last_update_timer;        /* 0x268 */
653
    uint64_t        user_timer;               /* 0x270 */
654
    uint64_t        system_timer;             /* 0x278 */
655
    uint64_t        last_update_clock;        /* 0x280 */
656
    uint64_t        steal_clock;              /* 0x288 */
657
    PSW             return_mcck_psw;          /* 0x290 */
658
    uint8_t         pad8[0xc00-0x2a0];        /* 0x2a0 */
659
    /* System info area */
660
    uint64_t        save_area[16];            /* 0xc00 */
661
    uint8_t         pad9[0xd40-0xc80];        /* 0xc80 */
662
    uint64_t        kernel_stack;             /* 0xd40 */
663
    uint64_t        thread_info;              /* 0xd48 */
664
    uint64_t        async_stack;              /* 0xd50 */
665
    uint64_t        kernel_asce;              /* 0xd58 */
666
    uint64_t        user_asce;                /* 0xd60 */
667
    uint64_t        panic_stack;              /* 0xd68 */
668
    uint64_t        user_exec_asce;           /* 0xd70 */
669
    uint8_t         pad10[0xdc0-0xd78];       /* 0xd78 */
670

    
671
    /* SMP info area: defined by DJB */
672
    uint64_t        clock_comparator;         /* 0xdc0 */
673
    uint64_t        ext_call_fast;            /* 0xdc8 */
674
    uint64_t        percpu_offset;            /* 0xdd0 */
675
    uint64_t        current_task;             /* 0xdd8 */
676
    uint32_t        softirq_pending;          /* 0xde0 */
677
    uint32_t        pad_0x0de4;               /* 0xde4 */
678
    uint64_t        int_clock;                /* 0xde8 */
679
    uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
680

    
681
    /* 0xe00 is used as indicator for dump tools */
682
    /* whether the kernel died with panic() or not */
683
    uint32_t        panic_magic;              /* 0xe00 */
684

    
685
    uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
686

    
687
    /* 64 bit extparam used for pfault, diag 250 etc  */
688
    uint64_t        ext_params2;               /* 0x11B8 */
689

    
690
    uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
691

    
692
    /* System info area */
693

    
694
    uint64_t        floating_pt_save_area[16]; /* 0x1200 */
695
    uint64_t        gpregs_save_area[16];      /* 0x1280 */
696
    uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
697
    uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
698
    uint32_t        prefixreg_save_area;       /* 0x1318 */
699
    uint32_t        fpt_creg_save_area;        /* 0x131c */
700
    uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
701
    uint32_t        tod_progreg_save_area;     /* 0x1324 */
702
    uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
703
    uint32_t        clock_comp_save_area[2];   /* 0x1330 */
704
    uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
705
    uint32_t        access_regs_save_area[16]; /* 0x1340 */
706
    uint64_t        cregs_save_area[16];       /* 0x1380 */
707

    
708
    /* align to the top of the prefix area */
709

    
710
    uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
711
} __attribute__((packed)) LowCore;
712

    
713
/* STSI */
714
#define STSI_LEVEL_MASK         0x00000000f0000000ULL
715
#define STSI_LEVEL_CURRENT      0x0000000000000000ULL
716
#define STSI_LEVEL_1            0x0000000010000000ULL
717
#define STSI_LEVEL_2            0x0000000020000000ULL
718
#define STSI_LEVEL_3            0x0000000030000000ULL
719
#define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
720
#define STSI_R0_SEL1_MASK       0x00000000000000ffULL
721
#define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
722
#define STSI_R1_SEL2_MASK       0x000000000000ffffULL
723

    
724
/* Basic Machine Configuration */
725
struct sysib_111 {
726
    uint32_t res1[8];
727
    uint8_t  manuf[16];
728
    uint8_t  type[4];
729
    uint8_t  res2[12];
730
    uint8_t  model[16];
731
    uint8_t  sequence[16];
732
    uint8_t  plant[4];
733
    uint8_t  res3[156];
734
};
735

    
736
/* Basic Machine CPU */
737
struct sysib_121 {
738
    uint32_t res1[80];
739
    uint8_t  sequence[16];
740
    uint8_t  plant[4];
741
    uint8_t  res2[2];
742
    uint16_t cpu_addr;
743
    uint8_t  res3[152];
744
};
745

    
746
/* Basic Machine CPUs */
747
struct sysib_122 {
748
    uint8_t res1[32];
749
    uint32_t capability;
750
    uint16_t total_cpus;
751
    uint16_t active_cpus;
752
    uint16_t standby_cpus;
753
    uint16_t reserved_cpus;
754
    uint16_t adjustments[2026];
755
};
756

    
757
/* LPAR CPU */
758
struct sysib_221 {
759
    uint32_t res1[80];
760
    uint8_t  sequence[16];
761
    uint8_t  plant[4];
762
    uint16_t cpu_id;
763
    uint16_t cpu_addr;
764
    uint8_t  res3[152];
765
};
766

    
767
/* LPAR CPUs */
768
struct sysib_222 {
769
    uint32_t res1[32];
770
    uint16_t lpar_num;
771
    uint8_t  res2;
772
    uint8_t  lcpuc;
773
    uint16_t total_cpus;
774
    uint16_t conf_cpus;
775
    uint16_t standby_cpus;
776
    uint16_t reserved_cpus;
777
    uint8_t  name[8];
778
    uint32_t caf;
779
    uint8_t  res3[16];
780
    uint16_t dedicated_cpus;
781
    uint16_t shared_cpus;
782
    uint8_t  res4[180];
783
};
784

    
785
/* VM CPUs */
786
struct sysib_322 {
787
    uint8_t  res1[31];
788
    uint8_t  count;
789
    struct {
790
        uint8_t  res2[4];
791
        uint16_t total_cpus;
792
        uint16_t conf_cpus;
793
        uint16_t standby_cpus;
794
        uint16_t reserved_cpus;
795
        uint8_t  name[8];
796
        uint32_t caf;
797
        uint8_t  cpi[16];
798
        uint8_t  res3[24];
799
    } vm[8];
800
    uint8_t res4[3552];
801
};
802

    
803
/* MMU defines */
804
#define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
805
#define _ASCE_SUBSPACE          0x200     /* subspace group control           */
806
#define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
807
#define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
808
#define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
809
#define _ASCE_REAL_SPACE        0x20      /* real space control               */
810
#define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
811
#define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
812
#define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
813
#define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
814
#define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
815
#define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
816

    
817
#define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
818
#define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
819
#define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
820
#define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
821
#define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
822
#define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
823
#define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
824

    
825
#define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
826
#define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
827
#define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
828

    
829
#define _PAGE_RO        0x200            /* HW read-only bit  */
830
#define _PAGE_INVALID   0x400            /* HW invalid bit    */
831

    
832

    
833

    
834
/* EBCDIC handling */
835
static const uint8_t ebcdic2ascii[] = {
836
    0x00, 0x01, 0x02, 0x03, 0x07, 0x09, 0x07, 0x7F,
837
    0x07, 0x07, 0x07, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
838
    0x10, 0x11, 0x12, 0x13, 0x07, 0x0A, 0x08, 0x07,
839
    0x18, 0x19, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
840
    0x07, 0x07, 0x1C, 0x07, 0x07, 0x0A, 0x17, 0x1B,
841
    0x07, 0x07, 0x07, 0x07, 0x07, 0x05, 0x06, 0x07,
842
    0x07, 0x07, 0x16, 0x07, 0x07, 0x07, 0x07, 0x04,
843
    0x07, 0x07, 0x07, 0x07, 0x14, 0x15, 0x07, 0x1A,
844
    0x20, 0xFF, 0x83, 0x84, 0x85, 0xA0, 0x07, 0x86,
845
    0x87, 0xA4, 0x5B, 0x2E, 0x3C, 0x28, 0x2B, 0x21,
846
    0x26, 0x82, 0x88, 0x89, 0x8A, 0xA1, 0x8C, 0x07,
847
    0x8D, 0xE1, 0x5D, 0x24, 0x2A, 0x29, 0x3B, 0x5E,
848
    0x2D, 0x2F, 0x07, 0x8E, 0x07, 0x07, 0x07, 0x8F,
849
    0x80, 0xA5, 0x07, 0x2C, 0x25, 0x5F, 0x3E, 0x3F,
850
    0x07, 0x90, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
851
    0x70, 0x60, 0x3A, 0x23, 0x40, 0x27, 0x3D, 0x22,
852
    0x07, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
853
    0x68, 0x69, 0xAE, 0xAF, 0x07, 0x07, 0x07, 0xF1,
854
    0xF8, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70,
855
    0x71, 0x72, 0xA6, 0xA7, 0x91, 0x07, 0x92, 0x07,
856
    0xE6, 0x7E, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
857
    0x79, 0x7A, 0xAD, 0xAB, 0x07, 0x07, 0x07, 0x07,
858
    0x9B, 0x9C, 0x9D, 0xFA, 0x07, 0x07, 0x07, 0xAC,
859
    0xAB, 0x07, 0xAA, 0x7C, 0x07, 0x07, 0x07, 0x07,
860
    0x7B, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
861
    0x48, 0x49, 0x07, 0x93, 0x94, 0x95, 0xA2, 0x07,
862
    0x7D, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50,
863
    0x51, 0x52, 0x07, 0x96, 0x81, 0x97, 0xA3, 0x98,
864
    0x5C, 0xF6, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
865
    0x59, 0x5A, 0xFD, 0x07, 0x99, 0x07, 0x07, 0x07,
866
    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
867
    0x38, 0x39, 0x07, 0x07, 0x9A, 0x07, 0x07, 0x07,
868
};
869

    
870
static const uint8_t ascii2ebcdic [] = {
871
    0x00, 0x01, 0x02, 0x03, 0x37, 0x2D, 0x2E, 0x2F,
872
    0x16, 0x05, 0x15, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
873
    0x10, 0x11, 0x12, 0x13, 0x3C, 0x3D, 0x32, 0x26,
874
    0x18, 0x19, 0x3F, 0x27, 0x22, 0x1D, 0x1E, 0x1F,
875
    0x40, 0x5A, 0x7F, 0x7B, 0x5B, 0x6C, 0x50, 0x7D,
876
    0x4D, 0x5D, 0x5C, 0x4E, 0x6B, 0x60, 0x4B, 0x61,
877
    0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7,
878
    0xF8, 0xF9, 0x7A, 0x5E, 0x4C, 0x7E, 0x6E, 0x6F,
879
    0x7C, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7,
880
    0xC8, 0xC9, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6,
881
    0xD7, 0xD8, 0xD9, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6,
882
    0xE7, 0xE8, 0xE9, 0xBA, 0xE0, 0xBB, 0xB0, 0x6D,
883
    0x79, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
884
    0x88, 0x89, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96,
885
    0x97, 0x98, 0x99, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6,
886
    0xA7, 0xA8, 0xA9, 0xC0, 0x4F, 0xD0, 0xA1, 0x07,
887
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
888
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
889
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
890
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
891
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
892
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
893
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
894
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
895
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
896
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
897
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
898
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
899
    0x3F, 0x59, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
900
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
901
    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
902
    0x90, 0x3F, 0x3F, 0x3F, 0x3F, 0xEA, 0x3F, 0xFF
903
};
904

    
905
static inline void ebcdic_put(uint8_t *p, const char *ascii, int len)
906
{
907
    int i;
908

    
909
    for (i = 0; i < len; i++) {
910
        p[i] = ascii2ebcdic[(int)ascii[i]];
911
    }
912
}
913

    
914
#define SIGP_SENSE             0x01
915
#define SIGP_EXTERNAL_CALL     0x02
916
#define SIGP_EMERGENCY         0x03
917
#define SIGP_START             0x04
918
#define SIGP_STOP              0x05
919
#define SIGP_RESTART           0x06
920
#define SIGP_STOP_STORE_STATUS 0x09
921
#define SIGP_INITIAL_CPU_RESET 0x0b
922
#define SIGP_CPU_RESET         0x0c
923
#define SIGP_SET_PREFIX        0x0d
924
#define SIGP_STORE_STATUS_ADDR 0x0e
925
#define SIGP_SET_ARCH          0x12
926

    
927
/* cpu status bits */
928
#define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
929
#define SIGP_STAT_INCORRECT_STATE   0x00000200UL
930
#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
931
#define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
932
#define SIGP_STAT_STOPPED           0x00000040UL
933
#define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
934
#define SIGP_STAT_CHECK_STOP        0x00000010UL
935
#define SIGP_STAT_INOPERATIVE       0x00000004UL
936
#define SIGP_STAT_INVALID_ORDER     0x00000002UL
937
#define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
938

    
939
void load_psw(CPUState *env, uint64_t mask, uint64_t addr);
940
int mmu_translate(CPUState *env, target_ulong vaddr, int rw, uint64_t asc,
941
                  target_ulong *raddr, int *flags);
942
int sclp_service_call(CPUState *env, uint32_t sccb, uint64_t code);
943
uint32_t calc_cc(CPUState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
944
                 uint64_t vr);
945

    
946
#define TARGET_HAS_ICE 1
947

    
948
/* The value of the TOD clock for 1.1.1970. */
949
#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
950

    
951
/* Converts ns to s390's clock format */
952
static inline uint64_t time2tod(uint64_t ns) {
953
    return (ns << 9) / 125;
954
}
955

    
956
static inline void cpu_inject_ext(CPUState *env, uint32_t code, uint32_t param,
957
                                  uint64_t param64)
958
{
959
    if (env->ext_index == MAX_EXT_QUEUE - 1) {
960
        /* ugh - can't queue anymore. Let's drop. */
961
        return;
962
    }
963

    
964
    env->ext_index++;
965
    assert(env->ext_index < MAX_EXT_QUEUE);
966

    
967
    env->ext_queue[env->ext_index].code = code;
968
    env->ext_queue[env->ext_index].param = param;
969
    env->ext_queue[env->ext_index].param64 = param64;
970

    
971
    env->pending_int |= INTERRUPT_EXT;
972
    cpu_interrupt(env, CPU_INTERRUPT_HARD);
973
}
974

    
975
#endif