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target-arm: Add support for AArch32 ARMv8 CRC32 instructions
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8and add a CPU feature flag to enable these instructions.
The CRC32-C implementation used is the built-in qemu implementation...
target-arm: Store AIF bits in env->pstate for AArch32
To avoid complication in code that otherwise would not need tocare about whether EL1 is AArch32 or AArch64, we should storethe interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIFin AArch64) in one place consistently regardless of EL1's mode....
target-arm: Implement AArch64 cache invalidate/clean ops
Implement all the AArch64 cache invalidate and clean ops(which are all NOPs since QEMU doesn't emulate the cache).The only remaining unimplemented cache op is DC ZVA.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Fix raw read and write functions on AArch64 registers
The raw read and write functions were using the ARM_CP_64BIT flag inri->type to determine whether to treat the register's state field asuint32_t or uint64_t; however AArch64 register info structs don't use...
target-arm: A64: Make cache ID registers visible to AArch64
Make the cache ID system registers (CLIDR, CSSELR, CCSIDR, CTR)visible to AArch64. These are mostly simple 64-bit extensions of theexisting 32 bit system registers and so can share reginfo definitions....
target-arm: Drop success/fail return from cpreg read and write functions
All cpreg read and write functions now return 0, so we can clean uptheir prototypes: * write functions return void * read functions return the value rather than taking a pointer to write the value to...
target-arm: Define names for SCTLR bits
The SCTLR is full of bits for enabling or disabling various things, and sothere are many places in the code which check if certain bits are set.Define some named constants for the SCTLR bits so these checks are easier...
ARM: Convert MIDR to a property
Convert the MIDR register to a property. This allows boards to later seta custom MIDR value. This has been done in such a way to maintaincompatibility with all existing CPUs and boards
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>...
Merge remote branch 'luiz/queue/qmp' into qmpq
target-arm: Switch ARMCPUInfo arrays to use terminator entries
Switch the ARMCPUInfo arrays in cpu.c and cpu64.c to use a terminatorentry rather than looping based on ARRAY_SIZE. The latter causescompile warnings on some versions of gcc if the configure options...
hw: Remove assert_no_error usages
Replace assert_no_error() usages with the error_abort system.&error_abort is passed into API calls to signal to the Error sub-systemthat any errors are fatal. Removes need for caller assertions.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
target-arm: Clean up handling of AArch64 PSTATE
The env->pstate field is a little odd since it doesn't strictlyspeaking represent an architectural register. However it's convenientfor QEMU to use it to hold the various PSTATE architectural bitsin the same format the architecture specifies for SPSR registers...
ARM: cpu: add "reset_hivecs" property
Add an ARM CPU property for the reset value of hivecs as it is aboard/SoC configurable setting.
The existence of the property is conditional on the ARM CPU not being Mclass.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>...
ARM: arm_cpu_reset: make it possible to use high vectors for reset_exc
If hivecs are being used on reset, the CPU should come out of reset atthe hivecs reset vector (0xFFFF0000)
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
target-arm: Define and use ARM_FEATURE_CBAR
Some processors (notably A9 within Highbank) define and use theCP15 configuration base address (CBAR). This is vendor specificso its best implemented as a CPU property (otherwise we would needvendor specific child classes for every ARM implementation)....
target-arm/cpu: Convert reset CBAR to a property
The reset value of the CP15 CBAR is a vendor (machine) configurableproperty. If ARM_FEATURE_CBAR is set, add it as a property atpost_init time.
target-arm: add support for v8 AES instructions
This adds support for the AESE/AESD/AESMC/AESIMC instructions thatare available on some v8 implementations of Aarch32.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>Message-id: 1386266078-6976-1-git-send-email-ard.biesheuvel@linaro.org...
target-arm: Don't hardcode KVM target CPU to be A15
Instead of assuming that a KVM target CPU must always be aCortex-A15 and hardcoding this in kvm_arch_init_vcpu(),store the KVM_ARM_TARGET_* value in the ARMCPU class,and use that.
target-arm: Add ARMCPU field for Linux device-tree 'compatible' string
Linux requires device tree CPU nodes to include a 'compatible'string describing the CPU. Add a field in the ARMCPU struct forthis so that boards which construct a device tree can insert...
target-arm: Allow secondary KVM CPUs to be booted via PSCI
New ARM boards are generally expected to boot their secondary CPUsvia the PSCI interface, rather than ad-hoc "loop around in holdingpen code" as hw/arm/boot.c implements. In particular this isnecessary for mach-virt kernels. For KVM we achieve this by creating...
target-arm: Disable 32 bit CPUs in 64 bit linux-user builds
If we're building aarch64-linux-user then the 32 bit CPUs areall unwanted, because they can't possibly execute the 64 bitbinaries we will be running; disable them.
target-arm: Prepare translation for AArch64 code
This patch adds all the prerequisites for AArch64 support that didn'tfit into split up patches. It extends important bits in the core cpuheaders to also take AArch64 mode into account.
Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag...
target-arm: Make '-cpu any' available in linux-user mode only
Make the 'any' CPU for target-arm available only in linux-user mode.The ARM target provides a CPU named "any", which turns on support forall user-level instruction set extensions we know about. This is...
target-arm: fix ARMv7M stack alignment on reset
When the initial SP is loaded from the vector table on ARMv7M systems the twoleast significant bits are ignored as the stack is always aligned at a four byteboundary (see ARM DDI 0403C, B1.4.1 and B1.5.5). So far QEMU did not ignore...
aio / timers: Switch entire codebase to the new timer API
This is an autogenerated patch using scripts/switch-timer-api.
Switch the entire code base to using the new timer API.
Note this patch may introduce some line length issues.
Signed-off-by: Alex Bligh <alex@alex.org.uk>...
target-arm: Implement the generic timer
The ARMv7 architecture specifies a 'generic timer' which is implementedvia cp15 registers. Newer kernels will prefer to use this rather thana devboard-level timer. Implement the generic timer for TCG; for KVMwe will already use the hardware's virtualized timer for this....
target-arm: Make IRQ and FIQ gpio lines on the CPU object
Now that ARMCPU is a subclass of DeviceState, we can make theCPU's inbound IRQ and FIQ lines be simply gpio lines, whichmeans we can remove the odd arm_pic shim.
We retain the arm_pic_init_cpu() function as a backwards...
cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"
Commit c643bed99 moved qemu_init_vcpu() calls to common CPUState code.This causes x86 cpu-add to fail with "KVM: setting VAPIC address failed".
The reason for the failure is that CPUClass::kvm_fd is not yet...
cpu: Introduce CPUClass::gdb_{read,write}_register()
Completes migration of target-specific code to new target-*/gdbstub.c.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Introduce CPUClass::gdb_core_xml_file for GDB_CORE_XML
Replace the GDB_CORE_XML define in gdbstub.c with a CPUClass field.Use first_cpu for qSupported and qXfer:features:read: for now.Add a stub for xml_builtin.
Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
CPUState::gdb_num_regs replaces num_g_regs.CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS.
Allows building gdb_register_coprocessor() for xtensa, too.
As a side effect this should fix coprocessor register numbering for SMP....
cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
Change breakpoint_invalidate() argument to CPUState alongside.
Since all targets now assign a softmmu-only field, we can drop helperscpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd()....
cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()
This moves setting the Program Counter from gdbstub into target code.Use vaddr type as upper-bound replacement for target_ulong.
target-arm: add feature flag for ARMv8
Signed-off-by: Mans Rullgard <mans@mansr.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
log: Change log_cpu_state[_mask]() argument to CPUState
Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turncpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is nolonger needed.
Add documentation and make the functions available through qemu/log.h...
cpu: Move reset logging to CPUState
x86 was using additional CPU_DUMP_* flags, so make that configurable inCPUClass::reset_dump_flags.
This adds reset logging for alpha, unicore32 and xtensa.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Reviewed-by: Richard Henderson <rth@twiddle.net>...
cpu: Change qemu_init_vcpu() argument to CPUState
This allows to move the call into CPUState's realizefn.Therefore move the stub into libqemustub.a.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
target-arm: Convert TCG to using (index,value) list for cp migration
Convert the TCG ARM target to using an (index,value) list for migratingcoprocessors. The primary benefit of the (index,value) list is forpassing state between KVM and QEMU, but it works for TCG-to-TCG...
target-arm: Make LPAE feature imply V7MP
The v7 ARM ARM specifies that the Large Physical AddressExtension requires implementation of the MultiprocessingExtensions, so make our LPAE feature imply V7MP ratherthan specifying both in the A15 CPU initfn....
target-arm: port ARM CPU save/load to use VMState
Port the ARM CPU save/load code to use VMState. Some state issaved in a slightly different order to simplify things -- forexample arrays are saved one after the other rather than 'striped',and we always save all 32 VFP registers even if the CPU happens...
cpu: Replace do_interrupt() by CPUClass::do_interrupt method
This removes a global per-target function and thus takes us one stepcloser to compiling multiple targets into one executable.
It will also allow to override the interrupt handling for certain CPU...
target-arm: Override do_interrupt for ARMv7-M profile
Enable ARMCPUInfo to specify a custom class_init functions.Introduce arm_v7m_class_init() and use it for "cortex-m3" model.
Instead of forwarding from arm_cpu_do_interrupt() to do_interrupt_v7m(),override CPUClass::do_interrupt with arm_v7m_cpu_do_interrupt()...
cpu: Add CPUArchState pointer to CPUState
The target-specific ENV_GET_CPU() macros have allowed us to navigatefrom CPUArchState to CPUState. The reverse direction was not supported.Avoid introducing CPU_GET_ENV() macros by initializing an untypedpointer that is initialized in derived instance_init functions....
target-arm: Move TCG initialization to ARMCPU initfn
Ensures that a QOM-created ARMCPU is usable.
target-arm: Update ARMCPU to QOM realizefn
Turn arm_cpu_realize() into a QOM realize function, no longer calledvia cpu.h prototype. To maintain the semantics of cpu_init(), setrealized = true explicitly in cpu_arm_init().
Move GDB coprocessor registration, CPU reset and vCPU initialization...
target-arm: Rename CPU types
In the initial conversion of CPU models to QOM types, model names weremapped 1:1 to type names. As a side effect this gained us a type "any",which is now a device.
To avoid "-device any" silliness and to pave the way for compiling...
target-arm: Catch attempt to instantiate abstract type in cpu_init()
This fixes -cpu arm-cpu asserting.
Cc: qemu-stable@nongnu.orgAcked-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-arm: Detect attempt to instantiate non-CPU type in cpu_init()
Consolidate model checking into a new arm_cpu_class_by_name().
If the name matches an existing type, also check whether that type isactually (a sub-type of) TYPE_ARM_CPU.
This fixes, e.g., -cpu tmp105 asserting....
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using anegative offset. Therefore the field is placed last in CPUState.
Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.
Move common parts of mips cpu_state_reset() to mips_cpu_reset()....
target-arm: use type_register() instead of type_register_static()
The type_register_static() interface is documented as:
type_register_static: @info: The #TypeInfo of the new type.
@info and all of the strings it points to should exist for the life...
softmmu: move include files to include/sysemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target-arm: Implement privileged-execute-never (PXN)
Implement the privileged-execute-never (PXN) translation table bit.It is implementation-defined whether this is implemented, so we giveit its own ARM_FEATURE_ flag. LPAE requires PXN, so add also anLPAE feature flag and the implication logic, as a placeholder...
target-arm: Extend feature flags to 64 bits
Extend feature flags to 64 bits, as we've just run out of spacein the 32 bit integer we were using for them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Remove ARM_CPUID_* macros
All the uses of ARM_CPUID() to vary behaviour have now beenremoved, so we can delete the ARM_CPUID_* macros now.The one exception is the TI915T/925T, because of its odd behaviourwhere the MIDR value can be changed at runtime....
target-arm: Convert final ID registers
Convert the final ID registers to the new cp15 scheme.
target-arm: Convert MPIDR
Convert the MPIDR to the new cp15 register scheme.This includes giving it its own feature bit ratherthan doing a CPUID value check.
target-arm: Convert cp15 cache ID registers
Convert the cp15 cache ID registers to the new scheme.
target-arm: Convert cp15 crn=0 crm={1,2} feature registers
Convert the cp15 crn=0 crm={1,2} features registers tothe new cp reg framework.
target-arm: Convert cp15 crn=1 registers
Convert the cp15 crn=1 registers to the new scheme.
target-arm: Convert cp15 crn=9 registers
Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme.
Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This isa change from previous behaviour, but a return to the behaviour of commit...
target-arm: Convert cp15 crn=6 registers
Convert the cp15 crn=6 registers to the new scheme.Note that this includes some minor tidyup: drop an unnecessaryunderdecoding of op2 on OMAPCP cores, and only implement thepre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5...
target-arm: convert cp15 crn=7 registers
Convert the cp15 crn=7 registers to the new scheme.Note that to do this we have to distinguish some registersused on the ARM9 and ARM10 from some which are ARM1176only. This is because the old code returned a value of 0...
target-arm: Convert cp15 crn=15 registers
Convert the cp15 crn=15 (implementation specific) registersto the new scheme.
target-arm: Convert cp15 crn=2 registers
Convert the cp15 crn=2 registers (MMU page table control,MPU cache control) to the new scheme.
target-arm: Convert performance monitor registers
Convert the v7 performance monitor cp15 registers tothe new scheme.
target-arm: Add register_cp_regs_for_features()
Add new function register_cp_regs_for_features() as a place toregister coprocessor registers dependent on feature flags.
target-arm: initial coprocessor register framework
Initial infrastructure for data-driven registration ofcoprocessor register implementations.
We still fall back to the old-style switch statements pendingcomplete conversion of all existing registers....
target-arm: Fix 11MPCore cache type register value
Make the 11MPCore report a valid value in its cache type register(the previous value appears to have been incorrectly copied fromthe 1136/1176). In particular, do not report that we have analiasing VIPT cache, because this causes Linux to attempt to use...
target-arm: Move A9 config_base_address reset value to ARMCPU
Move the A9 config_base_address cp15 register reset value toARMCPU. This should become a QOM property so that the Highbankboard can set it without having to pull in cpu-qom.h, but atleast this avoids the implicit dependency on reset ordering...
target-arm: Change cpu_arm_init() return type to ARMCPU
Make cpu_arm_init() return a QOM ARMCPU, so that we don't need toobtain an ARMCPU through arm_env_get_cpu() in machine init code.This requires to adjust the inclusion site of cpu-qom.h and in turn,...
target-arm: Move reset handling to arm_cpu_reset
Now that cpu_reset_model_id() has gone we can move thereset code over to the class reset function and have cpu_state_resetsimply do a reset on the CPU QOM object.
target-arm: Move cache ID register setup to cpu specific init fns
Move cache ID register reset out of cpu_reset_model_id() bycreating a field for the reset value in ARMCPU and setting itup in the cpu specific init functions.
target-arm: Move feature register setup to per-CPU init fns
Move feature register value setup to per-CPU init functions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Acked-by: Andreas Färber <afaerber@suse.de>
target-arm: Move SCTLR reset value setup to per cpu init fns
Move the reset value of SCTLR to ARMCPU, initialised inthe per-cpu init functions. It can then be reset by asimple copy, and we can drop the code from cpu_reset_model_id().
target-arm: Move CTR setup to per cpu init fns
Move CTR (cache type register) value to an ARMCPU fieldset up by per-cpu init fns.
target-arm: Move MVFR* setup to per cpu init fns
Move the MVFR* VFP feature register values to ARMCPU,so they are set up by the implementation-specific instanceinit functions rather than in cpu_reset_model_id().
target-arm: Move FPSID config to cpu init fns
Move the reset FPSID to the ARMCPU struct, and set it in theper-implementation instance init function. At reset we thenjust copy the reset value into the CPUARMState field.
target-arm: Move feature bit settings to CPU init fns
Move the setting of the feature bits from cpu_reset_model_id()to each CPU's instance init function. This requires us to movethe features field in CPUARMState so that it is not clearedon reset.
target-arm: Add QOM subclasses for each ARM cpu implementation
Register subclasses for each ARM CPU implementation.
Let arm_cpu_list() enumerate CPU subclasses in alphabetical order,except for special value "any".
Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the...
target-arm: Minimalistic CPU QOM'ification
Introduce only one non-abstract type TYPE_ARM_CPU and do not touchcp15 registers to not interfere with Peter's ongoing remodelling.Embed CPUARMState as first (additional) field of ARMCPU.
Let CPUClass::reset() call cpu_state_reset() for now....