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target-arm: Add support for AArch32 ARMv8 CRC32 instructions
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8and add a CPU feature flag to enable these instructions.
The CRC32-C implementation used is the built-in qemu implementation...
target-arm: A64: Implement MSR (immediate) instructions
Implement the MSR (immediate) instructions, which can update thePSTATE SP and DAIF fields.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
target-arm: Split cpreg access checks out from read/write functions
Several of the system registers handled via the ARMCPRegInfomechanism have access trap control bits controlling whether theregisters are accessible to lower privilege levels. Replacethe existing mechanism (allowing the read and write functions...
target-arm: A64: Implement remaining 3-same instructions
Implement the remaining instructions in the SIMD 3-reg-sameand scalar-3-reg-same groups: FMULX, FRECPS, FRSQRTS, FACGE,FACGT, FMLA and FMLS.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT
Implement the 2-reg-misc CNT, NOT and RBIT instructions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: Add set_neon_rmode helper
This helper sets the rounding mode in the standard_fp_status word toallow NEON instructions to modify the rounding mode whilst using thestandard FPSCR values for everything else.
Signed-off-by: Will Newton <will.newton@linaro.org>...
target-arm: A64: Add floating-point<->fixed-point instructions
This patch adds emulation for the instruction group labeled"Floating-point <-> fixed-point conversions" in the ARM ARM.
Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU(scalar, fixed-point)....
target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
This patch adds support for those instructions in the "Floating-pointdata-processing (1 source)" group which are simple 32-bit-to-32-bitor 64-bit-to-64-bit operations (ie everything except FCVT between...
target-arm: A64: Add support for FCVT between half, single and double
Add support for FCVT between half, single and double precision.
target-arm: Rename A32 VFP conversion helpers
The VFP conversion helpers for A32 round to zero as this is the onlyrounding mode supported. Rename these helpers to make it clear thatthey round to zero and are not suitable for use in the AArch64 code.
target-arm: A64: Add extra VFP fixed point conversion helpers
Define the full set of floating point to fixed point conversionhelpers required to support AArch64.
Signed-off-by: Will Newton <will.newton@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum
Use the VFP_BINOP macro to provide helpers for min, max, minnumand maxnum, rather than hand-rolling them. (The float64 maxversion is not used by A32 but will be needed for A64.)
target-arm: A64: add stubs for a64 specific helpers
We will need helpers that only make sense with AArch64. Addhelper-a64.{c,h} files as stubs that we can fill with thesehelpers in the following patches.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: add support for v8 AES instructions
This adds support for the AESE/AESD/AESMC/AESIMC instructions thatare available on some v8 implementations of Aarch32.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>Message-id: 1386266078-6976-1-git-send-email-ard.biesheuvel@linaro.org...
target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.
This adds support for the ARMv8 floating point VMAXNM and VMINNMinstructions.
Signed-off-by: Will Newton <will.newton@linaro.org>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Message-id: 1386158099-9239-6-git-send-email-will.newton@linaro.org...
tcg: Remove stray semi-colons from target-*/helper.h
During GEN_HELPER=1, these are actually stray top-level semi-colonswhich are technically invalid ISO C, but GCC accepts as an extension.If we added enough extension markers that we could dare use...
target-arm: Use mul[us]2 and add2 in umlal et al
Cc: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Implement adc_cc inline
Use add2 if available, otherwise use 64-bit arithmetic.
target-arm: Implement sbc_cc inline
Use sub2 if available, otherwise use 64-bit arithmetic.
exec: move include files to include/exec/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target-arm: rename helper flags
Rename helper flags to the new ones. This is purely a mechanical change,it's possible to use better flags by looking at the helpers.
Cc: Paul Brook <paul@codesourcery.com>Cc: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-arm: Use TCG operation for Neon 64 bit negation
Use the TCG operation to do Neon 64 bit negations rather than callinga helper routine for it.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Implement abs_i32 inline rather than as a helper
Implement abs_i32 inline (with movcond) rather than using a helperfunction.
target-arm: mark a few integer helpers const and pure
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: convert add_cc and sub_cc helpers to TCG
Now that the setcond TCG op is available, it's possible to replaceadd_cc and sub_cc helpers by TCG code. The code generated by TCG isactually very close to the one generated by GCC for the helper, and...
target-arm: convert sar, shl and shr helpers to TCG
Now that the movcond TCG op is available, it's possible to replaceshl and shr helpers by TCG code. The code generated by TCG is slightlylonger than the code generated by GCC for the helper but is still worth...
target-arm: convert void helpers
Add an explicit CPUState parameter instead of relying on AREG0.
For easier review, convert only op helpers which don't return any value.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: convert remaining helpers
Convert remaining helpers to AREG0 free mode: add an explicitCPUState parameter instead of relying on AREG0.
target-arm: Remove remaining old cp15 infrastructure
There are now no uses of the old cp15 infrastructure,so it can be deleted.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Convert TEECR, TEEHBR to new scheme
Convert the THUMB2EE cp14 registers TEECR and TEEHBR touse arm_cp_reginfo.
target-arm: Remove old cpu_arm_set_cp_io infrastructure
All the users of cpu_arm_set_cp_io have been converted, so wecan remove it and the infrastructure it used.
target-arm: initial coprocessor register framework
Initial infrastructure for data-driven registration ofcoprocessor register implementations.
We still fall back to the old-style switch statements pendingcomplete conversion of all existing registers....
target-arm: Implement VFPv4 fused multiply-accumulate insns
Implement the fused multiply-accumulate instructions (VFMA, VFMS,VFNMA, VFNMS) which are new in VFPv4.
Revert "target-arm: Use global env in neon_helper.c helpers"
This effectively reverts commit 2a3f75b42ac255be09ec2939b96c549ec830efd3so that we return to passing CPUState to helpers as an explicit parameter.(There were a number of conflicts in target-arm/translate.c which had...
target-arm: Pass fp status pointer explicitly to neon fp helpers
Make the Neon helpers for various floating point operations take anexplicit pointer to the float_status they use, so they don't rely onthe global environment pointer any more. This also allows us to drop...
target-arm: Make VFP binop helpers take pointer to fpstatus, not CPUState
Make the VFP binop helper functions take a pointer to the fp status, notthe entire CPUState. This will allow us to use them for Neon operations too.
Revert "target-arm: Use global env in iwmmxt_helper.c helpers"
This reverts commit 947a2fa21b61703802a660a938cabd7b3600ee79,returning the iwmmxt helpers to passing env in as a parameter.
target-arm: Use correct float status for Neon int-float conversions
The Neon versions of int-float conversions must use the "standard FPSCR" rather than the default FPSCR. Implement this by having the helperfunctions take a pointer to the appropriate float_status value rather...
move helpers.h to helper.h
This provides a consistent naming scheme across all targets.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>