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target-arm: Widen exclusive-access support struct fields to 64 bits
In preparation for adding support for A64 load/store exclusive instructions,widen the fields in the CPU state struct that deal with address and data valuesfor exclusives from 32 to 64 bits. Although in practice AArch64 and AArch32...
target-arm: Prepare translation for AArch64 code
This patch adds all the prerequisites for AArch64 support that didn'tfit into split up patches. It extends important bits in the core cpuheaders to also take AArch64 mode into account.
Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag...
target-arm: Implement the generic timer
The ARMv7 architecture specifies a 'generic timer' which is implementedvia cp15 registers. Newer kernels will prefer to use this rather thana devboard-level timer. Implement the generic timer for TCG; for KVMwe will already use the hardware's virtualized timer for this....
target-arm: Convert TCG to using (index,value) list for cp migration
Convert the TCG ARM target to using an (index,value) list for migratingcoprocessors. The primary benefit of the (index,value) list is forpassing state between KVM and QEMU, but it works for TCG-to-TCG...
target-arm: Initialize cpreg list from KVM when using KVM
When using KVM, use the kernel's initial state to set up thecpreg list, and sync to and from the kernel when doingmigration.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: port ARM CPU save/load to use VMState
Port the ARM CPU save/load code to use VMState. Some state issaved in a slightly different order to simplify things -- forexample arrays are saved one after the other rather than 'striped',and we always save all 32 VFP registers even if the CPU happens...
target-arm: Add some missing CPU state fields to VMState
A number of CPU state fields were accidentally omitted fromour migration state: some OMAP specific cp15 registers, andsome related to state for load/store exclusive insns. Add them.
target-arm: Correctly restore FPSCR
Use the helper functions to save and restore the FPSCR, so thatwe correctly propagate rounding mode and flushing behaviour intothe float_status fields. This also allows us to stop saving thevector length/stride fields separately....
target-arm: Extend feature flags to 64 bits
Extend feature flags to 64 bits, as we've just run out of spacein the 32 bit integer we were using for them.
target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE
Under LPAE, the cp15 registers PAR, TTBR0 and TTBR1 are extendedto 64 bits, with a 64 bit (MRRC/MCRR) access path to read thefull width of the register. Add the state fields for the tophalf and the 64 bit access path. Actual use of the top half of...
target-arm: Remove c0_cachetype CPUARMState field
Remove the no-longer-used CPUARMState c0_cachetype field.Although this was a constant register we had it in ourmigration state. Drop this (with resulting version bump)because for ARM currently we prefer cleaner migration...
arm: Add dummy support for co-processor 15's secure config register
Signed-off-by: Rob Herring <rob.herring@calxeda.com>Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
arm: add dummy A9-specific cp15 registers
Add dummy register support for the cp15, CRn=c15 registers.
config_base_register and power_control_register currentlydefault to 0, but may have improved support after the QOMCPU patches are finished.
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>...
target-arm/machine.c: Restore VFP registers correctly
Fix the restoring of VFP registers on vmload.
Signed-off-by: Dmitry Koshelev <karaghiozis@gmail.com>Reviewed-by: Juan Quintela <quintela@redhat.com>[peter.maydell: improved commit message a little]...
target-arm: Minimal implementation of performance counters
Newer Linux kernels assume the existence of the performance countercp15 registers. Provide a minimal implementation of these registers.We support no events. This should be compliant with the ARM ARM,...
target-arm: Implement cp15 VA->PA translation
Implement VA->PA translations by cp15-c7 that went through unchangedpreviously.
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Save/restore ARMv6 MMU state
Correctly save/restore ARMV6 MMU state.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Convert machine registration to use module init functions
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Syborg (Symbian Virtual Platform) board
A virtual reference platform for SymbianOS development/debugging.
ARM: basic SX1-cellphone sysemu support (Jean-Christophe PLAGNIOL-VILLARD).
The TSC2102 chip is not included in documentation because a patch ispending.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6038 c046a42c-6fe2-441c-8c8c-71466251a162
Remove unnecessary trailing newlines
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
Move CPU save/load registration to common code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
Provide basic emulation for Sharp SL-6000 PDA (Tosa), Dmitry Baryshkov.
This adds basic support for emulating Sharp Zaurus SL-6000 PDA (tosa).Currently it provides only basic support: no kbd/lcd, sound, ts, etc.But it's able at least to boot Linux from CF....
Add N810 to allowed -M values, add documentation part for N8x0.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4490 c046a42c-6fe2-441c-8c8c-71466251a162
remove target ifdefs from vl.c
(Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4327 c046a42c-6fe2-441c-8c8c-71466251a162