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target-arm: A64: Implement MSR (immediate) instructions
Implement the MSR (immediate) instructions, which can update thePSTATE SP and DAIF fields.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
target-arm: Drop success/fail return from cpreg read and write functions
All cpreg read and write functions now return 0, so we can clean uptheir prototypes: * write functions return void * read functions return the value rather than taking a pointer to write the value to...
target-arm: Split cpreg access checks out from read/write functions
Several of the system registers handled via the ARMCPRegInfomechanism have access trap control bits controlling whether theregisters are accessible to lower privilege levels. Replacethe existing mechanism (allowing the read and write functions...
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-arm: Implement adc_cc inline
Use add2 if available, otherwise use 64-bit arithmetic.
Cc: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Implement sbc_cc inline
Use sub2 if available, otherwise use 64-bit arithmetic.
exec: move include files to include/exec/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
exec: refactor cpu_restore_state
Refactor common code around calls to cpu_restore_state().
tb_find_pc() has now no external users, make it static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Remove out of date FIXME regarding saturating arithmetic
Remove an out of date FIXME regarding the saturating arithmetic helpers:we now do pass a pointer to CPUARMState to these helpers, and sincethe AREG0 changes went in there is no difference between helper.c...
target-arm: convert add_cc and sub_cc helpers to TCG
Now that the setcond TCG op is available, it's possible to replaceadd_cc and sub_cc helpers by TCG code. The code generated by TCG isactually very close to the one generated by GCC for the helper, and...
target-arm: convert sar, shl and shr helpers to TCG
Now that the movcond TCG op is available, it's possible to replaceshl and shr helpers by TCG code. The code generated by TCG is slightlylonger than the code generated by GCC for the helper but is still worth...
target-arm: convert void helpers
Add an explicit CPUState parameter instead of relying on AREG0.
For easier review, convert only op helpers which don't return any value.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: convert remaining helpers
Convert remaining helpers to AREG0 free mode: add an explicitCPUState parameter instead of relying on AREG0.
target-arm: final conversion to AREG0 free mode
Convert code load functions and switch to AREG0 free mode.
target-arm: Fix typos in comments
Fix a variety of typos in comments in target-arm files.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
target-arm: initial coprocessor register framework
Initial infrastructure for data-driven registration ofcoprocessor register implementations.
We still fall back to the old-style switch statements pendingcomplete conversion of all existing registers....
Use uintptr_t for various op related functions
Use uintptr_t instead of void * or unsigned long inseveral op related functions, env->mem_io_pc andGETPC macro.
Reviewed-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc] sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>...
ARM: fix segfault
Fix a bug in bccd9ec5f098668576342c83d90d6d6833d61d33,target-arm/op_helper.c missed a change unlike all other targets.This lead to a NULL pointer dereferences.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture localcpu_single_env hacks.
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h totarget-*/op_helper.c. Move also various other stuff only used inop_helper.c there.
Define global env in dyngen-exec.h.
For i386, move wrappers for segment and FPU helpers from user-exec.c...
cpu_loop_exit: avoid using AREG0
Make cpu_loop_exit() take a parameter for CPUState instead of relyingon global env.
Remove unused function parameter from cpu_restore_state
The previous patch removed the need for parameter puc.Is is now unused, so remove it.
Cc: Aurelien Jarno <aurelien@aurel32.net>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Weil <weil@mail.berlios.de>
move helpers.h to helper.h
This provides a consistent naming scheme across all targets.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Set the right overflow bit for neon 32 and 64 bit saturating add/sub.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
[PATCH] target-arm: remove unused functions cpu_lock(), cpu_unlock()
Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
target-arm: use native tcg-ops for ror/bic/vorn
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: convert NEON VZIP/VUZP/VTRN helper functions to pure TCG
The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16helpers used fixed registers to return values. This patch replaces that withTCG code, so T0/T1 is no longer directly used by the helper functions....
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
Update to a hopefully more future proof FSF address
target-arm: don't use T[x] in helper
(Torbjörn Andersson)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7034 c046a42c-6fe2-441c-8c8c-71466251a162
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Remove FORCE_RET() and RETURN
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5923 c046a42c-6fe2-441c-8c8c-71466251a162
Fix undeclared symbol warnings from sparse
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5539 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARM NEON vdup and vtbl bugs.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5286 c046a42c-6fe2-441c-8c8c-71466251a162
Fix smlald, smlsld, pkhtp, pkhbt, ssat, usat, umul, smul... (Laurent Desnogues).
helper.c - copy reference c0_c2 to runtime c0_c2 and not c0_c1
op_helper.c - remove old code (PARAM1, probably some left over from old dyngen) that broke do_[us]sat
translate.c...
Convert remaining __builtin_expect to likely/unlikely, by Jan Kiszka.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4840 c046a42c-6fe2-441c-8c8c-71466251a162
Fix off-by-one unwinding error.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
ARM N=Z=1 flag fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4156 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 14/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4151 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 13/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4150 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 12/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4149 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 10/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4147 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 9/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4146 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 8/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4145 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 7/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4144 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 4/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4141 c046a42c-6fe2-441c-8c8c-71466251a162
fixed invalid type
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3582 c046a42c-6fe2-441c-8c8c-71466251a162
ARMv7 support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3572 c046a42c-6fe2-441c-8c8c-71466251a162
Adjust s390 addresses (the MSB is defined as "to be ignored").
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3486 c046a42c-6fe2-441c-8c8c-71466251a162
Replace is_user variable with mmu_idx in softmmu core, allowing support of more than 2 mmu access modes.Add backward compatibility is_user variable in targets code when needed.Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions....
find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
Add Arm926 core support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1765 c046a42c-6fe2-441c-8c8c-71466251a162
ARM system emulation (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1661 c046a42c-6fe2-441c-8c8c-71466251a162
arm vfp fcmp and fcmpe instructions fix (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1382 c046a42c-6fe2-441c-8c8c-71466251a162
soft float support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1337 c046a42c-6fe2-441c-8c8c-71466251a162
ARM VFP support (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1309 c046a42c-6fe2-441c-8c8c-71466251a162