Archipelago » qemu

target-mips: add user-mode FR switch support for MIPS32r5

Description of UFR feature:

Required in MIPS32r5 if floating point is implemented and user-mode FR
switching is supported. The UFR register allows user-mode to clear StatusFR
by executing a CTC1 to UFR with GPR⁰ as input, and read StatusFR by...

target-mips: add support for CP0_Config4

Add CP0_Config4, define rw_bitmask.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>

target-mips: Use mul[us]2 in [D]MULT[U] insns

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

exec: move include files to include/exec/

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

target-mips: use the softfloat floatXX_muladd functions

Use the new softfloat floatXX_muladd() functions to implement the madd,
msub, nmadd and nmsub instructions. At the same time replace the name of
the helpers by the name of the instruction, as the only reason for the...

target-mips: Add ASE DSP compare-pick instructions

Add MIPS ASE DSP Compare-Pick instructions.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

target-mips: Add ASE DSP bit/manipulation instructions

Add MIPS ASE DSP Bit/Manipulation instructions.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

target-mips: Add ASE DSP arithmetic instructions

Add MIPS ASE DSP Arithmetic instructions.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

target-mips: Implement Loongson Multimedia Instructions

Implements all of the COP2 instructions except for the S<cond>
family of comparisons. The documentation is unclear for those.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

target-mips: Add compiler attribute to some functions which don't return

helper_raise_exception_err does not return, nor do helper_raise_exception
and do_unaligned_access.

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Weil <sw@weilnetz.de>...

target-mips: fix translation of MT instructions

The translation of dmt/emt/dvpe/evpe was doing the moral equivalent of:

int x;
  ...        /* no initialization of x */
  x = f (x);

which confused later bits of TCG rather badly, leading to crashes.

Fix the helpers to only return results (those instructions have no...

target-mips: microMIPS ASE support

Add instruction decoding for the microMIPS ASE. All we do is decode and
then forward to the existing gen_* routines.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

target-mips: make CP0_LLAddr register CPU dependent

Depending on the CPU, CP0_LLAddr is either read-only or read-write,
and the returned value can be shifted by a variable amount of bits.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>

target-mips: rename helpers from do_ to helper_

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6773 c046a42c-6fe2-441c-8c8c-71466251a162

target-mips: convert bit shuffle ops to TCG

Bit shuffle operations can be written with very few TCG instructions
(between 5 and 8), so it is worth converting them to TCG.

This code also move all bit shuffle generation code to a separate
function in order to have a cleaner exception code path, that is it...

target-mips: fix mft* helpers/call

This patch attempts to fix mft* helpers and the associated TCG calls.
mft* helpers do not take a register in argument, however:
- some helpers are called with an argument while they do not take one.
- some helpers are declared with an argument they don't use....

Use temporary registers for the MIPS FPU emulation.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4861 c046a42c-6fe2-441c-8c8c-71466251a162

Avoid unused input arguments which triggered tcg errors. Spotted by
Stefan Weil.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4795 c046a42c-6fe2-441c-8c8c-71466251a162

Use temporaries instead of fixed registers for some instructions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4784 c046a42c-6fe2-441c-8c8c-71466251a162

Convert unaligned load/store to TCG.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4759 c046a42c-6fe2-441c-8c8c-71466251a162

Convert remaining MIPS FP instructions to TCG.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4753 c046a42c-6fe2-441c-8c8c-71466251a162

Switch bitfield instructions and assorted special ops to TCG.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4739 c046a42c-6fe2-441c-8c8c-71466251a162

Call most FP helpers without deroute through op.c

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4734 c046a42c-6fe2-441c-8c8c-71466251a162

Register helper functions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4700 c046a42c-6fe2-441c-8c8c-71466251a162

Add file left out from previous commit.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4497 c046a42c-6fe2-441c-8c8c-71466251a162