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target-mips: add user-mode FR switch support for MIPS32r5
Description of UFR feature:
Required in MIPS32r5 if floating point is implemented and user-mode FRswitching is supported. The UFR register allows user-mode to clear StatusFRby executing a CTC1 to UFR with GPR0 as input, and read StatusFR by...
target-mips: add support for CP0_Config5
Add CP0_Config5, define rw_bitmask and enable modifications.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
target-mips: add support for CP0_Config4
Add CP0_Config4, define rw_bitmask.
cpu: Use QTAILQ for CPU list
Introduce CPU_FOREACH(), CPU_FOREACH_SAFE() and CPU_NEXT() shorthandmacros.
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-mips: Remove assignment to a variable which is never used
This assignment causes a compiler warning for compilations with the compileroption -Wunused-but-set-variable (which is included with -Wextra).
Removing it allows using -Wextra for QEMU code without suppressing too many...
cpu: Make first_cpu and next_cpu CPUState
Move next_cpu from CPU_COMMON to CPUState.Move first_cpu variable to qom/cpu.h.
gdbstub needs to use CPUState::env_ptr for now.cpu_copy() no longer needs to save and restore cpu_next.
Acked-by: Paolo Bonzini <pbonzini@redhat.com>...
cpu: Turn cpu_unassigned_access() into a CPUState hook
Use it for all targets, but be careful not to pass invalid CPUState.cpu_single_env can be NULL, e.g. on Xen.
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
exec: Pass CPUState to cpu_reset_interrupt()
Move it to qom/cpu.c to avoid build failures depending on include orderof cpu-qom.h and exec/cpu-all.h.
Change opaques of various ..._irq_handler() functions to theappropriate CPU type to facilitate using cpu_reset_interrupt()....
cpu: Pass CPUState to cpu_interrupt()
Move it to qom/cpu.h to avoid issues with include order.
Change pc_acpi_smi_interrupt() opaque to X86CPU.
target-mips: Use mul[us]2 in [D]MULT[U] insns
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-mips: Unfuse {,N}M{ADD,SUB}.fmt
Turn MADD.fmt, MSUB.fmt, NMADD.fmt and NMSUB.fmt from fused to unfusedoperations, so that they behave in the same way as a separate multiplicationand addition. The instructions were only fused in early MIPS IV processors....
exec: Return CPUState from qemu_get_cpu()
Move the declaration to qemu/cpu.h and add documentation.The implementation still depends on CPUArchState for CPU iteration.
cpu: Move nr_{cores,threads} fields to CPUState
To facilitate the field movements, pass MIPSCPU to malta_mips_config();avoid that for mips_cpu_map_tc() since callers only access MIPS ThreadContexts, inside TCG helpers.
target-mips: Clean up mips_cpu_map_tc() documentation
This function will be touched again soon, so a good understanding of envvs. other helps. Adopt gtk-doc style.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Eric Johnson <ericj@mips.com>
target-mips: Replace macros by inline functions
The macros RESTORE_ROUNDING_MODE and RESTORE_FLUSH_MODE silently usedvariable env from their callers. Using inline functions with env passedas a function argument is more transparent.
This modification was proposed by Peter Maydell....
target-mips: Use EXCP_SC rather than a magic number
From the discussion on the ML [1], the exception limit defined bymagic number 0x100 is actually EXCP_SC defined in cpu.h. Replace themagic number with EXCP_SC. Remove "#if 1 .. #endif" as well.
[1] http://lists.gnu.org/archive/html/qemu-devel/2012-11/msg03080.html...
target-mips: Remove semicolon from macro definition
Macro RESTORE_FLUSH_MODE is similar to RESTORE_ROUNDING_MODEbut included a semicolon.
The code which uses that macro also includes a semicolon,so the result was an empty statement.
Remove the superfluous semicolon from the macro definition....
misc: move include files to include/qemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
exec: move include files to include/exec/
exec: refactor cpu_restore_state
Refactor common code around calls to cpu_restore_state().
tb_find_pc() has now no external users, make it static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-mips: fix TLBR wrt SEGMask
Like r4k_map_address(), r4k_helper_tlbp() should use SEGMask to mask theaddress.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: don't flush extra TLB on permissions upgrade
If the guest uses a TLBWI instruction for upgrading permissions, wedon't need to flush the extra TLBs. This improve boot time performanceby about 10%.
target-mips: simplify load/store microMIPS helpers
load/store microMIPS helpers are reinventing the wheel. Call do_lw,do_ll, do_sw and do_sl instead of using a macro calling the cpu_*load/store functions.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-mips: implement unaligned loads using TCG
Load/store from helpers should be avoided as they are quiteinefficient. Rewrite unaligned loads instructions using TCG andaligned loads. The number of actual loads operations to implementan unaligned load instruction is reduced from up to 8 to 1....
target-mips: keep softfloat exception set to 0 between instructions
Instead of clearing the softfloat exception flags before each floatingpoint instruction, reset them to 0 in update_fcr31() when an exceptionis detected.
target-mips: fix FPU exceptions
For each FPU instruction that can trigger an FPU exception, to callcall update_fcr31() after.
Remove the manual NaN assignment in case of float to float operation, assoftfloat is already taking care of that. However for float to int...
target-mips: cleanup float to int conversion helpers
Instead of accessing the flags from the floating point controlregister after updating it, read the softfloat flags.
This is just code cleanup and should not change the behaviour.
target-mips: use softfloat constants when possible
softfloat already has a few constants defined, use them instead ofredefining them in target-mips.
Rename FLOAT_SNAN32 and FLOAT_SNAN64 to FP_TO_INT32_OVERFLOW andFP_TO_INT64_OVERFLOW as even if they have the same value, they are...
target-mips: restore CPU state after an FPU exception
Rework raise_exception() functions so that they can be called fromother helpers, passing the return address as an argument.
Use do_raise_exception() function in update_fcr31() to correctly restore...
target-mips: use the softfloat floatXX_muladd functions
Use the new softfloat floatXX_muladd() functions to implement the madd,msub, nmadd and nmsub instructions. At the same time replace the name ofthe helpers by the name of the instruction, as the only reason for the...
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes arereserved) and its purpose doesn't match the name (most target_phys_addr_taddresses are not target specific). Replace it with a finger-friendly,...
target-mips: Pass MIPSCPU to mips_vpe_is_wfi()
Needed for moving halted field to CPUState.The variable name "c" is retained for MIPSCPU to leave "cpu" for CPUState.
Also change return type to bool while at it.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-mips: Pass MIPSCPU to mips_tc_sleep()
Needed for changing mips_vpe_sleep() argument type to MIPSCPU.
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Pass MIPSCPU to mips_vpe_sleep()
Needed for moving halted field to CPUState.
target-mips: Clean up other_cpu in helper_{d,e}vpe()
Free the variable name "other_cpu" for later use for MIPSCPU.
Fix off-by-one indentation while at it.
target-mips: Pass MIPSCPU to mips_tc_wake()
Needed for changing mips_vpe_is_wfi() argument type to MIPSCPU.
target-mips: switch to AREG0 free mode
Add an explicit CPUState parameter instead of relying on AREG0and switch to AREG0 free mode.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Aurelien Jarno <aurelien@aurel32.net>
MIPS/user: Fix reset CPU state initialization
This change updates the CPU reset sequence to use a common piece of codethat figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1Xnot being set where applicable that causes floating-point MADD family...
target-mips: Fix some helper functions (VR54xx multiplication)
Commits b5dc7732e1cc2fb549e48b7b5d664f2c79628e2e andbe24bb4f3007c3e07cbf1934f7e781493d876ab7 optimized the codeand removed the correct setting of t0. Fix this.
gcc-4.7 detected this bug because parameter arg1 was unused...
target-mips: Remove unused inline function
Function set_HILO is not needed anywhere.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
target-mips: Fix type cast for w64 (uintptr_t)
This changes nothing for other hosts.
Use uintptr_t for various op related functions
Use uintptr_t instead of void * or unsigned long inseveral op related functions, env->mem_io_pc andGETPC macro.
Reviewed-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-mips: Add compiler attribute to some functions which don't return
helper_raise_exception_err does not return, nor do helper_raise_exceptionand do_unaligned_access.
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <sw@weilnetz.de>...
target-mips: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc] sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Spelling fixes in comments (it's -> its)
Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Stefan Weil <sw@weilnetz.de>...
softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture localcpu_single_env hacks.
mips: Add MT halting and waking of VPEs
+ some partial support for TC's.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
mips: Handle TC indexing of other VPEs
Introduce mips_cpu_map_tc() to map a global TC index into a VPE nrand local tc index.
mips: Synchronize CP0 TCSTatus, Status and EntryHi
These registers share some of their fields. Writes to these fieldsshould be visible through the corresponding mirror fields.
mips: Hook in more reg accesses via mttr/mftr
mips: Correct IntCtl write mask for VInt
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h totarget-*/op_helper.c. Move also various other stuff only used inop_helper.c there.
Define global env in dyngen-exec.h.
For i386, move wrappers for segment and FPU helpers from user-exec.c...
Fix unassigned memory access handling
cea5f9a28faa528b6b1b117c9ab2d8828f473fef exposed bugs in unassigned memoryaccess handling. Fix them by always passing CPUState to the handlers.
Reported-by: Hervé Poussineau <hpoussin@reactos.org>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
cpu_loop_exit: avoid using AREG0
Make cpu_loop_exit() take a parameter for CPUState instead of relyingon global env.
Remove unused function parameter from cpu_restore_state
The previous patch removed the need for parameter puc.Is is now unused, so remove it.
Cc: Aurelien Jarno <aurelien@aurel32.net>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Weil <weil@mail.berlios.de>
target-mips: simplify FP comparisons
As the softfloat comparison functions already test for NaN, there is noneed to always call the float*_unordered*() functions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: don't hardcode softfloat exception bits
target-mips: fix c.ps.* instructions
Contrary to cabs.ps.* instructions, c.ps.* should not compare the absolutevalue of the operand, but directly the operands.
target-mips: clear softfpu exception state for comparison instructions
MIPS FPU instructions should start with a clean softfpu status. Thisis done for the most instructions, but not for comparison ones.
target-mips: use new float*_unordered*() functions
Use the new float*_unordered*() functions from softfloat instead ofredefining a private version.
softfloat: rename float*_eq() into float*_eq_quiet()
float*_eq functions have a different semantics than other comparisonfunctions. Fix that by first renaming float*_quiet() into float*_eq_quiet().
Note that it is purely mechanical, and the behaviour should be unchanged....
[PATCH] [MIPS] Clear softfpu exception state for round, trunc, ceil and floor
MIPS FPU instructions should start with a clean softfpu status. Thisis done for the arithmetic operations and cvt instructions, but notfor round, trunc, ceil and floor.
Signed-off-by: Chris Dearman <chris@mips.com>...
softfloat: Rename float*_is_nan() functions to float*_is_quiet_nan()
The softfloat functions float*_is_nan() were badly misnamed,because they return true only for quiet NaNs, not for all NaNs.Rename them to float*_is_quiet_nan() to more accurately reflect...
target-mips: fix translation of MT instructions
The translation of dmt/emt/dvpe/evpe was doing the moral equivalent of:
int x; ... /* no initialization of x */ x = f (x);
which confused later bits of TCG rather badly, leading to crashes.
Fix the helpers to only return results (those instructions have no...
MIPS: fix yield handling
The parameter for yield should be handled as a signed integerfor the comparisons to have any effect.
This also avoids a gcc warning with -Wtype-limits.
Correctly identify multiple cpus in SMP systems
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
mips: more fixes to the MIPS interrupt glue logic
Commit 36388314febad3d7675ab919287f03733a560ff6 moved most of theinterrupt logic to cpu-exec.c. Remove the remaining useless codeand fix software interrupts.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
mips: Correct MIPS interrupt glue logic for icount
When hw interrupt pending bits in CP0_Cause are set, the CPU shouldsee the hw interrupt line as active. The CPU may or may not take theinterrupt based on internal state (global irq mask etc) but the glue...
remove unused stuff from */exec.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-mips: microMIPS ASE support
Add instruction decoding for the microMIPS ASE. All we do is decode andthen forward to the existing gen_* routines.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: don't call cpu_loop_exit() from helper.c
In helper.c AREG0 may not correspond do env, so it's not possible tocall cpu_loop_exit() here. Call it from op_helper.c instead.
target-mips: change interrupt bits to be mips16-aware
We need to stash the operating mode into the low bit of the error PC andrestore it on return from interrupts.
target-mips: use physical address in lladdr
Currently the ll/sc instructions use the virtual address in bothuser and system mode. Use the physical address insteead in systemmode.
target-mips: factorize load/store code in op_helper.c
target-mips: make CP0_LLAddr register CPU dependent
Depending on the CPU, CP0_LLAddr is either read-only or read-write,and the returned value can be shifted by a variable amount of bits.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
target-mips: rename CP0_LLAddr into lladdr
The variable CP0_LLAddr represent the full lladdr, not the actualregister value, which is only part of this value and depends on theCPU.
target-mips: fix indentation
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
Add 'static' to please Sparse
Update to a hopefully more future proof FSF address
target-mips: variable names consistency
Use a consistent naming of arguments and TCG variables across the wholefile, the same as in tcg/tcg-op.h:- arg1, arg2, ... for arguments- t0, t1, t2, ... for variables
target-mips: implement FPU Flush-To-Zero mode
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6914 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: remove dead code
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6774 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: rename helpers from do_ to helper_
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6773 c046a42c-6fe2-441c-8c8c-71466251a162
global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &X) qemu_log()' statement.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
Remove all tabs from target-mips/*
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6306 c046a42c-6fe2-441c-8c8c-71466251a162
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Fix remaining compiler warnings for mips targets.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6111 c046a42c-6fe2-441c-8c8c-71466251a162
MIPS: remove a few warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5944 c046a42c-6fe2-441c-8c8c-71466251a162
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: convert bit shuffle ops to TCG
Bit shuffle operations can be written with very few TCG instructions(between 5 and 8), so it is worth converting them to TCG.
This code also move all bit shuffle generation code to a separatefunction in order to have a cleaner exception code path, that is it...
target-mips: convert bitfield ops to TCG
Bitfield operations can be written with very few TCG instructions(between 2 and 5), so it is worth converting them to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5678 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: fix mft* helpers/call
This patch attempts to fix mft* helpers and the associated TCG calls.mft* helpers do not take a register in argument, however:- some helpers are called with an argument while they do not take one.- some helpers are declared with an argument they don't use....
Show size for unassigned accesses (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5436 c046a42c-6fe2-441c-8c8c-71466251a162
Move the active FPU registers into env again, and use more TCG registersto access them.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5252 c046a42c-6fe2-441c-8c8c-71466251a162
MIPS: Fix tlbwi/tlbwr
In CP0 Index register, bit 31 means 'Probe Failure', while lowest bitscontain the TLB index.
In tlbwi and tlbwr instructions, this Probe Failure bit must be ignoredwhen reading the TLB index.
Attached patch fixes it.
(Hervé Poussineau)...