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# Date Author Comment
f976b09e 12/22/2013 08:15 pm Alexander Graf

PPC: Fix compilation with TCG debug

The recent VSX patches broken compilation of QEMU when configurated
with --enable-debug, as it was treating "target long" TCG variables
as "i64" which is not true for 32bit targets.

This patch fixes all the places that the compiler has found to use...
acc42968 12/20/2013 02:58 am Tom Musta

Add xxsldwi

This patch adds the VSX Shift Left Double by Word Immediate
(xxsldwi) instruction.

Signed-off-by: Tom Musta <>
Signed-off-by: Alexander Graf <>
76c15fe0 12/20/2013 02:58 am Tom Musta

Add xxspltw

This patch adds the VSX Splat Word (xxsplatw) instruction.

This is the first instruction to use the UIM immediate field
and consequently a decoder is also added.

V2: reworked implementation per Richard Henderson's comments.

Signed-off-by: Tom Musta <>...
551e3ef7 12/20/2013 02:58 am Tom Musta

Add xxsel

This patch adds the VSX Select (xxsel) instruction.

The xxsel instruction has four VSR operands. Thus the xC
instruction decoder is added.

The xxsel instruction is massively overloaded in the opcode
table since only bits 26 and 27 are opcode bits. This...
79ca8a6a 12/20/2013 02:58 am Tom Musta

Add Power7 VSX Logical Instructions

This patch adds the VSX logical instructions that are defined
by the Version 2.06 Power ISA (aka Power7):

- xxland
   - xxlandc
   - xxlor
   - xxlxor
   - xxlnor

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
ce577d2e 12/20/2013 02:58 am Tom Musta

Add xxmrgh/xxmrgl

This patch adds the VSX Merge High Word and VSX Merge Low Word
instructions.

V2: Now implemented using deposit (per Richard Henderson's comment)

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
be574920 12/20/2013 02:58 am Tom Musta

Add VSX Vector Move Instructions

This patch adds the vector move instructions:

- xvabsdp - Vector Absolute Value Double-Precision
  - xvnabsdp - Vector Negative Absolute Value Double-Precision
  - xvnegdp - Vector Negate Double-Precision
  - xvcpsgndp - Vector Copy Sign Double-Precision...
df020ce0 12/20/2013 02:58 am Tom Musta

Add VSX Scalar Move Instructions

This patch adds the VSX scalar move instructions:

- xsabsdp (Scalar Absolute Value Double-Precision)
  - xsnabspd (Scalar Negative Absolute Value Double-Precision)
  - xsnegdp (Scalar Negate Double-Precision)
  - xscpsgndp (Scalar Copy Sign Double-Precision)...
86e61ce3 12/20/2013 02:57 am Tom Musta

Add stxvw4x

This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x)
instruction.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Reviewed-by: Paolo Bonzini <>
Signed-off-by: Alexander Graf <>
9231ba9e 12/20/2013 02:57 am Tom Musta

Add stxsdx

This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)
instruction.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Reviewed-by: Paolo Bonzini <>
Signed-off-by: Alexander Graf <>
897e61d1 12/20/2013 02:57 am Tom Musta

Add lxvw4x

This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)
instruction.

V2: changed to use deposit_i64 per Richard Henderson's review.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Reviewed-by: Paolo Bonzini <>...
ca03b467 12/20/2013 02:57 am Tom Musta

Add lxvdsx

This patch adds the Load VSX Vector Doubleword & Splat Indexed
(lxvdsx) instruction.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Reviewed-by: Paolo Bonzini <>
Signed-off-by: Alexander Graf <>
fa1832d7 12/20/2013 02:57 am Tom Musta

Add lxsdx

This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
instruction.

The lower 8 bytes of the target register are undefined; this
implementation leaves those bytes unaltered.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
cd73f2c9 12/20/2013 02:57 am Tom Musta

Add xxpermdi

This patch adds the xxpermdi instruction. The instruction
uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX
and BX). This results in overloading of the opcode table
with aliases, which can be seen in the GEN_XX3FORM_DM
macro.

Signed-off-by: Tom Musta <>...
fbed2478 12/20/2013 02:57 am Tom Musta

Add stxvd2x

This patch adds the stxvd2x instruction.

Signed-off-by: Tom Musta <>
Signed-off-by: Anton Blanchard <>
Signed-off-by: Alexander Graf <>
304af367 12/20/2013 02:57 am Tom Musta

Add lxvd2x

This patch adds the lxvd2x instruction.

Signed-off-by: Tom Musta <>
Signed-off-by: Anton Blanchard <>
Signed-off-by: Alexander Graf <>
472b24ce 12/20/2013 02:57 am Tom Musta

Add VSR to Global Registers

This patch adds VSX VSRs to the the list of global register indices.
More specifically, it adds the lower halves of the first 32 VSRs to
the list of global register indices. The upper halves of the first
32 VSRs are already defined via cpu_fpr[]. And the second 32 VSRs...
f9fc6d81 12/20/2013 02:57 am Tom Musta

Add VSX Instruction Decoders

This patch adds decoders for the VSX fields XT, XS, XA, XB and
DM. The first four are split fields and a general helper for
these types of fields is also added.

Signed-off-by: Tom Musta <>
Signed-off-by: Anton Blanchard <>...
1f29871c 12/20/2013 02:57 am Tom Musta

Add MSR VSX and Associated Exception

This patch adds support for the VSX bit of the PowerPC Machine
State Register (MSR) as well as the corresponding VSX Unavailable
exception.

The VSX bit is added to the defined bits masks of the Power7 and
Power8 CPU models....
5cd8f621 10/10/2013 09:43 pm Richard Henderson

tcg: Move helper registration into tcg_context_init

No longer needs to be done on a per-target basis.

Signed-off-by: Richard Henderson <>
97577fd4 09/20/2013 01:37 pm James Hogan

cpu: Move cpu state syncs up into cpu_dump_state()

The x86 and ppc targets call cpu_synchronize_state() from their
*_cpu_dump_state() callbacks to ensure that up to date state is dumped
when KVM is enabled (for example when a KVM internal error occurs).
...
545825d4 09/03/2013 02:35 am Aurelien Jarno

Merge branch 'tcg-next' of git://github.com/rth7680/qemu

  • 'tcg-next' of git://github.com/rth7680/qemu: (29 commits)
    tcg-i386: Make use of zero-extended memory helper routines
    tcg: Introduce zero and sign-extended versions of load helpers
    exec: Split softmmu_defs.h...
8cfd0495 09/02/2013 07:08 pm Richard Henderson

tcg: Change tcg_gen_exit_tb argument to uintptr_t

And update all users.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
779f6590 09/02/2013 11:06 am Aurelien Jarno

target-ppc: fix bit extraction for FPBF and FPL

Bit extraction for the FP BF and L field of the MTFSFI and MTFSF
instructions is wrong and doesn't match the reference manual (which
explain the bit number in big endian format). It has been broken in
commit 7d08d85645def18eac2a9d672c1868a35e0bcf79....
ed2803da 07/23/2013 03:41 am Andreas Färber

cpu: Move singlestep_enabled field from CPU_COMMON to CPUState

Prepares for changing cpu_single_step() argument to CPUState.

Acked-by: Michael Walle <> (for lm32)
Signed-off-by: Andreas Färber <>
213fe1f5 07/09/2013 10:33 pm Andreas Färber

target-ppc: Change gen_intermediate_code_internal() argument to PowerPCCPU

Also use bool type while at it.

Prepares for moving singlestep_enabled field to CPUState.

Reviewed-by: Richard Henderson <>
Signed-off-by: Andreas Färber <>
cb446eca 06/28/2013 02:25 pm Andreas Färber

kvm: Change cpu_synchronize_state() argument to CPUState

Change Monitor::mon_cpu to CPUState as well.

Reviewed-by: liguang <>
Acked-by: Paolo Bonzini <>
Signed-off-by: Andreas Färber <>
878096ee 06/28/2013 02:25 pm Andreas Färber

cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks

Make cpustats monitor command available unconditionally.

Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()
arguments to CPUState.

Signed-off-by: Andreas Färber <>
36f48d9c 05/08/2013 09:23 pm Alexander Graf

PPC: Depend behavior of cmp instructions only on instruction encoding

When running an L=1 cmp instruction on a 64bit PPC CPU with SF off, it
still behaves identical to what it does when SF is on. Remove the implicit
difference in the code.

Also, on most 32bit CPUs we should always treat the compare as 32bit...
554ecc57 05/08/2013 09:23 pm Alexander Graf

PPC: Fix rldcl

The implementation for rldcl tried to always fetch its
parameters from the opcode, even though the opcode was
already passed in in decoded and different forms.

Use the parameters instead, fixing rldcl.

Reported-by: Torbjorn Granlund <>...
c05541ee 05/06/2013 06:22 pm Anton Blanchard

target-ppc: Fix invalid SPR read/write warnings

Invalid and privileged SPR warnings currently print the wrong
address. While fixing that, also make it clear that we are
printing both the decimal and hexadecimal SPR number.

Before:

Trying to read invalid spr 896 380 at 0000000000000714...
909eedb7 04/27/2013 01:37 am Aurelien Jarno

target-ppc: slightly optimize lfiwax

Signed-off-by: Aurelien Jarno <>
199f830d 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate lfiwax instruction

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
[agraf: fix tcg debug error]
Signed-off-by: Alexander Graf <>
05050ee8 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate load doubleword pair instructions

Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>
44bc0c4d 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate store doubleword pair instructions

Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>
7d08d856 04/27/2013 12:02 am Aurelien Jarno

target-ppc: add support for extended mtfsf/mtfsfi forms

Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a new
W field to select the upper part of the FPCSR register.

For that the helper is changed to handle 64-bit input values and mask with...
bf45a2e6 04/27/2013 12:02 am Aurelien Jarno

target-ppc: optimize fabs, fnabs, fneg

fabs, fnabs and fneg are just flipping the bit sign of an FP register,
this can be implemented in TCG instead of using softfloat.

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>
fcfda20f 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate cmpb instruction

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>
725bcec2 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate prtyw and prtyd instructions

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
[agraf: fix 32-bit host compile, simplify code]
Signed-off-by: Alexander Graf <>
f0332888 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate fcpsgn instruction

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>
8e7a6db9 04/27/2013 12:02 am Aurelien Jarno

target-ppc: fix nego and subf*o instructions

The overflow computation of nego and subf*o instructions has been broken
in commit ffe30937. Contrary to other targets, the instruction is subtract
from an not subtract on PowerPC.

This patch fixes the issue by using the correct argument in the xor...
752d634e 04/27/2013 12:02 am Richard Henderson

target-ppc: Fix narrow-mode add/sub carry output

Broken in b5a73f8d8a57e940f9bbeb399a9e47897522ee9a, the carry itself was
fixed in 79482e5ab38a05ca8869040b0d8b8f451f16ff62. But we still need to
produce the full 64-bit addition.

Simplify the conditions at the top of the functions for when we need a...
79482e5a 03/22/2013 04:28 pm Richard Henderson

target-ppc: Fix add and subf carry generation in narrow mode

The set of computations used in b5a73f8d8a57e940f9bbeb399a9e47897522ee9a
are only valid if the current word size == target_long size. This failed
to take ppc64 in 32-bit (narrow) mode into account....
e0c8f9ce 03/22/2013 04:28 pm Richard Henderson

target-ppc: Use NARROW_MODE macro for branches

Removing conditional compilation in the process.

Signed-off-by: Richard Henderson <>
Signed-off-by: Alexander Graf <>
02765534 03/22/2013 04:28 pm Richard Henderson

target-ppc: Use NARROW_MODE macro for comparisons

Removing conditional compilation in the process.

Signed-off-by: Richard Henderson <>
Signed-off-by: Alexander Graf <>
c791fe84 03/22/2013 04:28 pm Richard Henderson

target-ppc: Use NARROW_MODE macro for addresses

Removing conditional compilation in the process.

Signed-off-by: Richard Henderson <>
Signed-off-by: Alexander Graf <>
9ca3f7f3 03/22/2013 04:28 pm Richard Henderson

target-ppc: Use NARROW_MODE macro for tlbie

Removing conditional compilation in the process.

Signed-off-by: Richard Henderson <>
Signed-off-by: Alexander Graf <>
9baea4a3 03/22/2013 04:28 pm David Gibson

target-ppc: Remove vestigial PowerPC 620 support

The PowerPC 620 was the very first 64-bit PowerPC implementation, but
hardly anyone ever actually used the chips. qemu notionally supports the
620, but since we don't actually have code to implement the segment table,...
259186a7 03/12/2013 11:35 am Andreas Färber

cpu: Move halted and interrupt_request fields to CPUState

Both fields are used in VMState, thus need to be moved together.
Explicitly zero them on reset since they were located before
breakpoints.

Pass PowerPCCPU to kvmppc_handle_halt().

Signed-off-by: Andreas Färber <>
806f352d 03/03/2013 04:29 pm Peter Maydell

gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end

The gen_icount_start/end functions are now somewhat misnamed since they
are useful for generic "start/end of TB" code, used for more than just
icount. Rename them to gen_tb_start/end.

Signed-off-by: Peter Maydell <>...
08f4a0f7 02/25/2013 10:32 pm Richard Henderson

target-ppc: Fix SUBFE carry

While ~T0+T1+CF = T1-T0+CF-1 is true for the low 32-bits,
it does not produce the correct carry-out to bit 33. Do
exactly what the manual says.

Cc: Alexander Graf <>
Signed-off-by: Richard Henderson <>...
23ad1d5d 02/23/2013 07:25 pm Richard Henderson

target-ppc: Use mul*2 in mulh* insns

Cc: Alexander Graf <>
Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
da91a00f 02/23/2013 07:25 pm Richard Henderson

target-ppc: Split out SO, OV, CA fields from XER

In preparation for more efficient setting of these fields.

Cc: Alexander Graf <>
Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
2fdcb629 02/23/2013 07:25 pm Richard Henderson

target-ppc: Use setcond in gen_op_cmp

Which means that callers need not copy data into local tmps.

Cc: Alexander Graf <>
Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
ffe30937 02/23/2013 07:25 pm Richard Henderson

target-ppc: Compute addition overflow without branches

Cc: Alexander Graf <>
Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
146de60d 02/23/2013 07:25 pm Richard Henderson

target-ppc: Compute addition carry with setcond

Cc: Alexander Graf <>
Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
b5a73f8d 02/23/2013 07:25 pm Richard Henderson

target-ppc: Use add2 for carry generation

Cc: Alexander Graf <>
Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
fd3f0081 02/23/2013 07:25 pm Richard Henderson

target-ppc: Implement neg in terms of subf

Cc: Alexander Graf <>
Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
ba4af3e4 02/23/2013 07:25 pm Richard Henderson

target-ppc: Compute arithmetic shift carry without branches

Cc: Alexander Graf <>
Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
e4a2c846 02/23/2013 07:25 pm Richard Henderson

target-ppc: Compute mullwo without branches

Cc: Alexander Graf <>
Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
476b6d16 02/01/2013 02:52 am Andreas Färber

target-ppc: Fix build for PPC_DEBUG_DISAS

In r5949 / 76db3ba44ee8db671f804755f13b016eefd13288 (target-ppc: memory
load/store rework) variable little_endian was replaced with ctx.le_mode.
Update the debug code.

Signed-off-by: Andreas Färber <>...
8e33944f 02/01/2013 02:52 am Alexander Graf

PPC: Unify dcbzl code path

The bit that makes a dcbz instruction a dcbzl instruction was declared as
reserved in ppc32 ISAs. However, hardware simply ignores the bit, making
code valid if it simply invokes dcbzl instead of dcbz even on 750 and G4.

Thus, mark the bit as unreserved so that we properly emulate a simple dcbz...
1de7afc9 12/19/2012 09:32 am Paolo Bonzini

misc: move include files to include/qemu/

Signed-off-by: Paolo Bonzini <>
022c62cb 12/19/2012 09:31 am Paolo Bonzini

exec: move include files to include/exec/

Signed-off-by: Paolo Bonzini <>
76cad711 12/19/2012 09:29 am Paolo Bonzini

build: kill libdis, move disassemblers to disas/

Signed-off-by: Paolo Bonzini <>
ab1103de 12/08/2012 04:24 pm Evgeny Voevodin

TCG: Use gen_opc_instr_start from context instead of global variable.

Signed-off-by: Evgeny Voevodin <>
Signed-off-by: Blue Swirl <>
25983cad 12/08/2012 04:24 pm Evgeny Voevodin

TCG: Use gen_opc_pc from context instead of global variable.

Signed-off-by: Evgeny Voevodin <>
Signed-off-by: Blue Swirl <>
c9c99c22 12/08/2012 04:24 pm Evgeny Voevodin

TCG: Use gen_opc_icount from context instead of global variable.

Signed-off-by: Evgeny Voevodin <>
Signed-off-by: Blue Swirl <>
f0cc4aa8 11/26/2012 08:53 pm Julio Guerra

PPC: Fix missing TRACE exception

This patch fixes bug 1031698 :
https://bugs.launchpad.net/qemu/+bug/1031698

If we look at the (truncated) translation of the conditional branch
instruction in the test submitted in the bug post, the call to the
exception helper is missing in the "bne-false" chunk of translated...
92414b31 11/17/2012 03:53 pm Evgeny Voevodin

TCG: Use gen_opc_buf from context instead of global variable.

Signed-off-by: Evgeny Voevodin <>
Reviewed-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
efd7f486 11/17/2012 03:53 pm Evgeny Voevodin

TCG: Use gen_opc_ptr from context instead of global variable.

Signed-off-by: Evgeny Voevodin <>
Reviewed-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
f4359b9f 11/10/2012 03:49 pm Blue Swirl

disas: avoid using cpu_single_env

Pass around CPUArchState instead of using global cpu_single_env.

Signed-off-by: Blue Swirl <>
Acked-by: Richard Henderson <>
Acked-by: Aurelien Jarno <>
Acked-by: Guan Xuetao <>
30304420 11/01/2012 02:02 pm David Gibson

target-ppc: Extend FPU state for newer POWER CPUs

This patch adds some extra FPU state to CPUPPCState. Specifically,
fpscr is extended to a target_ulong bits, since some recent (64 bit)
CPUs now have more status bits than fit inside 32 bits. Also, we add...
fdefe51c 09/27/2012 10:38 pm Richard Henderson

Emit debug_insn for CPU_LOG_TB_OP_OPT as well.

For all targets that currently call tcg_gen_debug_insn_start,
add CPU_LOG_TB_OP_OPT to the condition that gates it.

This is useful for comparing optimization dumps, when the
pre-optimization dump is merely noise....
54cddd21 08/28/2012 07:49 pm Aurelien Jarno

target-ppc: fix altivec instructions

Altivec instructions are not working anymore in PowerPC emulation,
following commit d15f74fb, which inverted two registers in the call
to helper. Fix that.

Reviewed-by: Peter Maydell <>
Reviewed-by: Andreas Färber <>...
975e5463 06/24/2012 11:52 pm Stefan Weil

target-ppc: Fix build with --enable-debug

The order of the arguments was wrong (copy+paste error).

Signed-off-by: Stefan Weil <>
Signed-off-by: Alexander Graf <>
e42a61f1 06/24/2012 02:04 am Alexander Graf

PPC: Add support for MSR_CM

The BookE variant of MSR_SF is MSR_CM. Implement everything it takes in TCG to
support running 64bit code with MSR_CM set.

Signed-off-by: Alexander Graf <>
d0f1562d 06/24/2012 02:04 am Blue Swirl

ppc: Avoid AREG0 for timebase helpers

Add an explicit CPUPPCState parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>
Signed-off-by: Alexander Graf <>
d523dd00 06/24/2012 02:04 am Blue Swirl

ppc: Avoid AREG0 for misc helpers

Add an explicit CPUPPCState parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>
Signed-off-by: Alexander Graf <>
2f5a189c 06/24/2012 02:04 am Blue Swirl

ppc: Move load and store helpers, switch to AREG0 free mode

Add an explicit CPUPPCState parameter instead of relying on AREG0
and rename op_helper.c (which only contains load and store helpers)
to mem_helper.c. Remove AREG0 swapping in
tlb_fill().

Switch to AREG0 free mode. Use cpu_ld{l,uw}_code in translation...
c6c7cf05 06/24/2012 02:04 am Blue Swirl

ppc: Avoid AREG0 for MMU etc. helpers

Add an explicit CPUPPCState parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>
Signed-off-by: Alexander Graf <>
8e703949 06/24/2012 02:04 am Blue Swirl

ppc: Avoid AREG0 for FPU and SPE helpers

Add an explicit CPUPPCState parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>
Signed-off-by: Alexander Graf <>
d15f74fb 06/24/2012 02:04 am Blue Swirl

ppc: Avoid AREG0 for integer and vector helpers

Add an explicit CPUPPCState parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>...
e5f17ac6 06/24/2012 02:04 am Blue Swirl

ppc: Avoid AREG0 for exception helpers

Add an explicit CPUPPCState parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>
Signed-off-by: Alexander Graf <>
a1389542 04/15/2012 06:12 pm Andreas Färber

target-ppc: QOM'ify CPU reset

Move code from cpu_state_reset() into ppc_cpu_reset().
Reorder #include of helper_regs.h to use it in translate_init.c.

Adjust whitespace and add braces.

Signed-off-by: Andreas Färber <>
Acked-by: David Gibson <>
29979a8d 03/15/2012 02:12 pm Alexander Graf

PPC: KVM: Synchronize regs on CPU dump

When we dump the CPU registers, there's a certain chance they haven't been
synchronized with KVM yet, so we have to manually trigger that.

This aligns the code with x86 and fixes a bug where the register state was
bogus on invalid/unknown kvm exit reasons....
cd6e9320 03/15/2012 02:12 pm Thomas Huth

PPC64: Add support for ldbrx and stdbrx instructions

These instructions for loading and storing byte-swapped 64-bit values have
been introduced in PowerISA 2.06.

Signed-off-by: Thomas Huth <>
Signed-off-by: David Gibson <>...
1328c2bf 03/14/2012 11:20 pm Andreas Färber

target-ppc: Don't overuse CPUState

Scripted conversion:
sed -i "s/CPUState/CPUPPCState/g" target-ppc/*.[hc]
sed -i "s/#define CPUPPCState/#define CPUState/" target-ppc/cpu.h

Signed-off-by: Andreas Färber <>
Acked-by: Anthony Liguori <>
550a82ec 02/28/2012 11:33 pm Stefan Weil

target-ppc: Clean includes

Remove some include statements which are not needed.

Acked-by: Alexander Graf <>
Signed-off-by: Stefan Weil <>
9e0b5cb1 02/02/2012 03:47 am Alexander Graf

PPC: E500: Implement msgclr

This patch implements the msgclr instruction. It is part of the
Embedded.Processor Control specification and clears pending doorbell
interrupts on the current CPU.

Signed-off-by: Alexander Graf <>
d5d11a39 02/02/2012 03:47 am Alexander Graf

PPC: E500: Implement msgsnd

This patch implements the msgsnd instruction. It is part of the
Embedded.Processor Control specification and allows one CPU to
IPI another CPU without going through an interrupt controller.

Signed-off-by: Alexander Graf <>
6d3db821 02/02/2012 03:47 am Alexander Graf

PPC: booke206: Implement tlbilx

The PowerPC 2.06 BookE ISA defines an opcode called "tlbilx" which is used
to flush TLB entries. It's the recommended way of flushing in virtualized
environments.

So far we got away without implementing it, but Linux for e500mc uses this...
3f162d11 02/02/2012 03:47 am Alexander Graf

PPC: booke206: Check for TLB overrun

Our internal helpers to fetch TLB entries were not able to tell us
that an entry doesn't even exist. Pass an error out if we hit such
a case to not accidently pass beyond the TLB array.

Signed-off-by: Alexander Graf <>
53319166 02/02/2012 03:47 am Alexander Graf

PPC: e500: msync is 440 only, e500 has real sync

The e500 CPUs don't use 440's msync which falls on the same opcode IDs,
but instead use the real powerpc sync instruction. This is important,
since the invalid mask differs between the two.

Signed-off-by: Alexander Graf <>
dcb2b9e1 02/02/2012 03:47 am Alexander Graf

PPC: rename msync to msync_4xx

The msync instruction as defined today is only valid on 4xx cores, not
on e500 which also supports msync, but treats it the same way as sync.

Rename it to reflect that it's 4xx only.

Signed-off-by: Alexander Graf <>
ee2b3994 11/11/2011 06:33 pm Sebastian Bauer

PPC: Fix for the gdb single step problem on an rfi instruction

When using gdb to single step a ppc interrupt routine, the execution
flow passes the rfi instruction without actually returning from the
interrupt.

The patch fixes this by avoiding to update the nip when the debug...
70560da7 10/30/2011 06:11 pm Fabien Chouteau

Set an invalid-bits mask for each SPE instructions

SPE instructions are defined by pairs. Currently, the invalid-bits mask is set
for the first instruction, but the second one can have a different mask.

example:
GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),...
697ab892 10/06/2011 10:48 am David Gibson

Implement POWER7's CFAR in TCG

This patch implements support for the CFAR SPR on POWER7 (Come From
Address Register), which snapshots the PC value at the time of a branch or
an rfid. The latest powerpc-next kernel also catches it and can show it in
xmon or in the signal frames....
27a69bb0 08/23/2011 11:24 pm Alexander Graf

PPC: E500: Inject SPE exception on invalid SPE access

When accessing an SPE instruction despite it being not available,
throw an SPE exception instead of an APU exception. That way the
guest knows what's going on and actually uses SPE.

Reported-by: Jason Wessel <>...
3b886706 07/02/2011 12:12 am Blue Swirl

Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf

  • 'ppc-next' of git://repo.or.cz/qemu/agraf:
    PPC: move TLBs to their own arrays
    PPC: 440: Use 440 style MMU as default, so Qemu knows the MMU type
    PPC: E500: Use MAS registers instead of internal TLB representation...