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target-ppc: Make ppc40x CPUs available in ppcemb
Not only 44x CPUs (BookE) but also 40x CPUs can run with 1k page size.
Move the criteria to a central inline function to avoid repetitionand #ifdef'fery. Update qom-test to no longer exempt them.
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-ppc: move POWER7+ to a separate family
So far POWER7+ was a part of POWER7 family. However it has a differentPVR base value so in order to support PVR masks, it needs a separatefamily class.
This adds a new family class, PVR base and mask values and moves...
Add MSR VSX and Associated Exception
This patch adds support for the VSX bit of the PowerPC MachineState Register (MSR) as well as the corresponding VSX Unavailableexception.
The VSX bit is added to the defined bits masks of the Power7 andPower8 CPU models....
Declare and Enable VSX
This patch adds the flag POWERPC_FLAG_VSX to the list of definedflags and also adds this flag to the list of supported features ofthe Power7 and Power8 CPUs. Additionally, the VSX instructionsare added to the list of TCG-enabled instruction....
powerpc: add PVR mask support
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits anda CPU version in lower 16 bits. Since there is no significant changein behavior between versions, there is no point to add every single CPUversion in QEMU's CPU list. Also, new CPU versions of already supported...
target-ppc: dump-guest-memory support
This patch add support for dumping guest memory using dump-guest-memorymonitor command.
Before patch:
(qemu) dump-guest-memory testcrashthis feature or command is not currently supported(qemu)
After patch:
(qemu) dump-guest-memory testcrash...
target-ppc: Fill in OpenFirmware names for some PowerPCCPU families
Set the expected values for POWER7, POWER7+, POWER8 and POWER5+.Note that POWER5+ and POWER7+ are intentionally lacking the '+', so thelack of a POWER7P family constitutes no problem....
spapr: Use DeviceClass::fw_name for device tree CPU node
Instead of relying on cpu_model, obtain the device tree node labelper CPU. Use DeviceClass::fw_name as source.
Whenever DeviceClass::fw_name is unknown, default to "PowerPC,UNKNOWN".
As a consequence, spapr_fixup_cpu_dt() can operate on each CPU's fw_name,...
PPC: Fix L2CR write accesses
Commit 2345f1c01 was supposed to render L2CR writes into noops. Instead,it made them illegal instruction traps which apparently didn't confuseXNU, but can easily confuse other OSs.
Fix it up by actually doing nothing when we write to L2CR....
cpu: Drop cpu_model_str from CPU_COMMON
Since this is only read in cpu_copy() and linux-user has a globalcpu_model, drop the field from generic code.
target-ppc: POWER7 supports the MSR_LE bit
Add MSR_LE to the msr_mask for POWER7.
Signed-off-by: Anton Blanchard <anton@samba.org>Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>Signed-off-by: Alexander Graf <agraf@suse.de>
Convert stderr message calling error_get_pretty() to error_report()
Convert stderr messages calling error_get_pretty()to error_report().
Timestamp is prepended by -msg timstamp option with it.
Per Markus's comment below, A conversion from fprintf() to...
target-ppc: Prepare POWER5P CPU family
It is ISA 2.03. Modelled as 970FX minus AltiVec flag.
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>Cc: Alexey Kardashevskiy <aik@ozlabs.ru>Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-ppc: Suppress TCG instruction emulation warnings for qtest
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>Signed-off-by: Andreas Färber <afaerber@suse.de>Message-id: 1375106733-832-2-git-send-email-afaerber@suse.de...
Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging
QOM CPUState refactorings
target-ppc: Convert ppc cpu savevm to VMStateDescription
The savevm code for the powerpc cpu emulation is currently based aroundthe old register_savevm() rather than register_vmstate() method. It's alsorather broken, missing some important state on some CPU models....
cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"
Commit c643bed99 moved qemu_init_vcpu() calls to common CPUState code.This causes x86 cpu-add to fail with "KVM: setting VAPIC address failed".
The reason for the failure is that CPUClass::kvm_fd is not yet...
cpu: Introduce CPUClass::gdb_{read,write}_register()
Completes migration of target-specific code to new target-*/gdbstub.c.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Introduce CPUClass::gdb_core_xml_file for GDB_CORE_XML
Replace the GDB_CORE_XML define in gdbstub.c with a CPUClass field.Use first_cpu for qSupported and qXfer:features:read: for now.Add a stub for xml_builtin.
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
CPUState::gdb_num_regs replaces num_g_regs.CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS.
Allows building gdb_register_coprocessor() for xtensa, too.
As a side effect this should fix coprocessor register numbering for SMP....
cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
Change breakpoint_invalidate() argument to CPUState alongside.
Since all targets now assign a softmmu-only field, we can drop helperscpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd()....
gdbstub: Change gdb_register_coprocessor() argument to CPUState
cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()
This moves setting the Program Counter from gdbstub into target code.Use vaddr type as upper-bound replacement for target_ulong.
e600 core for MPC86xx processors
MPC86xx processors are based on the e600 core, which is not the casein qemu where it is based on the 7400 processor.
This patch creates the e600 core and instantiates the MPC86xxprocessors based on it. Therefore, adding the high BATs, the SPRG...
target-ppc: Add POWER8 v1.0 CPU model
This patch adds CPU PVR definition for POWER8,and enables QEMU to launch guests on POWER8 hardware.
Signed-off-by: Prerna Saxena
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Paul Mackerras <paulus@samba.org>...
log: Change log_cpu_state[_mask]() argument to CPUState
Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turncpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is nolonger needed.
Add documentation and make the functions available through qemu/log.h...
cpu: Move reset logging to CPUState
x86 was using additional CPU_DUMP_* flags, so make that configurable inCPUClass::reset_dump_flags.
This adds reset logging for alpha, unicore32 and xtensa.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Reviewed-by: Richard Henderson <rth@twiddle.net>...
PPC: Introduce an alias cache for faster lookups
When running QEMU with "-cpu ?" we walk through every alias for everytarget CPU we know about. This takes several seconds on my very fasthost system.
Let's introduce a class object cache in the alias table. Using that we...
PPC: Ignore writes to L2CR
The L2CR register contains a number of bits that either impose configurationwhich we can't deal with or mean "something is in progress until the bit is0 again".
Since we don't model the former and we do want to accomodate guests using the...
target-ppc: Introduce unrealizefn for PowerPCCPU
Use it to clean up the opcode table, resolving a former TODO from Jocelyn.Also switch from malloc() to g_malloc().
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Drop redundant flags assignments from CPU families
Previous code has #define POWERPC_INSNS2_<family> PPC_NONE in someplaces for macrofied assignment to insns_flags2 field.
PPC_NONE is defined as zero though and QOM classes are zero-initialized,...
ppc: do not register IABR SPR twice for 603e
IABR SPR is already registered in gen_spr_603(), called from init_proc_603E().
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
cpu: Change qemu_init_vcpu() argument to CPUState
This allows to move the call into CPUState's realizefn.Therefore move the stub into libqemustub.a.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
target-ppc: Add read and write of PPR SPR
Recent Linux kernels save and restore the PPR across exceptionsso we need to handle it.
Signed-off-by: Anton Blanchard <anton@au1.ibm.com>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: add instruction flags for Book I 2.05
.. and enable it on POWER7 CPU.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
pseries: Fixes and enhancements to L1 cache properties
PAPR requires that the device tree's CPU nodes have several propertieswith information about the L1 cache. We already create two of theseproperties, but with incorrect names - "[id]cache-block-size" instead...
target-ppc: Add more stubs for POWER7 PMU registers
In addition to the performance monitor registers found on nearly all6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and anextra control register (MMCRA). This patch adds stub support for them to...
PPC: Remove env->hreset_excp_prefix
This value is not needed if we use correctly the MSR[IP] bit.
excp_prefix is always 0x00000000, except when the MSR[IP] bit isimplemented and set to 1, in that case excp_prefix is 0xfff00000.
The handling of MSR[IP] was already implemented but not used at reset...
PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
According to the different user's manuals, the vector offset for systemreset (both /HRESET and /SRESET) is 0x00100.
This patch may break support of some executables, as the power-on start...
PPC: Add breakpoint registers for 603 and e300
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Enable ISEL on POWER7
ISEL is a Power ISA 2.06 instruction and thus is available on POWER7.Given this is trapped and emulated by the Linux kernel, I guess it wentunnoticed.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
mmu-hash64: Implement Virtual Page Class Key Protection
Version 2.06 of the Power architecture describes an additional pageprotection mechanism. Each virtual page has a "class" (0-31) recorded inthe PTE. The AMR register contains bits which can prohibit reads and/or...
target-ppc: Use QOM method dispatch for MMU fault handling
After previous cleanups, the many scattered checks of env->mmu_model inthe ppc MMU implementation have, at least for "classic" hash MMUs beenreduced (almost) to a single switch at the top ofcpu_ppc_handle_mmu_fault()....
PPC/GDB: handle read and write of fpscr
Although the support of this register may be uncomplete, there are noreason to prevent the debugger from reading or writing it.
target-ppc: Remove vestigial PowerPC 620 support
The PowerPC 620 was the very first 64-bit PowerPC implementation, buthardly anyone ever actually used the chips. qemu notionally supports the620, but since we don't actually have code to implement the segment table,...
cpu: Replace do_interrupt() by CPUClass::do_interrupt method
This removes a global per-target function and thus takes us one stepcloser to compiling multiple targets into one executable.
It will also allow to override the interrupt handling for certain CPU...
target-ppc: Fix PPC_DUMP_SPR_ACCESS build
A victim of the d523dd00a7d73b28f2e99acf45a4b3f92e56e40a AREG0conversion, insert the missing cpu_env arguments.
target-ppc: Make host CPU a subclass of the host's CPU model
This avoids assigning individual class fields and contributorsforgetting to add field assignments in KVM-only code.
ppc_cpu_class_find_by_pvr() requires the CPU model classes to beregistered, so defer host CPU type registration to kvm_arch_init()....
target-ppc: List alias names alongside CPU models
Revert adding a separate -cpu ? output section for aliases and list themper CPU subclass.
Requested-by: Alexander Graf <agraf@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Report CPU aliases for QMP
The QMP query-cpu-definitions implementation iterated over CPU classesonly, which were getting less and less as aliases were extracted.
Keep them in QMP as valid -cpu arguments even if not guaranteed stable.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-ppc: Move CPU aliases out of translate_init.c
Move array of CPU aliases to cpu-models.c, alongside model definitions.This requires to zero-terminate the aliases array since ARRAY_SIZE() canno longer be used in translate_init.c then.
Suggested-by: Alexander Graf <agraf@suse.de>...
target-ppc: Turn descriptive CPU model comments into device descriptions
Fix microcontroller typo while at it.
target-ppc: Update Coding Style for CPU models
Drop the space in #if defined (TODO).
target-ppc: Split model definitions out of translate_init.c
Now that model definitions only reference their parent type, modeldefinitions are independent of the family definitions and can becompiled independently of TCG translation.
Keep all #if defined(TODO) code local to cpu-models.c....
target-ppc: Change "POWER7" CPU alias
Let it resolve to v2.3 rather than v2.0.
Suggested-by: David Gibson <david@gibson.dropbear.id.au>Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Add mechanism for synchronizing SPRs with KVM
Currently when runing under KVM on ppc, we synchronize a certain number ofvital SPRs to KVM through the SET_SREGS call. This leaves out quite a lotof important SPRs which are maintained in KVM. It would be helpful to...
target-ppc: Convert CPU definitions
Turn the array of model definitions into a set of self-registering QOMtypes with their own class_init. Unique identifiers are obtained fromthe combination of PVR, SVR and family identifiers; this requires allalias #defines to be removed from the list. Possibly there are some more...
target-ppc: Introduce abstract CPU family types
Instead of assigning *_<family> constants, set .parent to a family type.
Introduce a POWERPC_FAMILY() macro to keep type registration close toits implementation. This macro will need tweaking later.
target-ppc: Set instruction flags on CPU family classes
target-ppc: Register all types for TARGET_PPCEMB
Don't attempt to suppress registration of CPU types, since the criteriais actually a property of the class and should thus become a field.Since we can't check a field set in a class_init function beforeregistering the type that leads to execution of that function, guard the...
target-ppc: Set remaining fields on CPU family classes
Now POWERPC_DEF_SVR() no longer sets family-specific fields itself.
target-ppc: Turn descriptive CPU family comments into device descriptions
This gets rid of some more overly long comments that have lost most oftheir purpose now that in most cases there's only two functions left perCPU family.
The class field is inherited by the actual CPU models, so override it....
target-ppc: Extract 970 aliases
target-ppc: Extract POWER7 alias
target-ppc: Get model name from type name
We are about to drop the redundant name field along with ppc_def_t.
target-ppc: Extract MPC82xx_HiP{3, 4} aliases
target-ppc: Extract MPC52xx alias
target-ppc: Extract MPC5200/MPC5200B aliases
target-ppc: Extract MPC8240 alias
target-ppc: Extract 405GPe alias
target-ppc: Extract 604e alias
target-ppc: Extract MPC85xx aliases
target-ppc: Extract e500v1/e500v2 aliases
target-ppc: Extract MPC83xx aliases
target-ppc: Extract e300 alias
target-ppc: Extract e200 alias
target-ppc: Extract MPC82xx alias
target-ppc: Extract MPC8247/MPC8248/MPC8270-80 aliases
This depends on the fix for "G2leGP3" PVR.
target-ppc: Extract MPC82xx aliases to *_HiP4
target-ppc: Extract 7410 alias
target-ppc: Extract 7400 alias
target-ppc: Extract 7x5 aliases
target-ppc: Extract 750 aliases
target-ppc: Extract 740/750 aliases
target-ppc: Extract 603e alias
target-ppc: Extract 603r alias
target-ppc: Extract 601/601v aliases
target-ppc: Extract MGT823/MPC8xx as aliases
They used different PVRs but were defined to MPC8xx.
target-ppc: Extract 40x aliases
target-ppc: Extract 440 aliases
target-ppc: Turn "ppc32" and "ppc64" CPUs into aliases
target-ppc: Extract 74x7[A] aliases
target-ppc: Extract 74x5 as aliases
target-ppc: Extract 74x1 aliases
target-ppc: Extract 7450 alias
target-ppc: Extract 7448 alias
target-ppc: Extract aliases from definitions list
Move definitions that were 100% identical except for the name into alist of aliases so that we don't register duplicate CPU types.Drop the accompanying comments since they don't really add value.
We need to support recursive lookup due to code names referencing a...
target-ppc: Make -cpu "ppc" an alias to "ppc32"
Drop the #if 0'ed alternative to make it "ppc64" for TARGET_PPC64.If we ever want to change it, we can more easily do so now.
target-ppc: Extract MPC5xx aliases
Their PVR differed but was defined to MPC5xx.