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exec: move include files to include/exec/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target-sh4: rename helper flags
Rename helper flags to the new ones. This is purely a mechanical change,it's possible to use better flags by looking at the helpers.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-sh4: implement addv and subv using TCG
addv and subv helpers implementation is directly copied from the SH4manual and looks quite complex. It is however possible to explain itwithout branches, and is therefore possible to implement it with TCG....
target-sh4: rework exceptions handling
Since commit fd4bab102 PC is restored in case of exception through coderetranslation. While it is clearly the thing to do in case it is notnot known if an helper is going to trigger an exception or not(e.g. for load/store, FPU, etc.), it just make things slower when the...
target-sh4: mark a few helpers const and pure
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-sh4: implement addc and subc using TCG
Now that setcond is available, the addc and subc can easily beimplemented using TCG.
target-sh4: switch to AREG0 free mode
Add an explicit CPUState parameter instead of relying on AREG0and switch to AREG0 free mode.
Acked-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sh4: get rid of CPU_{Float,Double}U
SH4 is always using softfloat, so it's possible to have helpers directlytaking float32 or float64 value. This allow to get rid of conversionsthrough CPU_{Float,Double}U.
target-sh4: implement negc using TCG
Using setcond it's now possible to generate a relatively short negcinstruction in TCG.
target-sh4: add fipr instruction
Add the fipr FVm,FVn instruction, which computes the inner products ofa 4-dimensional single precision floating-point vector.
target-sh4: add ftrv instruction
Add the ftrv XMTRX,FVn instruction, which computes the 4-row x 4-columnmatrix XMTRX by the 4-dimensional vector FVn.
SH: Improve movca.l/ocbi emulation.
Author: Vladimir Prus <vladimir@codesourcery.com>
Fix movcal.l/ocbi emulation.
sh4: Add FMAC instruction support
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Lionel Landwerlin <lionel.landwerlin@openwide.fr>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6309 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Implement FD bit
SH4 manual say that if a floating point instruction is executed whileFD bit in the status register is 1, an exception should be raised. QEMUpresently does not do that, so the kernel does not initialize FP statefor any thread, nor does it save/restore FP state. The most apparent...
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: sleep instruction bug fix
fix a bug on 'sleep' instruction, which have caused halt of idle task.As i386 'hlt' instruction does, it should save PC before sleep.
(Shin-ichiro KAWASAKI)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5220 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: final conversion to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5125 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert floating-point ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5124 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Convert remaining non-fp ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5120 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert control/status register load/store to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5118 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert some more arithmetics ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5116 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: convert a few helpers to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5112 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: add support for TCG helpers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5096 c046a42c-6fe2-441c-8c8c-71466251a162