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target-sh4: Use new qemu_ld/st opcodes
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Move helper registration into tcg_context_init
No longer needs to be done on a per-target basis.
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg: Change tcg_gen_exit_tb argument to uintptr_t
And update all users.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Prepares for changing cpu_single_step() argument to CPUState.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Signed-off-by: Andreas Färber <afaerber@suse.de>
target-sh4: Change gen_intermediate_code_internal() argument to SuperHCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-sh4: Introduce SuperHCPU subclasses
Store legacy name in SuperHCPUClass for -cpu ? and for case-insensitiveclass lookup.
List CPUs by iterating over TYPE_SUPERH_CPU subclasses.
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since theyare useful for generic "start/end of TB" code, used for more than justicount. Rename them to gen_tb_start/end.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-sh4: Use mul*2 for dmul*
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sh4: Move TCG initialization to SuperHCPU initfn
Add a tcg_enabled() check to suppress it for qtest.
target-sh4: Introduce QOM realizefn for SuperHCPU
Introduce a realizefn and set realized = true in cpu_sh4_init().
exec: move include files to include/exec/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
build: kill libdis, move disassemblers to disas/
TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_pc from context instead of global variable.
TCG: Use gen_opc_icount from context instead of global variable.
TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
disas: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Richard Henderson <rth@twiddle.net>Acked-by: Aurelien Jarno <aurelien@aurel32.net>Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when thepre-optimization dump is merely noise....
target-sh4: implement addv and subv using TCG
addv and subv helpers implementation is directly copied from the SH4manual and looks quite complex. It is however possible to explain itwithout branches, and is therefore possible to implement it with TCG....
target-sh4: optimize xtrct
The register being 32 bit long, after a shift to the right by 16 bits,the upper 16 bit are already cleared. There is no need to call ext16uto clear them.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-sh4: optimize swap.w
It's possible swap the two 16-bit words of a 32-bit register using arotation. If the TCG target doesn't implement rotation, the replacementcode is similar to the previously implemented code.
target-sh4: remove gen_clr_t() and gen_set_t()
gen_clr_t() and gen_set_t() have very few callers and can be remplacedby a single line. Remove them.
target-sh4: rework exceptions handling
Since commit fd4bab102 PC is restored in case of exception through coderetranslation. While it is clearly the thing to do in case it is notnot known if an helper is going to trigger an exception or not(e.g. for load/store, FPU, etc.), it just make things slower when the...
target-sh4: cleanup DisasContext
We should avoid accessing env at translation stage, except of course forstatic values like the supported features.
Remove variables copied from env in DisasContext and use the TB flagsinstead.
target-sh4: remove useless code
Almost dead code.
target-sh4: implement addc and subc using TCG
Now that setcond is available, the addc and subc can easily beimplemented using TCG.
target-sh4: switch to AREG0 free mode
Add an explicit CPUState parameter instead of relying on AREG0and switch to AREG0 free mode.
Acked-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Kill off cpu_state_reset()
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset()was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()that would operate on QOM objects.
All callers have been updated except for one in target-mips, so drop all...
target-sh4: Let cpu_sh4_init() return SuperHCPU
Turn cpu_init macro into a static inline function returningCPUSH4State for backwards compatibility.
target-sh4: QOM'ify CPU
Embed CPUSH4State as first member of SuperHCPU.
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
target-sh4: QOM'ify CPU reset
Move code from cpu_state_reset() to QOM superh_cpu_reset().
target-sh4: Start QOM'ifying CPU init
Move code from cpu_sh4_init() into a QOM initfn.
target-sh4: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUSH4State/g" target-sh4/*.[hc] sed -i "s/#define CPUSH4State/#define CPUState/" target-sh4/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).
Don't hide the parameter type behind explicit casts, use staticfunctions with strongly typed argument to indirect.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-sh4: Clean includes
Remove some include statements which are not needed.
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <sw@weilnetz.de>
target-sh4: ignore ocbp and ocbwb instructions
ocbp and ocbwb controls the writeback of a cache line to memory. Theyare supposed to do nothing in case of a cache miss. Given QEMU onlypartially emulate caches, it is safe to ignore these instructions.
This fixes a kernel oops when trying to access an rtl8139 NIC with...
target-sh4: Fix operands for fipr, ftrv instructions
Coverity complained about right shifts of opcode (16, 18) which werelarger than the size of opcode (16 bit).
Using the correct shift values fixes this.
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <sw@weilnetz.de>...
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
target-sh4: fix negc
target-sh4: use rotl/rotr when possible
target-sh4: implement negc using TCG
Using setcond it's now possible to generate a relatively short negcinstruction in TCG.
target-sh4: define FPSCR constants
Define FPSCR constants for all field and use them instead of hardcodedvalues.
target-sh4: implement flush-to-zero
When the FPSCR.DN bit is set, the SH4 FPU treat denormalized numbers aszero. Enable the corresponding softfloat option when this bit is set.
target-sh4: add fipr instruction
Add the fipr FVm,FVn instruction, which computes the inner products ofa 4-dimensional single precision floating-point vector.
target-sh4: add ftrv instruction
Add the ftrv XMTRX,FVn instruction, which computes the 4-row x 4-columnmatrix XMTRX by the 4-dimensional vector FVn.
target-sh4: optimize exceptions
As exception is not the normal path, don't bother saving PC, beforeraising one, instead rely on code retranslation to get the CPU state.
target-sh4: fix reset on r2d
target-sh4: simplify comparisons after a 'and' op
When a TCG variable is anded with a value and the compared with the samevalue, we can simply invert the comparison and compare it with 0. Thegenerated code is smaller.
target-sh4: log instructions start in TCG code
target-sh4: use setcond when possible
target-sh4: use default-NaN mode
SH4 FPU doesn't propagate NaN, and instead always regenerate new ones.Enable the default-NaN mode by default.
target-sh4: fix fpu disabled/illegal exception
Illegal instructions in a slot delay should generate a slot illegalinstruction exception instead of an illegal instruction exception.
The current PC should be saved before generating such an exception,but should not be corrected if in a delay slot, given it's already...
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
target-sh4: Add support for ldc & stc with sgr
Add support for the following missing priviledged intructions:
For SH4:- stc sgr, Rn- stc.l sgr, @-Rn
For SH4A:- ldc Rm, sgr- ldc.l @Rm+, sgr
Signed-off-by: Alexandre Courbot <gnurou@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-sh4: Split the LDST macro into 2 sub-macros
The LDST macro is used to generate ldc and stc instructions that work with aspecific register. However, the SGR register only supports stc up to SH4A,which supports both stc and ldc. This patch creates two sub-macros named LD...
target-sh4: Remove duplicate CPU log.
Logging for -d cpu is done in generic code.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
remove TARGET_* defines from translate-all.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-sh4: MMU: fix mem_idx computation
The mem_idx is wrongly computed. As written in target-sh4/cpu.h, mode 0corresponds to kernel mode (SR_MD = 1), while mode 1 corresponds to usermode (SR_MD = 0).
target-sh4: minor optimisations
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
Update to a hopefully more future proof FSF address
Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.cpu-all.h still need to include it because of the dyngen-exec.h hacks
Signed-off-by: Paul Brook <paul@codesourcery.com>
qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
Add new command line option -singlestep for tcg single stepping.
This replaces a compile time option for some targets and addsthis feature to targets which did not have a compile time option.
Add monitor command to enable or disable single step mode.
Modify monitor command "info status" to display single step mode....
SH: Improve movca.l/ocbi emulation.
Author: Vladimir Prus <vladimir@codesourcery.com>
Fix movcal.l/ocbi emulation.
SH: Implement MOVCO.L and MOVLI.L
(Vladimir Prus)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6666 c046a42c-6fe2-441c-8c8c-71466251a162
SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6548 c046a42c-6fe2-441c-8c8c-71466251a162
targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
Log reset events (Jan Kiszka)
Original idea&code by Kevin Wolf, split-up in two patches and added morearchs.
This patch introduces a flag to log CPU resets. Useful for tracingunexpected resets (such as those triggered by x86 triple faults).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &X) qemu_log()' statement.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
sh4: Add FMAC instruction support
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Lionel Landwerlin <lionel.landwerlin@openwide.fr>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6309 c046a42c-6fe2-441c-8c8c-71466251a162
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
tcg_temp_local_new should take no parameter
This patch removes useless type information in some calls totcg_temp_local_new. It also removes the parameter from themacro declaration; if a target has to use a specific non-defaultsize then it should use tcg_temp_local_new_{i32,i64}....
Use the ARRAY_SIZE() macro where appropriate.
Change from v1: Avoid changing the existing coding style in certain files.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: make the initial value of SR easier to read
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6016 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: don't disable FPU instructions in user mode
Based on a patch from Lionel Landwerlin.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6015 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: disable debug code
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6014 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: add prefi, icbi, synco
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6013 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: add SH7785 as CPU option
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6012 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: check FD bit for FP instructions
Based on a patch from Vladimir Prus <vladimir@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5970 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: kill a few warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5938 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Implement FD bit
SH4 manual say that if a floating point instruction is executed whileFD bit in the status register is 1, an exception should be raised. QEMUpresently does not do that, so the kernel does not initialize FP statefor any thread, nor does it save/restore FP state. The most apparent...
Use sys-queue.h for break/watchpoint managment (Jan Kiszka)
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying thecode and also fixing a use after release issue incpu_break/watchpoint_remove_all.
target-sh4: fix 64-bit fmov to/from memory
When loading/storing a register pair, the even-numbered registeralways maps to the low 32 bits of memory independently of targetendian configuration.
Signed-off-by: Mans Rullgard <mans@mansr.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-sh4: fix fldi0/fldi1
fldi0/fldi1 should be executed as a nop if FPSCR.FR is set instead ofgenerating an exception. Reported by Laurent Desnogues.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5759 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: map FP registers as TCG variables
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5758 c046a42c-6fe2-441c-8c8c-71466251a162
Refactor and enhance break/watchpoint API (Jan Kiszka)
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow thesucceeding enhancements this series comes with.
First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switchingto dynamically allocated data structures that are kept in linked lists....
TCG variable type checking.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
Fix undeclared symbol warnings from sparse
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5539 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Implement MOVUA.L
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5473 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: fix single-stepping
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5472 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Fix swap.b
The SH4 manual documents the swap.b instruction as follows:
SWAP.B Rm,Rn Rm → swap lower 2 bytes → Rn
Current QEMU code, in addition to the above, also clears the high16 bits. The immediate breakage I saw is that htonl function applied...
Silence some warnings about no value returned from non-void function
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5430 c046a42c-6fe2-441c-8c8c-71466251a162
Add concat_i32_i64 op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162