Statistics
| Branch: | Revision:

root / target-xtensa / overlay_tool.h @ feature-archipelago

History | View | Annotate | Download (17.7 kB)

# Date Author Comment
676056d4 02/24/2014 02:47 am Max Filippov

target-xtensa: refactor standard core configuration

Coalesce all standard configuration sections into single
DEFAULT_SECTIONS macro for all cores. This allows to add new features in
a single place: overlay_tool.h

Signed-off-by: Max Filippov <>
604e1f9c 02/24/2014 02:47 am Max Filippov

target-xtensa: provide HW confg ID registers

Signed-off-by: Max Filippov <>
fcc803d1 12/08/2012 08:48 pm Max Filippov

target-xtensa: implement ATOMCTL SR

ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory
type. See ISA, 4.3.12.4 for details.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
4e41d2f5 12/08/2012 08:48 pm Max Filippov

target-xtensa: implement CACHEATTR SR

In XEA1, the Options for Memory Protection and Translation and the
corresponding TLB management instructions are not available. Instead,
functionality similar to the Region Protection Option is available
through the cache attribute register. See ISA, A.2.14 for details....
fe0bd475 12/08/2012 08:48 pm Max Filippov

target-xtensa: restrict available SRs by enabled options

Beginning with the RA-2004.1 release, SR access instructions (rsr, wsr,
xsr) are associated with their corresponding SR and raise illegal opcode
exception in case the register is not configured for the core....
b7909d81 12/08/2012 08:48 pm Max Filippov

target-xtensa: implement MISC SR

The Miscellaneous Special Registers Option provides zero to four scratch
registers within the processor readable and writable by RSR, WSR, and
XSR. These registers are privileged. They may be useful for some
application-specific exception and interrupt processing tasks in the...
10f6ca03 09/22/2012 08:59 pm Max Filippov

target-xtensa: handle boolean option in overlays

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
18da9326 02/20/2012 06:07 pm Max Filippov

target-xtensa: add DEBUG_SECTION to overlay tool

Fill debug configuration from overlay definitions in the DEBUG_SECTION.
Add DEBUG_SECTION to DC232B and FSF cores.

Signed-off-by: Max Filippov <>
b96ac3e4 02/17/2012 11:25 pm Max Filippov

target-xtensa: define TLB_TEMPLATE for MMU-less cores

TLB_TEMPLATE macro specifies TLB geometry in the core configuration.
Make TLB_TEMPLATE available for region protection core variants,
defining 1 way ITLB and DTLB with 8 entries each.

Signed-off-by: Max Filippov <>
0fdd2e1d 11/26/2011 11:44 am Max Filippov

target-xtensa: fix MMUv3 initialization

- ITLB/DTLB ways 5 and 6 have 4 and 8 entries respectively;
- ITLB/DTLB way 6 attr field is set to 3 on reset.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
0c852e17 11/02/2011 03:05 am Max Filippov

target-xtensa: handle cache options in the overlay tool

Cache options must be enabled for the cores that have cache to avoid
illegal instruction exceptions.

Signed-off-by: Max Filippov <>
ac8b7db4 10/16/2011 01:39 pm Max Filippov

target-xtensa: extract core configuration from overlay

Introduce overlay_tool.h that defines core configuration blocks from
data available in the linux architecture variant overlay.

Overlay data is automatically generated in the core configuration
process by Tensilica tools and can be directly converted to qemu xtensa...