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tcg: Add qemu_ld_st_i32/64
Step two in the transition, adding the new ldst opcodes. Keep the oldopcodes around until all backends support the new opcodes.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Use proper term in TCG README
In TCG, "target" means the host architecture for which TCG generatesthe code. Using "guest" rather than "target" to make the document moreconsistent.
Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
tcg: Add 64-bit multiword arithmetic operations
Matching the 32-bit multiword arithmetic that we already have.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg: Add signed multiword multiplication operations
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg: rework TCG helper flags
The current helper flags, TCG_CALL_CONST and TCG_CALL_PURE might beconfusing and doesn't provide enough granularity for some helpers (FPhelpers for example).
This patch changes them into the following helpers flags:- TCG_CALL_NO_READ_GLOBALS means that the helper does not read globals,...
tcg: forbid ld/st function to modify globals
Mapping a memory address using a global and accessing it throughld/st operations is currently broken. As it doesn't make any senseto do that performance wise, let's forbid that.
Update the TCG documentation, and remove partial support for that....
tcg: remove obsolete jmp op
The TCG jmp operation doesn't really make sense in the QEMU context, itis unused, it is not implemented by some targets, and it is wronglyimplemented by some others.
This patch simply removes it.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
tcg: Adjust descriptions of *cond opcodes
The README file documented the operand ordering of the tcg_gen_*functions. Since we're documenting opcodes here, use the trueoperand ordering.
Signed-off-by: Richard Henderson <rth@twiddle.net>Cc: malc <av1474@comtv.ru>...
tcg/README: document tcg_gen_goto_tb restrictions
Seehttp://lists.nongnu.org/archive/html/qemu-devel/2012-09/msg03196.htmlfor the whole story.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Introduce movcond
Implemented with setcond if the target does not providethe optional opcode.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/README: Expand advice on number of TCG ops per target insn
Expand the note on the number of TCG ops generated per target insn,to be clearer about the range of applicability of the 20 op ruleof thumb. Also add a note about the hard MAX_OP_PER_INSTR limit....
tcg: README, name deposit second argument len/LEN
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
tcg: Define "deposit" as an optional operation.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
tcg: fix typo in readme
Signed-off-by: Mike Frysinger <vapier@gentoo.org>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg/README: Spelling fixes
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg/README: improve description of bswap*
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operandssign-extended in 64-bit registers (regardless of the "real" signof the operand). For that, we need to be able to distinguishbetween a 32-bit load with a 32-bit result and a 32-bit load with...
tcg: Allow target-specific implementation of EQV.
tcg: update README with const and pure helpers
tcg: document double-word support opcodes.
The internal opcodes brcond2, add2, sub2, mulu2 were undocumented.Place these in a new section that clearly indicates that they arenot to be emitted by translators.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
tcg: generic support for conditional set
Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit.
tcg/README: fix description of bswap32_i32/i64
Thanks to Stuart Brady for the notice.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6920 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: update README wrt recent bswap changes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6834 c046a42c-6fe2-441c-8c8c-71466251a162
TCG: Fix documentation of qemu_ld/st ops
The functions defined in tcg/tcg-op.h have no _i32 or _i64 suffix,qemu_ld64 and qemu_st64 were missing from the list, and there areno 'plain' qemu_ld/qemu_st ops.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>...
Remove a few dyngen and dyngen related code
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5914 c046a42c-6fe2-441c-8c8c-71466251a162
Mention output overlaps.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5619 c046a42c-6fe2-441c-8c8c-71466251a162
tcg-ops.h: add rotl/rotli and rotr/rotri TCG instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5607 c046a42c-6fe2-441c-8c8c-71466251a162
TCG: add logical operations found on alpha and powerpc processors
- andc_i32/i64 t0, t1, t2- eqv_i32/i64 t0, t1, t2- nand_i32/i64 t0, t1, t2- nor_i32/i64 t0, t1, t2- orc_i32/i64 t0, t1, t2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5501 c046a42c-6fe2-441c-8c8c-71466251a162
Add concat32_i64 and concat_tl_i64 ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5282 c046a42c-6fe2-441c-8c8c-71466251a162
Add concat_i32_i64 op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
update
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4581 c046a42c-6fe2-441c-8c8c-71466251a162
ARM host support for TCG targets.
Updated from previous version to use the tcg prologue/epilogue mechanism, may be slower than direct call.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4500 c046a42c-6fe2-441c-8c8c-71466251a162
Add TCG native negation op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4426 c046a42c-6fe2-441c-8c8c-71466251a162
Add zero extension (pseudo-)ops.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4424 c046a42c-6fe2-441c-8c8c-71466251a162
TCG README fixes (Stuart Brady)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4042 c046a42c-6fe2-441c-8c8c-71466251a162
fixed sign extensions - added explicit side effect op flag - added discard instruction
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3963 c046a42c-6fe2-441c-8c8c-71466251a162
typos
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3945 c046a42c-6fe2-441c-8c8c-71466251a162
TCG code generator
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3943 c046a42c-6fe2-441c-8c8c-71466251a162