Statistics
| Branch: | Revision:

root / target-arm @ feature-archipelago

Name Size
Makefile.objs 465 Bytes
arm-semi.c 17.2 kB
cpu-qom.h 6.2 kB
cpu.c 32.6 kB
cpu.h 43.6 kB
cpu64.c 3.6 kB
crypto_helper.c 13 kB
gdbstub.c 2.8 kB
gdbstub64.c 1.9 kB
helper-a64.c 7.5 kB
helper-a64.h 2 kB
helper.c 158.8 kB
helper.h 19.1 kB
iwmmxt_helper.c 24.8 kB
kvm-consts.h 4.4 kB
kvm-stub.c 437 Bytes
kvm.c 10.4 kB
kvm32.c 15.7 kB
kvm64.c 5.2 kB
kvm_arm.h 4.2 kB
machine.c 7.9 kB
neon_helper.c 53.2 kB
op_addsub.h 1.8 kB
op_helper.c 9.8 kB
translate-a64.c 284.3 kB
translate.c 380.3 kB
translate.h 1.9 kB

Latest revisions

# Date Author Comment
1f79ee32 02/26/2014 07:20 pm Peter Maydell

target-arm: Add utility function for checking AA32/64 state of an EL

There are various situations where we need to behave differently
depending on whether a given exception level is in AArch64 or
AArch32 state. The state of the current exception level is stored...

eb0ecd5a 02/26/2014 07:20 pm Will Newton

target-arm: Add support for AArch32 ARMv8 CRC32 instructions

Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8
and add a CPU feature flag to enable these instructions.

The CRC32-C implementation used is the built-in qemu implementation...

1ed69e82 02/26/2014 07:20 pm Peter Maydell

target-arm: A64: Implement WFI

Implement the WFI instruction for A64; this just involves wiring
up the instruction, and adding a gen_a64_set_pc_im() which was
accidentally omitted from the A64 decoder top loop.

Signed-off-by: Peter Maydell <>...

4cc35614 02/26/2014 07:20 pm Peter Maydell

target-arm: Store AIF bits in env->pstate for AArch32

To avoid complication in code that otherwise would not need to
care about whether EL1 is AArch32 or AArch64, we should store
the interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIF
in AArch64) in one place consistently regardless of EL1's mode....

9cfa0b4e 02/26/2014 07:20 pm Peter Maydell

target-arm: A64: Implement MSR (immediate) instructions

Implement the MSR (immediate) instructions, which can update the
PSTATE SP and DAIF fields.

Signed-off-by: Peter Maydell <>
Reviewed-by: Peter Crosthwaite <>

34222fb8 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 view of CPACR

Implement the AArch64 view of the CPACR. The AArch64
CPACR is defined to have a lot of RES0 bits, but since
the architecture defines that RES0 bits may be implemented
as reads-as-written and we know that a v8 CPU will have...

e60cef86 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 ID and feature registers

Implement the AArch64-specific ID and feature registers. Although
many of these are currently not used by the architecture (and so
always zero for all implementations), we define the full set of
fields in the ARMCPU struct for symmetry....

0b45451e 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 dummy breakpoint and watchpoint registers

In AArch64 the breakpoint and watchpoint registers are mandatory, so the
kernel always accesses them on bootup. Implement dummy versions, which
read as written but have no actual effect....

cd5c11b8 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI

Define a dummy version of the AArch64 OSLAR_EL1 system register
which just ignores writes. Linux will always write to this (it
is the OS lock used for debugging), but we don't support debug.

Signed-off-by: Peter Maydell <>...

d9ea7d29 02/26/2014 07:20 pm Peter Maydell

target-arm: Get MMU index information correct for A64 code

Emit the correct MMU index information for loads and stores from
A64 code, rather than hardwiring it to "always kernel mode",
by storing the exception level in the TB flags, and make
cpu_mmu_index() return the right answer when the CPU is in...

View revisions

Also available in: Atom