Revision ff2712ba

b/cpu-exec.c
569 569 
                        next_tb = 0;
570 570 
                    }
571 571 
#endif
572 
                   /* Don't use the cached interupt_request value,
572 
                   /* Don't use the cached interrupt_request value,
573 573 
                      do_interrupt may have updated the EXITTB flag. */
574 574 
                    if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
575 575 
                        env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
b/hw/mst_fpga.c
154 154 
	case MST_MSCRD:
155 155 
		s->mscrd =  value;
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		break;
157 
	case MST_INTMSKENA:	/* Mask interupt */
157 
	case MST_INTMSKENA:	/* Mask interrupt */
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		s->intmskena = (value & 0xFEEFF);
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		qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
160 160 
		break;
b/hw/pl031.c
161 161 
        pl031_update(s);
162 162 
        break;
163 163 
    case RTC_ICR:
164 
        /* The PL031 documentation (DDI0224B) states that the interupt is
164 
        /* The PL031 documentation (DDI0224B) states that the interrupt is
165 165 
           cleared when bit 0 of the written value is set.  However the
166 166 
           arm926e documentation (DDI0287B) states that the interrupt is
167 167 
           cleared when any value is written.  */
b/hw/pl061.c
98 98 
        return s->isense;
99 99 
    case 0x408: /* Interrupt both edges */
100 100 
        return s->ibe;
101 
    case 0x40c: /* Interupt event */
101 
    case 0x40c: /* Interrupt event */
102 102 
        return s->iev;
103 103 
    case 0x410: /* Interrupt mask */
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        return s->im;
......
156 156 
    case 0x408: /* Interrupt both edges */
157 157 
        s->ibe = value;
158 158 
        break;
159 
    case 0x40c: /* Interupt event */
159 
    case 0x40c: /* Interrupt event */
160 160 
        s->iev = value;
161 161 
        break;
162 162 
    case 0x410: /* Interrupt mask */
b/target-mips/translate_init.c
38 38 
((1 << CP0C2_M))
39 39 

  		





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/* No config4, no DSP ASE, no large physaddr (PABITS),


  		





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   no external interrupt controller, no vectored interupts,


  		





  
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   no external interrupt controller, no vectored interrupts,


  		





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   no 1kb pages, no SmartMIPS ASE, no trace logic */


  		





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#define MIPS_CONFIG3                                              \


  		





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((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \


  		












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