Revision ff2712ba target-mips/translate_init.c

b/target-mips/translate_init.c
38 38 
((1 << CP0C2_M))
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/* No config4, no DSP ASE, no large physaddr (PABITS),


  		





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   no external interrupt controller, no vectored interupts,


  		





  
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   no external interrupt controller, no vectored interrupts,


  		





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   no 1kb pages, no SmartMIPS ASE, no trace logic */


  		





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#define MIPS_CONFIG3                                              \


  		





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((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \


  		












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