Revision ffd39257

b/Makefile.target
731 731
endif
732 732
ifeq ($(TARGET_BASE_ARCH), sh4)
733 733
OBJS+= shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
734
OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o
734
OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o sm501.o serial.o
735 735
endif
736 736
ifeq ($(TARGET_BASE_ARCH), m68k)
737 737
OBJS+= an5206.o mcf5206.o ptimer.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
b/hw/devices.h
73 73
qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s);
74 74
qemu_irq tc6393xb_l3v_get(struct tc6393xb_s *s);
75 75

  
76
/* sm501.c */
77
void sm501_init(DisplayState *ds, uint32_t base, unsigned long local_mem_base,
78
		uint32_t local_mem_bytes, CharDriverState *chr);
76 79
#endif
b/hw/r2d.c
25 25

  
26 26
#include "hw.h"
27 27
#include "sh.h"
28
#include "devices.h"
28 29
#include "sysemu.h"
29 30
#include "boards.h"
30 31

  
31 32
#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
32 33
#define SDRAM_SIZE 0x04000000
33 34

  
35
#define SM501_VRAM_SIZE 0x800000
36

  
34 37
#define PA_POWOFF	0x30
35 38
#define PA_VERREG	0x32
36 39
#define PA_OUTPORT	0x36
......
133 136
{
134 137
    CPUState *env;
135 138
    struct SH7750State *s;
139
    ram_addr_t sdram_addr, sm501_vga_ram_addr;
136 140

  
137 141
    if (!cpu_model)
138 142
        cpu_model = "SH7751R";
......
144 148
    }
145 149

  
146 150
    /* Allocate memory space */
147
    cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, 0);
151
    sdram_addr = qemu_ram_alloc(SDRAM_SIZE);
152
    cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
148 153
    /* Register peripherals */
149 154
    r2d_fpga_init(0x04000000);
150 155
    s = sh7750_init(env);
156
    sm501_vga_ram_addr = qemu_ram_alloc(SM501_VRAM_SIZE);
157
    sm501_init(ds, 0x10000000, sm501_vga_ram_addr, SM501_VRAM_SIZE,
158
	       serial_hds[2]);
151 159
    /* Todo: register on board registers */
152 160
    {
153 161
      int kernel_size;
......
167 175
    .name = "r2d",
168 176
    .desc = "r2d-plus board",
169 177
    .init = r2d_init,
170
    .ram_require = SDRAM_SIZE | RAMSIZE_FIXED,
178
    .ram_require = (SDRAM_SIZE + SM501_VRAM_SIZE) | RAMSIZE_FIXED,
171 179
};
b/hw/sm501.c
1
/*
2
 * QEMU SM501 Device
3
 *
4
 * Copyright (c) 2008 Shin-ichiro KAWASAKI
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
 * THE SOFTWARE.
23
 */
24

  
25
#include <stdio.h>
26
#include <assert.h>
27
#include "hw.h"
28
#include "pc.h"
29
#include "console.h"
30

  
31
/*
32
 * Status: 2008/11/02
33
 *   - Minimum implementation for Linux console : mmio regs and CRT layer.
34
 *   - Always updates full screen.
35
 *
36
 * TODO:
37
 *   - Panel support
38
 *   - Hardware cursor support
39
 *   - Touch panel support
40
 *   - USB support
41
 *   - UART support
42
 *   - Performance tuning
43
 */
44

  
45
//#define DEBUG_SM501
46
//#define DEBUG_BITBLT
47

  
48
#ifdef DEBUG_SM501
49
#define SM501_DPRINTF(fmt...) printf(fmt)
50
#else
51
#define SM501_DPRINTF(fmt...) do {} while(0)
52
#endif
53

  
54

  
55
#define MMIO_BASE_OFFSET 0x3e00000
56

  
57
/* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
58

  
59
/* System Configuration area */
60
/* System config base */
61
#define SM501_SYS_CONFIG		(0x000000)
62

  
63
/* config 1 */
64
#define SM501_SYSTEM_CONTROL 		(0x000000)
65

  
66
#define SM501_SYSCTRL_PANEL_TRISTATE	(1<<0)
67
#define SM501_SYSCTRL_MEM_TRISTATE	(1<<1)
68
#define SM501_SYSCTRL_CRT_TRISTATE	(1<<2)
69

  
70
#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4)
71
#define SM501_SYSCTRL_PCI_SLAVE_BURST_1	(0<<4)
72
#define SM501_SYSCTRL_PCI_SLAVE_BURST_2	(1<<4)
73
#define SM501_SYSCTRL_PCI_SLAVE_BURST_4	(2<<4)
74
#define SM501_SYSCTRL_PCI_SLAVE_BURST_8	(3<<4)
75

  
76
#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN	(1<<6)
77
#define SM501_SYSCTRL_PCI_RETRY_DISABLE	(1<<7)
78
#define SM501_SYSCTRL_PCI_SUBSYS_LOCK	(1<<11)
79
#define SM501_SYSCTRL_PCI_BURST_READ_EN	(1<<15)
80

  
81
/* miscellaneous control */
82

  
83
#define SM501_MISC_CONTROL		(0x000004)
84

  
85
#define SM501_MISC_BUS_SH		(0x0)
86
#define SM501_MISC_BUS_PCI		(0x1)
87
#define SM501_MISC_BUS_XSCALE		(0x2)
88
#define SM501_MISC_BUS_NEC		(0x6)
89
#define SM501_MISC_BUS_MASK		(0x7)
90

  
91
#define SM501_MISC_VR_62MB		(1<<3)
92
#define SM501_MISC_CDR_RESET		(1<<7)
93
#define SM501_MISC_USB_LB		(1<<8)
94
#define SM501_MISC_USB_SLAVE		(1<<9)
95
#define SM501_MISC_BL_1			(1<<10)
96
#define SM501_MISC_MC			(1<<11)
97
#define SM501_MISC_DAC_POWER		(1<<12)
98
#define SM501_MISC_IRQ_INVERT		(1<<16)
99
#define SM501_MISC_SH			(1<<17)
100

  
101
#define SM501_MISC_HOLD_EMPTY		(0<<18)
102
#define SM501_MISC_HOLD_8		(1<<18)
103
#define SM501_MISC_HOLD_16		(2<<18)
104
#define SM501_MISC_HOLD_24		(3<<18)
105
#define SM501_MISC_HOLD_32		(4<<18)
106
#define SM501_MISC_HOLD_MASK		(7<<18)
107

  
108
#define SM501_MISC_FREQ_12		(1<<24)
109
#define SM501_MISC_PNL_24BIT		(1<<25)
110
#define SM501_MISC_8051_LE		(1<<26)
111

  
112

  
113

  
114
#define SM501_GPIO31_0_CONTROL		(0x000008)
115
#define SM501_GPIO63_32_CONTROL		(0x00000C)
116
#define SM501_DRAM_CONTROL		(0x000010)
117

  
118
/* command list */
119
#define SM501_ARBTRTN_CONTROL		(0x000014)
120

  
121
/* command list */
122
#define SM501_COMMAND_LIST_STATUS	(0x000024)
123

  
124
/* interrupt debug */
125
#define SM501_RAW_IRQ_STATUS		(0x000028)
126
#define SM501_RAW_IRQ_CLEAR		(0x000028)
127
#define SM501_IRQ_STATUS		(0x00002C)
128
#define SM501_IRQ_MASK			(0x000030)
129
#define SM501_DEBUG_CONTROL		(0x000034)
130

  
131
/* power management */
132
#define SM501_POWERMODE_P2X_SRC		(1<<29)
133
#define SM501_POWERMODE_V2X_SRC		(1<<20)
134
#define SM501_POWERMODE_M_SRC		(1<<12)
135
#define SM501_POWERMODE_M1_SRC		(1<<4)
136

  
137
#define SM501_CURRENT_GATE		(0x000038)
138
#define SM501_CURRENT_CLOCK		(0x00003C)
139
#define SM501_POWER_MODE_0_GATE		(0x000040)
140
#define SM501_POWER_MODE_0_CLOCK	(0x000044)
141
#define SM501_POWER_MODE_1_GATE		(0x000048)
142
#define SM501_POWER_MODE_1_CLOCK	(0x00004C)
143
#define SM501_SLEEP_MODE_GATE		(0x000050)
144
#define SM501_POWER_MODE_CONTROL	(0x000054)
145

  
146
/* power gates for units within the 501 */
147
#define SM501_GATE_HOST			(0)
148
#define SM501_GATE_MEMORY		(1)
149
#define SM501_GATE_DISPLAY		(2)
150
#define SM501_GATE_2D_ENGINE		(3)
151
#define SM501_GATE_CSC			(4)
152
#define SM501_GATE_ZVPORT		(5)
153
#define SM501_GATE_GPIO			(6)
154
#define SM501_GATE_UART0		(7)
155
#define SM501_GATE_UART1		(8)
156
#define SM501_GATE_SSP			(10)
157
#define SM501_GATE_USB_HOST		(11)
158
#define SM501_GATE_USB_GADGET		(12)
159
#define SM501_GATE_UCONTROLLER		(17)
160
#define SM501_GATE_AC97			(18)
161

  
162
/* panel clock */
163
#define SM501_CLOCK_P2XCLK		(24)
164
/* crt clock */
165
#define SM501_CLOCK_V2XCLK		(16)
166
/* main clock */
167
#define SM501_CLOCK_MCLK		(8)
168
/* SDRAM controller clock */
169
#define SM501_CLOCK_M1XCLK		(0)
170

  
171
/* config 2 */
172
#define SM501_PCI_MASTER_BASE		(0x000058)
173
#define SM501_ENDIAN_CONTROL		(0x00005C)
174
#define SM501_DEVICEID			(0x000060)
175
/* 0x050100A0 */
176

  
177
#define SM501_DEVICEID_SM501		(0x05010000)
178
#define SM501_DEVICEID_IDMASK		(0xffff0000)
179
#define SM501_DEVICEID_REVMASK		(0x000000ff)
180

  
181
#define SM501_PLLCLOCK_COUNT		(0x000064)
182
#define SM501_MISC_TIMING		(0x000068)
183
#define SM501_CURRENT_SDRAM_CLOCK	(0x00006C)
184

  
185
#define SM501_PROGRAMMABLE_PLL_CONTROL	(0x000074)
186

  
187
/* GPIO base */
188
#define SM501_GPIO			(0x010000)
189
#define SM501_GPIO_DATA_LOW		(0x00)
190
#define SM501_GPIO_DATA_HIGH		(0x04)
191
#define SM501_GPIO_DDR_LOW		(0x08)
192
#define SM501_GPIO_DDR_HIGH		(0x0C)
193
#define SM501_GPIO_IRQ_SETUP		(0x10)
194
#define SM501_GPIO_IRQ_STATUS		(0x14)
195
#define SM501_GPIO_IRQ_RESET		(0x14)
196

  
197
/* I2C controller base */
198
#define SM501_I2C			(0x010040)
199
#define SM501_I2C_BYTE_COUNT		(0x00)
200
#define SM501_I2C_CONTROL		(0x01)
201
#define SM501_I2C_STATUS		(0x02)
202
#define SM501_I2C_RESET			(0x02)
203
#define SM501_I2C_SLAVE_ADDRESS		(0x03)
204
#define SM501_I2C_DATA			(0x04)
205

  
206
/* SSP base */
207
#define SM501_SSP			(0x020000)
208

  
209
/* Uart 0 base */
210
#define SM501_UART0			(0x030000)
211

  
212
/* Uart 1 base */
213
#define SM501_UART1			(0x030020)
214

  
215
/* USB host port base */
216
#define SM501_USB_HOST			(0x040000)
217

  
218
/* USB slave/gadget base */
219
#define SM501_USB_GADGET		(0x060000)
220

  
221
/* USB slave/gadget data port base */
222
#define SM501_USB_GADGET_DATA		(0x070000)
223

  
224
/* Display controller/video engine base */
225
#define SM501_DC			(0x080000)
226

  
227
/* common defines for the SM501 address registers */
228
#define SM501_ADDR_FLIP			(1<<31)
229
#define SM501_ADDR_EXT			(1<<27)
230
#define SM501_ADDR_CS1			(1<<26)
231
#define SM501_ADDR_MASK			(0x3f << 26)
232

  
233
#define SM501_FIFO_MASK			(0x3 << 16)
234
#define SM501_FIFO_1			(0x0 << 16)
235
#define SM501_FIFO_3			(0x1 << 16)
236
#define SM501_FIFO_7			(0x2 << 16)
237
#define SM501_FIFO_11			(0x3 << 16)
238

  
239
/* common registers for panel and the crt */
240
#define SM501_OFF_DC_H_TOT		(0x000)
241
#define SM501_OFF_DC_V_TOT		(0x008)
242
#define SM501_OFF_DC_H_SYNC		(0x004)
243
#define SM501_OFF_DC_V_SYNC		(0x00C)
244

  
245
#define SM501_DC_PANEL_CONTROL		(0x000)
246

  
247
#define SM501_DC_PANEL_CONTROL_FPEN	(1<<27)
248
#define SM501_DC_PANEL_CONTROL_BIAS	(1<<26)
249
#define SM501_DC_PANEL_CONTROL_DATA	(1<<25)
250
#define SM501_DC_PANEL_CONTROL_VDD	(1<<24)
251
#define SM501_DC_PANEL_CONTROL_DP	(1<<23)
252

  
253
#define SM501_DC_PANEL_CONTROL_TFT_888	(0<<21)
254
#define SM501_DC_PANEL_CONTROL_TFT_333	(1<<21)
255
#define SM501_DC_PANEL_CONTROL_TFT_444	(2<<21)
256

  
257
#define SM501_DC_PANEL_CONTROL_DE	(1<<20)
258

  
259
#define SM501_DC_PANEL_CONTROL_LCD_TFT	(0<<18)
260
#define SM501_DC_PANEL_CONTROL_LCD_STN8	(1<<18)
261
#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18)
262

  
263
#define SM501_DC_PANEL_CONTROL_CP	(1<<14)
264
#define SM501_DC_PANEL_CONTROL_VSP	(1<<13)
265
#define SM501_DC_PANEL_CONTROL_HSP	(1<<12)
266
#define SM501_DC_PANEL_CONTROL_CK	(1<<9)
267
#define SM501_DC_PANEL_CONTROL_TE	(1<<8)
268
#define SM501_DC_PANEL_CONTROL_VPD	(1<<7)
269
#define SM501_DC_PANEL_CONTROL_VP	(1<<6)
270
#define SM501_DC_PANEL_CONTROL_HPD	(1<<5)
271
#define SM501_DC_PANEL_CONTROL_HP	(1<<4)
272
#define SM501_DC_PANEL_CONTROL_GAMMA	(1<<3)
273
#define SM501_DC_PANEL_CONTROL_EN	(1<<2)
274

  
275
#define SM501_DC_PANEL_CONTROL_8BPP	(0<<0)
276
#define SM501_DC_PANEL_CONTROL_16BPP	(1<<0)
277
#define SM501_DC_PANEL_CONTROL_32BPP	(2<<0)
278

  
279

  
280
#define SM501_DC_PANEL_PANNING_CONTROL	(0x004)
281
#define SM501_DC_PANEL_COLOR_KEY	(0x008)
282
#define SM501_DC_PANEL_FB_ADDR		(0x00C)
283
#define SM501_DC_PANEL_FB_OFFSET	(0x010)
284
#define SM501_DC_PANEL_FB_WIDTH		(0x014)
285
#define SM501_DC_PANEL_FB_HEIGHT	(0x018)
286
#define SM501_DC_PANEL_TL_LOC		(0x01C)
287
#define SM501_DC_PANEL_BR_LOC		(0x020)
288
#define SM501_DC_PANEL_H_TOT		(0x024)
289
#define SM501_DC_PANEL_H_SYNC		(0x028)
290
#define SM501_DC_PANEL_V_TOT		(0x02C)
291
#define SM501_DC_PANEL_V_SYNC		(0x030)
292
#define SM501_DC_PANEL_CUR_LINE		(0x034)
293

  
294
#define SM501_DC_VIDEO_CONTROL		(0x040)
295
#define SM501_DC_VIDEO_FB0_ADDR		(0x044)
296
#define SM501_DC_VIDEO_FB_WIDTH		(0x048)
297
#define SM501_DC_VIDEO_FB0_LAST_ADDR	(0x04C)
298
#define SM501_DC_VIDEO_TL_LOC		(0x050)
299
#define SM501_DC_VIDEO_BR_LOC		(0x054)
300
#define SM501_DC_VIDEO_SCALE		(0x058)
301
#define SM501_DC_VIDEO_INIT_SCALE	(0x05C)
302
#define SM501_DC_VIDEO_YUV_CONSTANTS	(0x060)
303
#define SM501_DC_VIDEO_FB1_ADDR		(0x064)
304
#define SM501_DC_VIDEO_FB1_LAST_ADDR	(0x068)
305

  
306
#define SM501_DC_VIDEO_ALPHA_CONTROL	(0x080)
307
#define SM501_DC_VIDEO_ALPHA_FB_ADDR	(0x084)
308
#define SM501_DC_VIDEO_ALPHA_FB_OFFSET	(0x088)
309
#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR	(0x08C)
310
#define SM501_DC_VIDEO_ALPHA_TL_LOC	(0x090)
311
#define SM501_DC_VIDEO_ALPHA_BR_LOC	(0x094)
312
#define SM501_DC_VIDEO_ALPHA_SCALE	(0x098)
313
#define SM501_DC_VIDEO_ALPHA_INIT_SCALE	(0x09C)
314
#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY	(0x0A0)
315
#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP	(0x0A4)
316

  
317
#define SM501_DC_PANEL_HWC_BASE		(0x0F0)
318
#define SM501_DC_PANEL_HWC_ADDR		(0x0F0)
319
#define SM501_DC_PANEL_HWC_LOC		(0x0F4)
320
#define SM501_DC_PANEL_HWC_COLOR_1_2	(0x0F8)
321
#define SM501_DC_PANEL_HWC_COLOR_3	(0x0FC)
322

  
323
#define SM501_HWC_EN			(1<<31)
324

  
325
#define SM501_OFF_HWC_ADDR		(0x00)
326
#define SM501_OFF_HWC_LOC		(0x04)
327
#define SM501_OFF_HWC_COLOR_1_2		(0x08)
328
#define SM501_OFF_HWC_COLOR_3		(0x0C)
329

  
330
#define SM501_DC_ALPHA_CONTROL		(0x100)
331
#define SM501_DC_ALPHA_FB_ADDR		(0x104)
332
#define SM501_DC_ALPHA_FB_OFFSET	(0x108)
333
#define SM501_DC_ALPHA_TL_LOC		(0x10C)
334
#define SM501_DC_ALPHA_BR_LOC		(0x110)
335
#define SM501_DC_ALPHA_CHROMA_KEY	(0x114)
336
#define SM501_DC_ALPHA_COLOR_LOOKUP	(0x118)
337

  
338
#define SM501_DC_CRT_CONTROL		(0x200)
339

  
340
#define SM501_DC_CRT_CONTROL_TVP	(1<<15)
341
#define SM501_DC_CRT_CONTROL_CP		(1<<14)
342
#define SM501_DC_CRT_CONTROL_VSP	(1<<13)
343
#define SM501_DC_CRT_CONTROL_HSP	(1<<12)
344
#define SM501_DC_CRT_CONTROL_VS		(1<<11)
345
#define SM501_DC_CRT_CONTROL_BLANK	(1<<10)
346
#define SM501_DC_CRT_CONTROL_SEL	(1<<9)
347
#define SM501_DC_CRT_CONTROL_TE		(1<<8)
348
#define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
349
#define SM501_DC_CRT_CONTROL_GAMMA	(1<<3)
350
#define SM501_DC_CRT_CONTROL_ENABLE	(1<<2)
351

  
352
#define SM501_DC_CRT_CONTROL_8BPP	(0<<0)
353
#define SM501_DC_CRT_CONTROL_16BPP	(1<<0)
354
#define SM501_DC_CRT_CONTROL_32BPP	(2<<0)
355

  
356
#define SM501_DC_CRT_FB_ADDR		(0x204)
357
#define SM501_DC_CRT_FB_OFFSET		(0x208)
358
#define SM501_DC_CRT_H_TOT		(0x20C)
359
#define SM501_DC_CRT_H_SYNC		(0x210)
360
#define SM501_DC_CRT_V_TOT		(0x214)
361
#define SM501_DC_CRT_V_SYNC		(0x218)
362
#define SM501_DC_CRT_SIGNATURE_ANALYZER	(0x21C)
363
#define SM501_DC_CRT_CUR_LINE		(0x220)
364
#define SM501_DC_CRT_MONITOR_DETECT	(0x224)
365

  
366
#define SM501_DC_CRT_HWC_BASE		(0x230)
367
#define SM501_DC_CRT_HWC_ADDR		(0x230)
368
#define SM501_DC_CRT_HWC_LOC		(0x234)
369
#define SM501_DC_CRT_HWC_COLOR_1_2	(0x238)
370
#define SM501_DC_CRT_HWC_COLOR_3	(0x23C)
371

  
372
#define SM501_DC_PANEL_PALETTE		(0x400)
373

  
374
#define SM501_DC_VIDEO_PALETTE		(0x800)
375

  
376
#define SM501_DC_CRT_PALETTE		(0xC00)
377

  
378
/* Zoom Video port base */
379
#define SM501_ZVPORT			(0x090000)
380

  
381
/* AC97/I2S base */
382
#define SM501_AC97			(0x0A0000)
383

  
384
/* 8051 micro controller base */
385
#define SM501_UCONTROLLER		(0x0B0000)
386

  
387
/* 8051 micro controller SRAM base */
388
#define SM501_UCONTROLLER_SRAM		(0x0C0000)
389

  
390
/* DMA base */
391
#define SM501_DMA			(0x0D0000)
392

  
393
/* 2d engine base */
394
#define SM501_2D_ENGINE			(0x100000)
395
#define SM501_2D_SOURCE			(0x00)
396
#define SM501_2D_DESTINATION		(0x04)
397
#define SM501_2D_DIMENSION		(0x08)
398
#define SM501_2D_CONTROL		(0x0C)
399
#define SM501_2D_PITCH			(0x10)
400
#define SM501_2D_FOREGROUND		(0x14)
401
#define SM501_2D_BACKGROUND		(0x18)
402
#define SM501_2D_STRETCH		(0x1C)
403
#define SM501_2D_COLOR_COMPARE		(0x20)
404
#define SM501_2D_COLOR_COMPARE_MASK 	(0x24)
405
#define SM501_2D_MASK			(0x28)
406
#define SM501_2D_CLIP_TL		(0x2C)
407
#define SM501_2D_CLIP_BR		(0x30)
408
#define SM501_2D_MONO_PATTERN_LOW	(0x34)
409
#define SM501_2D_MONO_PATTERN_HIGH	(0x38)
410
#define SM501_2D_WINDOW_WIDTH		(0x3C)
411
#define SM501_2D_SOURCE_BASE		(0x40)
412
#define SM501_2D_DESTINATION_BASE	(0x44)
413
#define SM501_2D_ALPHA			(0x48)
414
#define SM501_2D_WRAP			(0x4C)
415
#define SM501_2D_STATUS			(0x50)
416

  
417
#define SM501_CSC_Y_SOURCE_BASE		(0xC8)
418
#define SM501_CSC_CONSTANTS		(0xCC)
419
#define SM501_CSC_Y_SOURCE_X		(0xD0)
420
#define SM501_CSC_Y_SOURCE_Y		(0xD4)
421
#define SM501_CSC_U_SOURCE_BASE		(0xD8)
422
#define SM501_CSC_V_SOURCE_BASE		(0xDC)
423
#define SM501_CSC_SOURCE_DIMENSION	(0xE0)
424
#define SM501_CSC_SOURCE_PITCH		(0xE4)
425
#define SM501_CSC_DESTINATION		(0xE8)
426
#define SM501_CSC_DESTINATION_DIMENSION	(0xEC)
427
#define SM501_CSC_DESTINATION_PITCH	(0xF0)
428
#define SM501_CSC_SCALE_FACTOR		(0xF4)
429
#define SM501_CSC_DESTINATION_BASE	(0xF8)
430
#define SM501_CSC_CONTROL		(0xFC)
431

  
432
/* 2d engine data port base */
433
#define SM501_2D_ENGINE_DATA		(0x110000)
434

  
435
/* end of register definitions */
436

  
437

  
438
/* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
439
static const uint32_t sm501_mem_local_size[] = {
440
	[0]	= 4*1024*1024,
441
	[1]	= 8*1024*1024,
442
	[2]	= 16*1024*1024,
443
	[3]	= 32*1024*1024,
444
	[4]	= 64*1024*1024,
445
	[5]	= 2*1024*1024,
446
};
447
#define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
448

  
449
typedef struct SM501State {
450
    /* graphic console status */
451
    DisplayState *ds;
452
    QEMUConsole *console;
453

  
454
    /* status & internal resources */
455
    target_phys_addr_t base;
456
    uint32_t local_mem_size_index;
457
    uint8_t * local_mem;
458
    uint32_t last_width;
459
    uint32_t last_height;
460

  
461
    /* mmio registers */
462
    uint32_t system_control;
463
    uint32_t misc_control;
464
    uint32_t gpio_31_0_control;
465
    uint32_t gpio_63_32_control;
466
    uint32_t dram_control;
467
    uint32_t irq_mask;
468
    uint32_t misc_timing;
469
    uint32_t power_mode_control;
470

  
471
    uint32_t uart0_ier;
472
    uint32_t uart0_lcr;
473
    uint32_t uart0_mcr;
474
    uint32_t uart0_scr;
475

  
476
    uint8_t dc_palette[0x400 * 3];
477

  
478
    uint32_t dc_panel_control;
479
    uint32_t dc_panel_panning_control;
480
    uint32_t dc_panel_fb_addr;
481
    uint32_t dc_panel_fb_offset;
482
    uint32_t dc_panel_fb_width;
483
    uint32_t dc_panel_fb_height;
484
    uint32_t dc_panel_tl_location;
485
    uint32_t dc_panel_br_location;
486
    uint32_t dc_panel_h_total;
487
    uint32_t dc_panel_h_sync;
488
    uint32_t dc_panel_v_total;
489
    uint32_t dc_panel_v_sync;
490

  
491
    uint32_t dc_panel_hwc_addr;
492
    uint32_t dc_panel_hwc_location;
493
    uint32_t dc_panel_hwc_color_1_2;
494
    uint32_t dc_panel_hwc_color_3;
495

  
496
    uint32_t dc_crt_control;
497
    uint32_t dc_crt_fb_addr;
498
    uint32_t dc_crt_fb_offset;
499
    uint32_t dc_crt_h_total;
500
    uint32_t dc_crt_h_sync;
501
    uint32_t dc_crt_v_total;
502
    uint32_t dc_crt_v_sync;
503

  
504
    uint32_t dc_crt_hwc_addr;
505
    uint32_t dc_crt_hwc_location;
506
    uint32_t dc_crt_hwc_color_1_2;
507
    uint32_t dc_crt_hwc_color_3;
508

  
509
} SM501State;
510

  
511
static uint32_t get_local_mem_size_index(uint32_t size)
512
{
513
    uint32_t norm_size = 0;
514
    int i, index = 0;
515

  
516
    for (i = 0; i < sizeof(sm501_mem_local_size)/sizeof(uint32_t); i++) {
517
	uint32_t new_size = sm501_mem_local_size[i];
518
	if (new_size >= size) {
519
	    if (norm_size == 0 || norm_size > new_size) {
520
		norm_size = new_size;
521
		index = i;
522
	    }
523
	}
524
    }
525

  
526
    return index;
527
}
528

  
529
static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr)
530
{
531
    SM501State * s = (SM501State *)opaque;
532
    uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET);
533
    uint32_t ret = 0;
534
    SM501_DPRINTF("sm501 system config regs : read addr=%x, offset=%x\n",
535
		  addr, offset);
536

  
537
    switch(offset) {
538
    case SM501_SYSTEM_CONTROL:
539
	ret = s->system_control;
540
	break;
541
    case SM501_MISC_CONTROL:
542
	ret = s->misc_control;
543
	break;
544
    case SM501_GPIO31_0_CONTROL:
545
	ret = s->gpio_31_0_control;
546
	break;
547
    case SM501_GPIO63_32_CONTROL:
548
	ret = s->gpio_63_32_control;
549
	break;
550
    case SM501_DEVICEID:
551
	ret = 0x050100A0;
552
	break;
553
    case SM501_DRAM_CONTROL:
554
	ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13;
555
	break;
556
    case SM501_IRQ_MASK:
557
	ret = s->irq_mask;
558
	break;
559
    case SM501_MISC_TIMING:
560
	/* TODO : simulate gate control */
561
	ret = s->misc_timing;
562
	break;
563
    case SM501_CURRENT_GATE:
564
	/* TODO : simulate gate control */
565
	ret = 0x00021807;
566
	break;
567
    case SM501_CURRENT_CLOCK:
568
	ret = 0x2A1A0A09;
569
	break;
570
    case SM501_POWER_MODE_CONTROL:
571
	ret = s->power_mode_control;
572
	break;
573

  
574
    default:
575
	printf("sm501 system config : not implemented register read."
576
	       " addr=%x, offset=%x\n", addr, offset);
577
	assert(0);
578
    }
579

  
580
    return ret;
581
}
582

  
583
static void sm501_system_config_write(void *opaque,
584
				      target_phys_addr_t addr, uint32_t value)
585
{
586
    SM501State * s = (SM501State *)opaque;
587
    uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET);
588
    SM501_DPRINTF("sm501 system config regs : write addr=%x, ofs=%x, val=%x\n",
589
		  addr, offset, value);
590

  
591
    switch(offset) {
592
    case SM501_SYSTEM_CONTROL:
593
	s->system_control = value & 0xE300B8F7;
594
	break;
595
    case SM501_MISC_CONTROL:
596
	s->misc_control = value & 0xFF7FFF20;
597
	break;
598
    case SM501_GPIO31_0_CONTROL:
599
	s->gpio_31_0_control = value;
600
	break;
601
    case SM501_GPIO63_32_CONTROL:
602
	s->gpio_63_32_control = value;
603
	break;
604
    case SM501_DRAM_CONTROL:
605
	s->local_mem_size_index = (value >> 13) & 0x7;
606
	/* rODO : check validity of size change */
607
	s->dram_control |=  value & 0x7FFFFFC3;
608
	break;
609
    case SM501_IRQ_MASK:
610
	s->irq_mask = value;
611
	break;
612
    case SM501_MISC_TIMING:
613
	s->misc_timing = value & 0xF31F1FFF;
614
	break;
615
    case SM501_POWER_MODE_0_GATE:
616
    case SM501_POWER_MODE_1_GATE:
617
    case SM501_POWER_MODE_0_CLOCK:
618
    case SM501_POWER_MODE_1_CLOCK:
619
	/* TODO : simulate gate & clock control */
620
	break;
621
    case SM501_POWER_MODE_CONTROL:
622
	s->power_mode_control = value & 0x00000003;
623
	break;
624

  
625
    default:
626
	printf("sm501 system config : not implemented register write."
627
	       " addr=%x, val=%x\n", addr, value);
628
	assert(0);
629
    }
630
}
631

  
632
static CPUReadMemoryFunc *sm501_system_config_readfn[] = {
633
    NULL,
634
    NULL,
635
    &sm501_system_config_read,
636
};
637

  
638
static CPUWriteMemoryFunc *sm501_system_config_writefn[] = {
639
    NULL,
640
    NULL,
641
    &sm501_system_config_write,
642
};
643

  
644
static uint32_t sm501_disp_ctrl_read(void *opaque,
645
					      target_phys_addr_t addr)
646
{
647
    SM501State * s = (SM501State *)opaque;
648
    uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET + SM501_DC);
649
    uint32_t ret = 0;
650
    SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x, offset=%x\n",
651
		  addr, offset);
652

  
653
    switch(offset) {
654

  
655
    case SM501_DC_PANEL_CONTROL:
656
	ret = s->dc_panel_control;
657
	break;
658
    case SM501_DC_PANEL_PANNING_CONTROL:
659
	ret = s->dc_panel_panning_control;
660
	break;
661
    case SM501_DC_PANEL_FB_ADDR:
662
	ret = s->dc_panel_fb_addr;
663
	break;
664
    case SM501_DC_PANEL_FB_OFFSET:
665
	ret = s->dc_panel_fb_offset;
666
	break;
667
    case SM501_DC_PANEL_FB_WIDTH:
668
	ret = s->dc_panel_fb_width;
669
	break;
670
    case SM501_DC_PANEL_FB_HEIGHT:
671
	ret = s->dc_panel_fb_height;
672
	break;
673
    case SM501_DC_PANEL_TL_LOC:
674
	ret = s->dc_panel_tl_location;
675
	break;
676
    case SM501_DC_PANEL_BR_LOC:
677
	ret = s->dc_panel_br_location;
678
	break;
679

  
680
    case SM501_DC_PANEL_H_TOT:
681
	ret = s->dc_panel_h_total;
682
	break;
683
    case SM501_DC_PANEL_H_SYNC:
684
	ret = s->dc_panel_h_sync;
685
	break;
686
    case SM501_DC_PANEL_V_TOT:
687
	ret = s->dc_panel_v_total;
688
	break;
689
    case SM501_DC_PANEL_V_SYNC:
690
	ret = s->dc_panel_v_sync;
691
	break;
692

  
693
    case SM501_DC_CRT_CONTROL:
694
	ret = s->dc_crt_control;
695
	break;
696
    case SM501_DC_CRT_FB_ADDR:
697
	ret = s->dc_crt_fb_addr;
698
	break;
699
    case SM501_DC_CRT_FB_OFFSET:
700
	ret = s->dc_crt_fb_offset;
701
	break;
702
    case SM501_DC_CRT_H_TOT:
703
	ret = s->dc_crt_h_total;
704
	break;
705
    case SM501_DC_CRT_H_SYNC:
706
	ret = s->dc_crt_h_sync;
707
	break;
708
    case SM501_DC_CRT_V_TOT:
709
	ret = s->dc_crt_v_total;
710
	break;
711
    case SM501_DC_CRT_V_SYNC:
712
	ret = s->dc_crt_v_sync;
713
	break;
714

  
715
    case SM501_DC_CRT_HWC_ADDR:
716
	ret = s->dc_crt_hwc_addr;
717
	break;
718
    case SM501_DC_CRT_HWC_LOC:
719
	ret = s->dc_crt_hwc_addr;
720
	break;
721
    case SM501_DC_CRT_HWC_COLOR_1_2:
722
	ret = s->dc_crt_hwc_addr;
723
	break;
724
    case SM501_DC_CRT_HWC_COLOR_3:
725
	ret = s->dc_crt_hwc_addr;
726
	break;
727

  
728
    default:
729
	printf("sm501 disp ctrl : not implemented register read."
730
	       " addr=%x, offset=%x\n", addr, offset);
731
	assert(0);
732
    }
733

  
734
    return ret;
735
}
736

  
737
static void sm501_disp_ctrl_write(void *opaque,
738
					   target_phys_addr_t addr,
739
					   uint32_t value)
740
{
741
    SM501State * s = (SM501State *)opaque;
742
    uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET + SM501_DC);
743
    SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, ofs=%x, val=%x\n",
744
		  addr, offset, value);
745

  
746
    switch(offset) {
747
    case SM501_DC_PANEL_CONTROL:
748
	s->dc_panel_control = value & 0x0FFF73FF;
749
	break;
750
    case SM501_DC_PANEL_PANNING_CONTROL:
751
	s->dc_panel_panning_control = value & 0xFF3FFF3F;
752
	break;
753
    case SM501_DC_PANEL_FB_ADDR:
754
	s->dc_panel_fb_addr = value & 0x8FFFFFF0;
755
	break;
756
    case SM501_DC_PANEL_FB_OFFSET:
757
	s->dc_panel_fb_offset = value & 0x3FF03FF0;
758
	break;
759
    case SM501_DC_PANEL_FB_WIDTH:
760
	s->dc_panel_fb_width = value & 0x0FFF0FFF;
761
	break;
762
    case SM501_DC_PANEL_FB_HEIGHT:
763
	s->dc_panel_fb_height = value & 0x0FFF0FFF;
764
	break;
765
    case SM501_DC_PANEL_TL_LOC:
766
	s->dc_panel_tl_location = value & 0x07FF07FF;
767
	break;
768
    case SM501_DC_PANEL_BR_LOC:
769
	s->dc_panel_br_location = value & 0x07FF07FF;
770
	break;
771

  
772
    case SM501_DC_PANEL_H_TOT:
773
	s->dc_panel_h_total = value & 0x0FFF0FFF;
774
	break;
775
    case SM501_DC_PANEL_H_SYNC:
776
	s->dc_panel_h_sync = value & 0x00FF0FFF;
777
	break;
778
    case SM501_DC_PANEL_V_TOT:
779
	s->dc_panel_v_total = value & 0x0FFF0FFF;
780
	break;
781
    case SM501_DC_PANEL_V_SYNC:
782
	s->dc_panel_v_sync = value & 0x003F0FFF;
783
	break;
784

  
785
    case SM501_DC_PANEL_HWC_ADDR:
786
	s->dc_panel_hwc_addr = value & 0x8FFFFFF0;
787
	break;
788
    case SM501_DC_PANEL_HWC_LOC:
789
	s->dc_panel_hwc_addr = value & 0x0FFF0FFF;
790
	break;
791
    case SM501_DC_PANEL_HWC_COLOR_1_2:
792
	s->dc_panel_hwc_addr = value;
793
	break;
794
    case SM501_DC_PANEL_HWC_COLOR_3:
795
	s->dc_panel_hwc_addr = value & 0x0000FFFF;
796
	break;
797

  
798
    case SM501_DC_CRT_CONTROL:
799
	s->dc_crt_control = value & 0x0003FFFF;
800
	break;
801
    case SM501_DC_CRT_FB_ADDR:
802
	s->dc_crt_fb_addr = value & 0x8FFFFFF0;
803
	break;
804
    case SM501_DC_CRT_FB_OFFSET:
805
	s->dc_crt_fb_offset = value & 0x3FF03FF0;
806
	break;
807
    case SM501_DC_CRT_H_TOT:
808
	s->dc_crt_h_total = value & 0x0FFF0FFF;
809
	break;
810
    case SM501_DC_CRT_H_SYNC:
811
	s->dc_crt_h_sync = value & 0x00FF0FFF;
812
	break;
813
    case SM501_DC_CRT_V_TOT:
814
	s->dc_crt_v_total = value & 0x0FFF0FFF;
815
	break;
816
    case SM501_DC_CRT_V_SYNC:
817
	s->dc_crt_v_sync = value & 0x003F0FFF;
818
	break;
819

  
820
    case SM501_DC_CRT_HWC_ADDR:
821
	s->dc_crt_hwc_addr = value & 0x8FFFFFF0;
822
	break;
823
    case SM501_DC_CRT_HWC_LOC:
824
	s->dc_crt_hwc_addr = value & 0x0FFF0FFF;
825
	break;
826
    case SM501_DC_CRT_HWC_COLOR_1_2:
827
	s->dc_crt_hwc_addr = value;
828
	break;
829
    case SM501_DC_CRT_HWC_COLOR_3:
830
	s->dc_crt_hwc_addr = value & 0x0000FFFF;
831
	break;
832

  
833
    default:
834
	printf("sm501 disp ctrl : not implemented register write."
835
	       " addr=%x, val=%x\n", addr, value);
836
	assert(0);
837
    }
838
}
839

  
840
static CPUReadMemoryFunc *sm501_disp_ctrl_readfn[] = {
841
    NULL,
842
    NULL,
843
    &sm501_disp_ctrl_read,
844
};
845

  
846
static CPUWriteMemoryFunc *sm501_disp_ctrl_writefn[] = {
847
    NULL,
848
    NULL,
849
    &sm501_disp_ctrl_write,
850
};
851

  
852
static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
853
{
854
    SM501State * s = (SM501State *)opaque;
855
    uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET
856
			      + SM501_DC + SM501_DC_PANEL_PALETTE);
857
    SM501_DPRINTF("sm501 palette read addr=%x, offset=%x\n", addr, offset);
858

  
859
    /* TODO : consider BYTE/WORD access */
860
    /* TODO : consider endian */
861

  
862
    assert(0 <= offset && offset < 0x400 * 3);
863
    return *(uint32_t*)&s->dc_palette[offset];
864
}
865

  
866
static void sm501_palette_write(void *opaque,
867
				target_phys_addr_t addr, uint32_t value)
868
{
869
    SM501State * s = (SM501State *)opaque;
870
    uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET
871
			      + SM501_DC + SM501_DC_PANEL_PALETTE);
872
    SM501_DPRINTF("sm501 palette write addr=%x, ofs=%x, val=%x\n",
873
		  addr, offset, value);
874

  
875
    /* TODO : consider BYTE/WORD access */
876
    /* TODO : consider endian */
877

  
878
    assert(0 <= offset && offset < 0x400 * 3);
879
    *(uint32_t*)&s->dc_palette[offset] = value;
880
}
881

  
882
static CPUReadMemoryFunc *sm501_palette_readfn[] = {
883
    &sm501_palette_read,
884
    &sm501_palette_read,
885
    &sm501_palette_read,
886
};
887

  
888
static CPUWriteMemoryFunc *sm501_palette_writefn[] = {
889
    &sm501_palette_write,
890
    &sm501_palette_write,
891
    &sm501_palette_write,
892
};
893

  
894

  
895
/* draw line functions for all console modes */
896

  
897
#include "pixel_ops.h"
898

  
899
typedef void draw_line_func(uint8_t *d, const uint8_t *s,
900
			    int width, const uint32_t *pal);
901

  
902
#define DEPTH 8
903
#include "sm501_template.h"
904

  
905
#define DEPTH 15
906
#include "sm501_template.h"
907

  
908
#define BGR_FORMAT
909
#define DEPTH 15
910
#include "sm501_template.h"
911

  
912
#define DEPTH 16
913
#include "sm501_template.h"
914

  
915
#define BGR_FORMAT
916
#define DEPTH 16
917
#include "sm501_template.h"
918

  
919
#define DEPTH 32
920
#include "sm501_template.h"
921

  
922
#define BGR_FORMAT
923
#define DEPTH 32
924
#include "sm501_template.h"
925

  
926
static draw_line_func * draw_line8_funcs[] = {
927
    draw_line8_8,
928
    draw_line8_15,
929
    draw_line8_16,
930
    draw_line8_32,
931
    draw_line8_32bgr,
932
    draw_line8_15bgr,
933
    draw_line8_16bgr,
934
};
935

  
936
static draw_line_func * draw_line16_funcs[] = {
937
    draw_line16_8,
938
    draw_line16_15,
939
    draw_line16_16,
940
    draw_line16_32,
941
    draw_line16_32bgr,
942
    draw_line16_15bgr,
943
    draw_line16_16bgr,
944
};
945

  
946
static draw_line_func * draw_line32_funcs[] = {
947
    draw_line32_8,
948
    draw_line32_15,
949
    draw_line32_16,
950
    draw_line32_32,
951
    draw_line32_32bgr,
952
    draw_line32_15bgr,
953
    draw_line32_16bgr,
954
};
955

  
956
static inline int get_depth_index(DisplayState *s)
957
{
958
    switch(s->depth) {
959
    default:
960
    case 8:
961
	return 0;
962
    case 15:
963
	if (s->bgr)
964
	    return 5;
965
	else
966
	    return 1;
967
    case 16:
968
	if (s->bgr)
969
	    return 6;
970
	else
971
	    return 2;
972
    case 32:
973
	if (s->bgr)
974
	    return 4;
975
	else
976
	    return 3;
977
    }
978
}
979

  
980
static void sm501_draw_crt(SM501State * s)
981
{
982
    int y;
983
    int width = (s->dc_crt_h_total & 0x00000FFF) + 1;
984
    int height = (s->dc_crt_v_total & 0x00000FFF) + 1;
985

  
986
    uint8_t  * src = s->local_mem;
987
    int src_bpp = 0;
988
    int dst_bpp = s->ds->depth / 8 + (s->ds->depth % 8 ? 1 : 0);
989
    uint32_t * palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE
990
						    - SM501_DC_PANEL_PALETTE];
991
    int ds_depth_index = get_depth_index(s->ds);
992
    draw_line_func * draw_line = NULL;
993
    int full_update = 0;
994
    int y_start = -1;
995
    int page_min = 0x7fffffff;
996
    int page_max = -1;
997

  
998
    /* choose draw_line function */
999
    switch (s->dc_crt_control & 3) {
1000
    case SM501_DC_CRT_CONTROL_8BPP:
1001
	src_bpp = 1;
1002
	draw_line = draw_line8_funcs[ds_depth_index];
1003
	break;
1004
    case SM501_DC_CRT_CONTROL_16BPP:
1005
	src_bpp = 2;
1006
	draw_line = draw_line16_funcs[ds_depth_index];
1007
	break;
1008
    case SM501_DC_CRT_CONTROL_32BPP:
1009
	src_bpp = 4;
1010
	draw_line = draw_line32_funcs[ds_depth_index];
1011
	break;
1012
    default:
1013
	printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
1014
	       s->dc_crt_control);
1015
	assert(0);
1016
	break;
1017
    }
1018

  
1019
    /* adjust console size */
1020
    if (s->last_width != width || s->last_height != height) {
1021
	qemu_console_resize(s->console, width, height);
1022
	s->last_width = width;
1023
	s->last_height = height;
1024
	full_update = 1;
1025
    }
1026

  
1027
    /* draw each line according to conditions */
1028
    for (y = 0; y < height; y++) {
1029
	int update = full_update;
1030
	uint8_t * line_end = &src[width * src_bpp - 1];
1031
	int page0 = (src - phys_ram_base) & TARGET_PAGE_MASK;
1032
	int page1 = (line_end - phys_ram_base) & TARGET_PAGE_MASK;
1033
	int page;
1034

  
1035
	/* check dirty flags for each line */
1036
	for (page = page0; page <= page1; page += TARGET_PAGE_SIZE)
1037
	    if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG))
1038
		update = 1;
1039

  
1040
	/* draw line and change status */
1041
	if (update) {
1042
	    draw_line(&s->ds->data[y * width * dst_bpp], src, width, palette);
1043
	    if (y_start < 0)
1044
		y_start = y;
1045
	    if (page0 < page_min)
1046
		page_min = page0;
1047
	    if (page1 > page_max)
1048
		page_max = page1;
1049
	} else {
1050
	    if (y_start >= 0) {
1051
		/* flush to display */
1052
		dpy_update(s->ds, 0, y_start, width, y - y_start);
1053
		y_start = -1;
1054
	    }
1055
	}
1056

  
1057
	src += width * src_bpp;
1058
    }
1059

  
1060
    /* complete flush to display */
1061
    if (y_start >= 0)
1062
	dpy_update(s->ds, 0, y_start, width, y - y_start);
1063

  
1064
    /* clear dirty flags */
1065
    if (page_max != -1)
1066
	cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
1067
					VGA_DIRTY_FLAG);
1068
}
1069

  
1070
static void sm501_update_display(void *opaque)
1071
{
1072
    SM501State * s = (SM501State *)opaque;
1073

  
1074
    if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE)
1075
	sm501_draw_crt(s);
1076
}
1077

  
1078
void sm501_init(DisplayState *ds, uint32_t base, unsigned long local_mem_base,
1079
		uint32_t local_mem_bytes, CharDriverState *chr)
1080
{
1081
    SM501State * s;
1082
    int sm501_system_config_index;
1083
    int sm501_disp_ctrl_index;
1084
    int sm501_palette_index;
1085

  
1086
    /* allocate management data region */
1087
    s = (SM501State *)qemu_mallocz(sizeof(SM501State));
1088
    s->base = base;
1089
    s->local_mem_size_index
1090
	= get_local_mem_size_index(local_mem_bytes);
1091
    SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
1092
		  s->local_mem_size_index);
1093
    s->system_control = 0x00100000;
1094
    s->misc_control = 0x00001000; /* assumes SH, active=low */
1095
    s->dc_panel_control = 0x00010000;
1096
    s->dc_crt_control = 0x00010000;
1097
    s->ds = ds;
1098

  
1099
    /* allocate local memory */
1100
    s->local_mem = (uint8 *)phys_ram_base + local_mem_base;
1101
    cpu_register_physical_memory(base, local_mem_bytes, local_mem_base);
1102

  
1103
    /* map mmio */
1104
    sm501_system_config_index
1105
	= cpu_register_io_memory(0, sm501_system_config_readfn,
1106
				 sm501_system_config_writefn, s);
1107
    cpu_register_physical_memory(base + MMIO_BASE_OFFSET,
1108
				 0x6c, sm501_system_config_index);
1109
    sm501_disp_ctrl_index = cpu_register_io_memory(0, sm501_disp_ctrl_readfn,
1110
						   sm501_disp_ctrl_writefn, s);
1111
    cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_DC,
1112
				 0x400, sm501_disp_ctrl_index);
1113

  
1114
    sm501_palette_index = cpu_register_io_memory(0, sm501_palette_readfn,
1115
						   sm501_palette_writefn, s);
1116
    cpu_register_physical_memory(base + MMIO_BASE_OFFSET
1117
				 + SM501_DC + SM501_DC_PANEL_PALETTE,
1118
				 0x400 * 3, sm501_palette_index);
1119

  
1120
    /* bridge to serial emulation module */
1121
    if (chr)
1122
	serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
1123
		       0, /* TODO : chain irq to IRL */
1124
		       115200, chr, 1);
1125

  
1126
    /* create qemu graphic console */
1127
    s->console = graphic_console_init(s->ds, sm501_update_display, NULL,
1128
				      NULL, NULL, s);
1129
}
b/hw/sm501_template.h
1
/*
2
 * Pixel drawing function templates for QEMU SM501 Device
3
 *
4
 * Copyright (c) 2008 Shin-ichiro KAWASAKI
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
 * THE SOFTWARE.
23
 */
24

  
25
#if DEPTH == 8
26
#define BPP 1
27
#define PIXEL_TYPE uint8_t
28
#elif DEPTH == 15 || DEPTH == 16
29
#define BPP 2
30
#define PIXEL_TYPE uint16_t
31
#elif DEPTH == 32
32
#define BPP 4
33
#define PIXEL_TYPE uint32_t
34
#else
35
#error unsupport depth
36
#endif
37

  
38
#ifdef BGR_FORMAT
39
#define PIXEL_NAME glue(DEPTH, bgr)
40
#else
41
#define PIXEL_NAME DEPTH
42
#endif /* BGR_FORMAT */
43

  
44

  
45
static void glue(draw_line8_, PIXEL_NAME)(
46
                 uint8_t *d, const uint8_t *s, int width, const uint32_t *pal)
47
{
48
    uint8_t v, r, g, b;
49
    do {
50
      	v = ldub_raw(s);
51
	r = (pal[v] >> 16) & 0xff;
52
	g = (pal[v] >>  8) & 0xff;
53
	b = (pal[v] >>  0) & 0xff;
54
	((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
55
	s ++;
56
	d += BPP;
57
    } while (-- width != 0);
58
}
59

  
60
static void glue(draw_line16_, PIXEL_NAME)(
61
		 uint8_t *d, const uint8_t *s, int width, const uint32_t *pal)
62
{
63
    uint16_t rgb565;
64
    uint8_t r, g, b;
65

  
66
    do {
67
	rgb565 = lduw_raw(s);
68
	r = ((rgb565 >> 11) & 0x1f) << 3;
69
	g = ((rgb565 >>  5) & 0x3f) << 2;
70
	b = ((rgb565 >>  0) & 0x1f) << 3;
71
	((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
72
	s += 2;
73
	d += BPP;
74
    } while (-- width != 0);
75
}
76

  
77
static void glue(draw_line32_, PIXEL_NAME)(
78
		 uint8_t *d, const uint8_t *s, int width, const uint32_t *pal)
79
{
80
    uint8_t r, g, b;
81

  
82
    do {
83
	ldub_raw(s);
84
#if defined(TARGET_WORDS_BIGENDIAN)
85
        r = s[1];
86
        g = s[2];
87
        b = s[3];
88
#else
89
        b = s[0];
90
        g = s[1];
91
        r = s[2];
92
#endif
93
	((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
94
	s += 4;
95
	d += BPP;
96
    } while (-- width != 0);
97
}
98

  
99
#undef DEPTH
100
#undef BPP
101
#undef PIXEL_TYPE
102
#undef PIXEL_NAME
103
#undef BGR_FORMAT
104

  

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