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/*
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* QEMU SM501 Device
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*
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* Copyright (c) 2008 Shin-ichiro KAWASAKI
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h> |
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#include <assert.h> |
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#include "hw.h" |
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#include "pc.h" |
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#include "console.h" |
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/*
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* Status: 2008/11/02
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* - Minimum implementation for Linux console : mmio regs and CRT layer.
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* - Always updates full screen.
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*
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* TODO:
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* - Panel support
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* - Hardware cursor support
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* - Touch panel support
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* - USB support
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* - UART support
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* - Performance tuning
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*/
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//#define DEBUG_SM501
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//#define DEBUG_BITBLT
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#ifdef DEBUG_SM501
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#define SM501_DPRINTF(fmt...) printf(fmt)
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#else
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#define SM501_DPRINTF(fmt...) do {} while(0) |
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#endif
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#define MMIO_BASE_OFFSET 0x3e00000 |
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/* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
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/* System Configuration area */
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/* System config base */
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#define SM501_SYS_CONFIG (0x000000) |
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/* config 1 */
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#define SM501_SYSTEM_CONTROL (0x000000) |
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#define SM501_SYSCTRL_PANEL_TRISTATE (1<<0) |
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#define SM501_SYSCTRL_MEM_TRISTATE (1<<1) |
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#define SM501_SYSCTRL_CRT_TRISTATE (1<<2) |
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4) |
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4) |
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4) |
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4) |
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#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4) |
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#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6) |
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#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7) |
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#define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11) |
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#define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15) |
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/* miscellaneous control */
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#define SM501_MISC_CONTROL (0x000004) |
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#define SM501_MISC_BUS_SH (0x0) |
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#define SM501_MISC_BUS_PCI (0x1) |
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#define SM501_MISC_BUS_XSCALE (0x2) |
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#define SM501_MISC_BUS_NEC (0x6) |
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#define SM501_MISC_BUS_MASK (0x7) |
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#define SM501_MISC_VR_62MB (1<<3) |
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#define SM501_MISC_CDR_RESET (1<<7) |
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#define SM501_MISC_USB_LB (1<<8) |
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#define SM501_MISC_USB_SLAVE (1<<9) |
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#define SM501_MISC_BL_1 (1<<10) |
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#define SM501_MISC_MC (1<<11) |
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#define SM501_MISC_DAC_POWER (1<<12) |
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#define SM501_MISC_IRQ_INVERT (1<<16) |
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#define SM501_MISC_SH (1<<17) |
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#define SM501_MISC_HOLD_EMPTY (0<<18) |
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#define SM501_MISC_HOLD_8 (1<<18) |
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#define SM501_MISC_HOLD_16 (2<<18) |
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#define SM501_MISC_HOLD_24 (3<<18) |
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#define SM501_MISC_HOLD_32 (4<<18) |
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#define SM501_MISC_HOLD_MASK (7<<18) |
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#define SM501_MISC_FREQ_12 (1<<24) |
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#define SM501_MISC_PNL_24BIT (1<<25) |
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#define SM501_MISC_8051_LE (1<<26) |
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#define SM501_GPIO31_0_CONTROL (0x000008) |
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#define SM501_GPIO63_32_CONTROL (0x00000C) |
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#define SM501_DRAM_CONTROL (0x000010) |
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/* command list */
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#define SM501_ARBTRTN_CONTROL (0x000014) |
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/* command list */
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#define SM501_COMMAND_LIST_STATUS (0x000024) |
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/* interrupt debug */
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#define SM501_RAW_IRQ_STATUS (0x000028) |
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#define SM501_RAW_IRQ_CLEAR (0x000028) |
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#define SM501_IRQ_STATUS (0x00002C) |
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#define SM501_IRQ_MASK (0x000030) |
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#define SM501_DEBUG_CONTROL (0x000034) |
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/* power management */
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#define SM501_POWERMODE_P2X_SRC (1<<29) |
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#define SM501_POWERMODE_V2X_SRC (1<<20) |
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#define SM501_POWERMODE_M_SRC (1<<12) |
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#define SM501_POWERMODE_M1_SRC (1<<4) |
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#define SM501_CURRENT_GATE (0x000038) |
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#define SM501_CURRENT_CLOCK (0x00003C) |
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#define SM501_POWER_MODE_0_GATE (0x000040) |
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#define SM501_POWER_MODE_0_CLOCK (0x000044) |
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#define SM501_POWER_MODE_1_GATE (0x000048) |
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#define SM501_POWER_MODE_1_CLOCK (0x00004C) |
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#define SM501_SLEEP_MODE_GATE (0x000050) |
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#define SM501_POWER_MODE_CONTROL (0x000054) |
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/* power gates for units within the 501 */
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#define SM501_GATE_HOST (0) |
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#define SM501_GATE_MEMORY (1) |
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#define SM501_GATE_DISPLAY (2) |
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#define SM501_GATE_2D_ENGINE (3) |
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#define SM501_GATE_CSC (4) |
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#define SM501_GATE_ZVPORT (5) |
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#define SM501_GATE_GPIO (6) |
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#define SM501_GATE_UART0 (7) |
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#define SM501_GATE_UART1 (8) |
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#define SM501_GATE_SSP (10) |
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#define SM501_GATE_USB_HOST (11) |
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#define SM501_GATE_USB_GADGET (12) |
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#define SM501_GATE_UCONTROLLER (17) |
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#define SM501_GATE_AC97 (18) |
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/* panel clock */
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#define SM501_CLOCK_P2XCLK (24) |
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/* crt clock */
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#define SM501_CLOCK_V2XCLK (16) |
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/* main clock */
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#define SM501_CLOCK_MCLK (8) |
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/* SDRAM controller clock */
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#define SM501_CLOCK_M1XCLK (0) |
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/* config 2 */
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#define SM501_PCI_MASTER_BASE (0x000058) |
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#define SM501_ENDIAN_CONTROL (0x00005C) |
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#define SM501_DEVICEID (0x000060) |
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/* 0x050100A0 */
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#define SM501_DEVICEID_SM501 (0x05010000) |
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#define SM501_DEVICEID_IDMASK (0xffff0000) |
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#define SM501_DEVICEID_REVMASK (0x000000ff) |
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#define SM501_PLLCLOCK_COUNT (0x000064) |
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#define SM501_MISC_TIMING (0x000068) |
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#define SM501_CURRENT_SDRAM_CLOCK (0x00006C) |
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#define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074) |
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/* GPIO base */
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#define SM501_GPIO (0x010000) |
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#define SM501_GPIO_DATA_LOW (0x00) |
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#define SM501_GPIO_DATA_HIGH (0x04) |
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#define SM501_GPIO_DDR_LOW (0x08) |
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#define SM501_GPIO_DDR_HIGH (0x0C) |
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#define SM501_GPIO_IRQ_SETUP (0x10) |
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#define SM501_GPIO_IRQ_STATUS (0x14) |
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#define SM501_GPIO_IRQ_RESET (0x14) |
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/* I2C controller base */
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#define SM501_I2C (0x010040) |
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#define SM501_I2C_BYTE_COUNT (0x00) |
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#define SM501_I2C_CONTROL (0x01) |
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#define SM501_I2C_STATUS (0x02) |
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#define SM501_I2C_RESET (0x02) |
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#define SM501_I2C_SLAVE_ADDRESS (0x03) |
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#define SM501_I2C_DATA (0x04) |
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/* SSP base */
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#define SM501_SSP (0x020000) |
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/* Uart 0 base */
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#define SM501_UART0 (0x030000) |
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/* Uart 1 base */
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#define SM501_UART1 (0x030020) |
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/* USB host port base */
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#define SM501_USB_HOST (0x040000) |
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/* USB slave/gadget base */
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#define SM501_USB_GADGET (0x060000) |
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/* USB slave/gadget data port base */
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#define SM501_USB_GADGET_DATA (0x070000) |
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/* Display controller/video engine base */
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#define SM501_DC (0x080000) |
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/* common defines for the SM501 address registers */
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#define SM501_ADDR_FLIP (1<<31) |
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#define SM501_ADDR_EXT (1<<27) |
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#define SM501_ADDR_CS1 (1<<26) |
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#define SM501_ADDR_MASK (0x3f << 26) |
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#define SM501_FIFO_MASK (0x3 << 16) |
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#define SM501_FIFO_1 (0x0 << 16) |
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#define SM501_FIFO_3 (0x1 << 16) |
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#define SM501_FIFO_7 (0x2 << 16) |
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#define SM501_FIFO_11 (0x3 << 16) |
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/* common registers for panel and the crt */
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#define SM501_OFF_DC_H_TOT (0x000) |
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#define SM501_OFF_DC_V_TOT (0x008) |
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#define SM501_OFF_DC_H_SYNC (0x004) |
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#define SM501_OFF_DC_V_SYNC (0x00C) |
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#define SM501_DC_PANEL_CONTROL (0x000) |
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#define SM501_DC_PANEL_CONTROL_FPEN (1<<27) |
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#define SM501_DC_PANEL_CONTROL_BIAS (1<<26) |
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#define SM501_DC_PANEL_CONTROL_DATA (1<<25) |
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#define SM501_DC_PANEL_CONTROL_VDD (1<<24) |
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#define SM501_DC_PANEL_CONTROL_DP (1<<23) |
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#define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21) |
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#define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21) |
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#define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21) |
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#define SM501_DC_PANEL_CONTROL_DE (1<<20) |
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#define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18) |
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#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18) |
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#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18) |
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#define SM501_DC_PANEL_CONTROL_CP (1<<14) |
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#define SM501_DC_PANEL_CONTROL_VSP (1<<13) |
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#define SM501_DC_PANEL_CONTROL_HSP (1<<12) |
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#define SM501_DC_PANEL_CONTROL_CK (1<<9) |
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#define SM501_DC_PANEL_CONTROL_TE (1<<8) |
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#define SM501_DC_PANEL_CONTROL_VPD (1<<7) |
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#define SM501_DC_PANEL_CONTROL_VP (1<<6) |
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#define SM501_DC_PANEL_CONTROL_HPD (1<<5) |
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#define SM501_DC_PANEL_CONTROL_HP (1<<4) |
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#define SM501_DC_PANEL_CONTROL_GAMMA (1<<3) |
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#define SM501_DC_PANEL_CONTROL_EN (1<<2) |
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#define SM501_DC_PANEL_CONTROL_8BPP (0<<0) |
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#define SM501_DC_PANEL_CONTROL_16BPP (1<<0) |
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#define SM501_DC_PANEL_CONTROL_32BPP (2<<0) |
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#define SM501_DC_PANEL_PANNING_CONTROL (0x004) |
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#define SM501_DC_PANEL_COLOR_KEY (0x008) |
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#define SM501_DC_PANEL_FB_ADDR (0x00C) |
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#define SM501_DC_PANEL_FB_OFFSET (0x010) |
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#define SM501_DC_PANEL_FB_WIDTH (0x014) |
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#define SM501_DC_PANEL_FB_HEIGHT (0x018) |
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#define SM501_DC_PANEL_TL_LOC (0x01C) |
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#define SM501_DC_PANEL_BR_LOC (0x020) |
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#define SM501_DC_PANEL_H_TOT (0x024) |
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#define SM501_DC_PANEL_H_SYNC (0x028) |
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#define SM501_DC_PANEL_V_TOT (0x02C) |
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#define SM501_DC_PANEL_V_SYNC (0x030) |
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#define SM501_DC_PANEL_CUR_LINE (0x034) |
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#define SM501_DC_VIDEO_CONTROL (0x040) |
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#define SM501_DC_VIDEO_FB0_ADDR (0x044) |
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#define SM501_DC_VIDEO_FB_WIDTH (0x048) |
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#define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C) |
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#define SM501_DC_VIDEO_TL_LOC (0x050) |
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#define SM501_DC_VIDEO_BR_LOC (0x054) |
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#define SM501_DC_VIDEO_SCALE (0x058) |
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#define SM501_DC_VIDEO_INIT_SCALE (0x05C) |
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#define SM501_DC_VIDEO_YUV_CONSTANTS (0x060) |
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#define SM501_DC_VIDEO_FB1_ADDR (0x064) |
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#define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068) |
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#define SM501_DC_VIDEO_ALPHA_CONTROL (0x080) |
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#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084) |
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#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088) |
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#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C) |
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#define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090) |
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#define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094) |
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#define SM501_DC_VIDEO_ALPHA_SCALE (0x098) |
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#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C) |
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#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0) |
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#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4) |
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#define SM501_DC_PANEL_HWC_BASE (0x0F0) |
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#define SM501_DC_PANEL_HWC_ADDR (0x0F0) |
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#define SM501_DC_PANEL_HWC_LOC (0x0F4) |
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#define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8) |
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#define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC) |
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#define SM501_HWC_EN (1<<31) |
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#define SM501_OFF_HWC_ADDR (0x00) |
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#define SM501_OFF_HWC_LOC (0x04) |
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#define SM501_OFF_HWC_COLOR_1_2 (0x08) |
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#define SM501_OFF_HWC_COLOR_3 (0x0C) |
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#define SM501_DC_ALPHA_CONTROL (0x100) |
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#define SM501_DC_ALPHA_FB_ADDR (0x104) |
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#define SM501_DC_ALPHA_FB_OFFSET (0x108) |
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#define SM501_DC_ALPHA_TL_LOC (0x10C) |
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#define SM501_DC_ALPHA_BR_LOC (0x110) |
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#define SM501_DC_ALPHA_CHROMA_KEY (0x114) |
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#define SM501_DC_ALPHA_COLOR_LOOKUP (0x118) |
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#define SM501_DC_CRT_CONTROL (0x200) |
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#define SM501_DC_CRT_CONTROL_TVP (1<<15) |
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#define SM501_DC_CRT_CONTROL_CP (1<<14) |
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#define SM501_DC_CRT_CONTROL_VSP (1<<13) |
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#define SM501_DC_CRT_CONTROL_HSP (1<<12) |
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#define SM501_DC_CRT_CONTROL_VS (1<<11) |
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#define SM501_DC_CRT_CONTROL_BLANK (1<<10) |
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#define SM501_DC_CRT_CONTROL_SEL (1<<9) |
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#define SM501_DC_CRT_CONTROL_TE (1<<8) |
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#define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) |
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#define SM501_DC_CRT_CONTROL_GAMMA (1<<3) |
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#define SM501_DC_CRT_CONTROL_ENABLE (1<<2) |
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#define SM501_DC_CRT_CONTROL_8BPP (0<<0) |
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#define SM501_DC_CRT_CONTROL_16BPP (1<<0) |
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#define SM501_DC_CRT_CONTROL_32BPP (2<<0) |
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#define SM501_DC_CRT_FB_ADDR (0x204) |
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#define SM501_DC_CRT_FB_OFFSET (0x208) |
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#define SM501_DC_CRT_H_TOT (0x20C) |
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#define SM501_DC_CRT_H_SYNC (0x210) |
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#define SM501_DC_CRT_V_TOT (0x214) |
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#define SM501_DC_CRT_V_SYNC (0x218) |
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#define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C) |
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#define SM501_DC_CRT_CUR_LINE (0x220) |
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#define SM501_DC_CRT_MONITOR_DETECT (0x224) |
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#define SM501_DC_CRT_HWC_BASE (0x230) |
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#define SM501_DC_CRT_HWC_ADDR (0x230) |
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#define SM501_DC_CRT_HWC_LOC (0x234) |
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#define SM501_DC_CRT_HWC_COLOR_1_2 (0x238) |
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#define SM501_DC_CRT_HWC_COLOR_3 (0x23C) |
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#define SM501_DC_PANEL_PALETTE (0x400) |
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#define SM501_DC_VIDEO_PALETTE (0x800) |
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#define SM501_DC_CRT_PALETTE (0xC00) |
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/* Zoom Video port base */
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#define SM501_ZVPORT (0x090000) |
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/* AC97/I2S base */
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#define SM501_AC97 (0x0A0000) |
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/* 8051 micro controller base */
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#define SM501_UCONTROLLER (0x0B0000) |
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/* 8051 micro controller SRAM base */
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#define SM501_UCONTROLLER_SRAM (0x0C0000) |
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/* DMA base */
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#define SM501_DMA (0x0D0000) |
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/* 2d engine base */
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#define SM501_2D_ENGINE (0x100000) |
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#define SM501_2D_SOURCE (0x00) |
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#define SM501_2D_DESTINATION (0x04) |
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#define SM501_2D_DIMENSION (0x08) |
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#define SM501_2D_CONTROL (0x0C) |
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#define SM501_2D_PITCH (0x10) |
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#define SM501_2D_FOREGROUND (0x14) |
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#define SM501_2D_BACKGROUND (0x18) |
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#define SM501_2D_STRETCH (0x1C) |
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#define SM501_2D_COLOR_COMPARE (0x20) |
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#define SM501_2D_COLOR_COMPARE_MASK (0x24) |
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#define SM501_2D_MASK (0x28) |
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#define SM501_2D_CLIP_TL (0x2C) |
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#define SM501_2D_CLIP_BR (0x30) |
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#define SM501_2D_MONO_PATTERN_LOW (0x34) |
409 |
#define SM501_2D_MONO_PATTERN_HIGH (0x38) |
410 |
#define SM501_2D_WINDOW_WIDTH (0x3C) |
411 |
#define SM501_2D_SOURCE_BASE (0x40) |
412 |
#define SM501_2D_DESTINATION_BASE (0x44) |
413 |
#define SM501_2D_ALPHA (0x48) |
414 |
#define SM501_2D_WRAP (0x4C) |
415 |
#define SM501_2D_STATUS (0x50) |
416 |
|
417 |
#define SM501_CSC_Y_SOURCE_BASE (0xC8) |
418 |
#define SM501_CSC_CONSTANTS (0xCC) |
419 |
#define SM501_CSC_Y_SOURCE_X (0xD0) |
420 |
#define SM501_CSC_Y_SOURCE_Y (0xD4) |
421 |
#define SM501_CSC_U_SOURCE_BASE (0xD8) |
422 |
#define SM501_CSC_V_SOURCE_BASE (0xDC) |
423 |
#define SM501_CSC_SOURCE_DIMENSION (0xE0) |
424 |
#define SM501_CSC_SOURCE_PITCH (0xE4) |
425 |
#define SM501_CSC_DESTINATION (0xE8) |
426 |
#define SM501_CSC_DESTINATION_DIMENSION (0xEC) |
427 |
#define SM501_CSC_DESTINATION_PITCH (0xF0) |
428 |
#define SM501_CSC_SCALE_FACTOR (0xF4) |
429 |
#define SM501_CSC_DESTINATION_BASE (0xF8) |
430 |
#define SM501_CSC_CONTROL (0xFC) |
431 |
|
432 |
/* 2d engine data port base */
|
433 |
#define SM501_2D_ENGINE_DATA (0x110000) |
434 |
|
435 |
/* end of register definitions */
|
436 |
|
437 |
|
438 |
/* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
|
439 |
static const uint32_t sm501_mem_local_size[] = { |
440 |
[0] = 4*1024*1024, |
441 |
[1] = 8*1024*1024, |
442 |
[2] = 16*1024*1024, |
443 |
[3] = 32*1024*1024, |
444 |
[4] = 64*1024*1024, |
445 |
[5] = 2*1024*1024, |
446 |
}; |
447 |
#define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
|
448 |
|
449 |
typedef struct SM501State { |
450 |
/* graphic console status */
|
451 |
DisplayState *ds; |
452 |
QEMUConsole *console; |
453 |
|
454 |
/* status & internal resources */
|
455 |
target_phys_addr_t base; |
456 |
uint32_t local_mem_size_index; |
457 |
uint8_t * local_mem; |
458 |
uint32_t last_width; |
459 |
uint32_t last_height; |
460 |
|
461 |
/* mmio registers */
|
462 |
uint32_t system_control; |
463 |
uint32_t misc_control; |
464 |
uint32_t gpio_31_0_control; |
465 |
uint32_t gpio_63_32_control; |
466 |
uint32_t dram_control; |
467 |
uint32_t irq_mask; |
468 |
uint32_t misc_timing; |
469 |
uint32_t power_mode_control; |
470 |
|
471 |
uint32_t uart0_ier; |
472 |
uint32_t uart0_lcr; |
473 |
uint32_t uart0_mcr; |
474 |
uint32_t uart0_scr; |
475 |
|
476 |
uint8_t dc_palette[0x400 * 3]; |
477 |
|
478 |
uint32_t dc_panel_control; |
479 |
uint32_t dc_panel_panning_control; |
480 |
uint32_t dc_panel_fb_addr; |
481 |
uint32_t dc_panel_fb_offset; |
482 |
uint32_t dc_panel_fb_width; |
483 |
uint32_t dc_panel_fb_height; |
484 |
uint32_t dc_panel_tl_location; |
485 |
uint32_t dc_panel_br_location; |
486 |
uint32_t dc_panel_h_total; |
487 |
uint32_t dc_panel_h_sync; |
488 |
uint32_t dc_panel_v_total; |
489 |
uint32_t dc_panel_v_sync; |
490 |
|
491 |
uint32_t dc_panel_hwc_addr; |
492 |
uint32_t dc_panel_hwc_location; |
493 |
uint32_t dc_panel_hwc_color_1_2; |
494 |
uint32_t dc_panel_hwc_color_3; |
495 |
|
496 |
uint32_t dc_crt_control; |
497 |
uint32_t dc_crt_fb_addr; |
498 |
uint32_t dc_crt_fb_offset; |
499 |
uint32_t dc_crt_h_total; |
500 |
uint32_t dc_crt_h_sync; |
501 |
uint32_t dc_crt_v_total; |
502 |
uint32_t dc_crt_v_sync; |
503 |
|
504 |
uint32_t dc_crt_hwc_addr; |
505 |
uint32_t dc_crt_hwc_location; |
506 |
uint32_t dc_crt_hwc_color_1_2; |
507 |
uint32_t dc_crt_hwc_color_3; |
508 |
|
509 |
} SM501State; |
510 |
|
511 |
static uint32_t get_local_mem_size_index(uint32_t size)
|
512 |
{ |
513 |
uint32_t norm_size = 0;
|
514 |
int i, index = 0; |
515 |
|
516 |
for (i = 0; i < sizeof(sm501_mem_local_size)/sizeof(uint32_t); i++) { |
517 |
uint32_t new_size = sm501_mem_local_size[i]; |
518 |
if (new_size >= size) {
|
519 |
if (norm_size == 0 || norm_size > new_size) { |
520 |
norm_size = new_size; |
521 |
index = i; |
522 |
} |
523 |
} |
524 |
} |
525 |
|
526 |
return index;
|
527 |
} |
528 |
|
529 |
static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr) |
530 |
{ |
531 |
SM501State * s = (SM501State *)opaque; |
532 |
uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET); |
533 |
uint32_t ret = 0;
|
534 |
SM501_DPRINTF("sm501 system config regs : read addr=%x, offset=%x\n",
|
535 |
addr, offset); |
536 |
|
537 |
switch(offset) {
|
538 |
case SM501_SYSTEM_CONTROL:
|
539 |
ret = s->system_control; |
540 |
break;
|
541 |
case SM501_MISC_CONTROL:
|
542 |
ret = s->misc_control; |
543 |
break;
|
544 |
case SM501_GPIO31_0_CONTROL:
|
545 |
ret = s->gpio_31_0_control; |
546 |
break;
|
547 |
case SM501_GPIO63_32_CONTROL:
|
548 |
ret = s->gpio_63_32_control; |
549 |
break;
|
550 |
case SM501_DEVICEID:
|
551 |
ret = 0x050100A0;
|
552 |
break;
|
553 |
case SM501_DRAM_CONTROL:
|
554 |
ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13; |
555 |
break;
|
556 |
case SM501_IRQ_MASK:
|
557 |
ret = s->irq_mask; |
558 |
break;
|
559 |
case SM501_MISC_TIMING:
|
560 |
/* TODO : simulate gate control */
|
561 |
ret = s->misc_timing; |
562 |
break;
|
563 |
case SM501_CURRENT_GATE:
|
564 |
/* TODO : simulate gate control */
|
565 |
ret = 0x00021807;
|
566 |
break;
|
567 |
case SM501_CURRENT_CLOCK:
|
568 |
ret = 0x2A1A0A09;
|
569 |
break;
|
570 |
case SM501_POWER_MODE_CONTROL:
|
571 |
ret = s->power_mode_control; |
572 |
break;
|
573 |
|
574 |
default:
|
575 |
printf("sm501 system config : not implemented register read."
|
576 |
" addr=%x, offset=%x\n", addr, offset);
|
577 |
assert(0);
|
578 |
} |
579 |
|
580 |
return ret;
|
581 |
} |
582 |
|
583 |
static void sm501_system_config_write(void *opaque, |
584 |
target_phys_addr_t addr, uint32_t value) |
585 |
{ |
586 |
SM501State * s = (SM501State *)opaque; |
587 |
uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET); |
588 |
SM501_DPRINTF("sm501 system config regs : write addr=%x, ofs=%x, val=%x\n",
|
589 |
addr, offset, value); |
590 |
|
591 |
switch(offset) {
|
592 |
case SM501_SYSTEM_CONTROL:
|
593 |
s->system_control = value & 0xE300B8F7;
|
594 |
break;
|
595 |
case SM501_MISC_CONTROL:
|
596 |
s->misc_control = value & 0xFF7FFF20;
|
597 |
break;
|
598 |
case SM501_GPIO31_0_CONTROL:
|
599 |
s->gpio_31_0_control = value; |
600 |
break;
|
601 |
case SM501_GPIO63_32_CONTROL:
|
602 |
s->gpio_63_32_control = value; |
603 |
break;
|
604 |
case SM501_DRAM_CONTROL:
|
605 |
s->local_mem_size_index = (value >> 13) & 0x7; |
606 |
/* rODO : check validity of size change */
|
607 |
s->dram_control |= value & 0x7FFFFFC3;
|
608 |
break;
|
609 |
case SM501_IRQ_MASK:
|
610 |
s->irq_mask = value; |
611 |
break;
|
612 |
case SM501_MISC_TIMING:
|
613 |
s->misc_timing = value & 0xF31F1FFF;
|
614 |
break;
|
615 |
case SM501_POWER_MODE_0_GATE:
|
616 |
case SM501_POWER_MODE_1_GATE:
|
617 |
case SM501_POWER_MODE_0_CLOCK:
|
618 |
case SM501_POWER_MODE_1_CLOCK:
|
619 |
/* TODO : simulate gate & clock control */
|
620 |
break;
|
621 |
case SM501_POWER_MODE_CONTROL:
|
622 |
s->power_mode_control = value & 0x00000003;
|
623 |
break;
|
624 |
|
625 |
default:
|
626 |
printf("sm501 system config : not implemented register write."
|
627 |
" addr=%x, val=%x\n", addr, value);
|
628 |
assert(0);
|
629 |
} |
630 |
} |
631 |
|
632 |
static CPUReadMemoryFunc *sm501_system_config_readfn[] = {
|
633 |
NULL,
|
634 |
NULL,
|
635 |
&sm501_system_config_read, |
636 |
}; |
637 |
|
638 |
static CPUWriteMemoryFunc *sm501_system_config_writefn[] = {
|
639 |
NULL,
|
640 |
NULL,
|
641 |
&sm501_system_config_write, |
642 |
}; |
643 |
|
644 |
static uint32_t sm501_disp_ctrl_read(void *opaque, |
645 |
target_phys_addr_t addr) |
646 |
{ |
647 |
SM501State * s = (SM501State *)opaque; |
648 |
uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET + SM501_DC); |
649 |
uint32_t ret = 0;
|
650 |
SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x, offset=%x\n",
|
651 |
addr, offset); |
652 |
|
653 |
switch(offset) {
|
654 |
|
655 |
case SM501_DC_PANEL_CONTROL:
|
656 |
ret = s->dc_panel_control; |
657 |
break;
|
658 |
case SM501_DC_PANEL_PANNING_CONTROL:
|
659 |
ret = s->dc_panel_panning_control; |
660 |
break;
|
661 |
case SM501_DC_PANEL_FB_ADDR:
|
662 |
ret = s->dc_panel_fb_addr; |
663 |
break;
|
664 |
case SM501_DC_PANEL_FB_OFFSET:
|
665 |
ret = s->dc_panel_fb_offset; |
666 |
break;
|
667 |
case SM501_DC_PANEL_FB_WIDTH:
|
668 |
ret = s->dc_panel_fb_width; |
669 |
break;
|
670 |
case SM501_DC_PANEL_FB_HEIGHT:
|
671 |
ret = s->dc_panel_fb_height; |
672 |
break;
|
673 |
case SM501_DC_PANEL_TL_LOC:
|
674 |
ret = s->dc_panel_tl_location; |
675 |
break;
|
676 |
case SM501_DC_PANEL_BR_LOC:
|
677 |
ret = s->dc_panel_br_location; |
678 |
break;
|
679 |
|
680 |
case SM501_DC_PANEL_H_TOT:
|
681 |
ret = s->dc_panel_h_total; |
682 |
break;
|
683 |
case SM501_DC_PANEL_H_SYNC:
|
684 |
ret = s->dc_panel_h_sync; |
685 |
break;
|
686 |
case SM501_DC_PANEL_V_TOT:
|
687 |
ret = s->dc_panel_v_total; |
688 |
break;
|
689 |
case SM501_DC_PANEL_V_SYNC:
|
690 |
ret = s->dc_panel_v_sync; |
691 |
break;
|
692 |
|
693 |
case SM501_DC_CRT_CONTROL:
|
694 |
ret = s->dc_crt_control; |
695 |
break;
|
696 |
case SM501_DC_CRT_FB_ADDR:
|
697 |
ret = s->dc_crt_fb_addr; |
698 |
break;
|
699 |
case SM501_DC_CRT_FB_OFFSET:
|
700 |
ret = s->dc_crt_fb_offset; |
701 |
break;
|
702 |
case SM501_DC_CRT_H_TOT:
|
703 |
ret = s->dc_crt_h_total; |
704 |
break;
|
705 |
case SM501_DC_CRT_H_SYNC:
|
706 |
ret = s->dc_crt_h_sync; |
707 |
break;
|
708 |
case SM501_DC_CRT_V_TOT:
|
709 |
ret = s->dc_crt_v_total; |
710 |
break;
|
711 |
case SM501_DC_CRT_V_SYNC:
|
712 |
ret = s->dc_crt_v_sync; |
713 |
break;
|
714 |
|
715 |
case SM501_DC_CRT_HWC_ADDR:
|
716 |
ret = s->dc_crt_hwc_addr; |
717 |
break;
|
718 |
case SM501_DC_CRT_HWC_LOC:
|
719 |
ret = s->dc_crt_hwc_addr; |
720 |
break;
|
721 |
case SM501_DC_CRT_HWC_COLOR_1_2:
|
722 |
ret = s->dc_crt_hwc_addr; |
723 |
break;
|
724 |
case SM501_DC_CRT_HWC_COLOR_3:
|
725 |
ret = s->dc_crt_hwc_addr; |
726 |
break;
|
727 |
|
728 |
default:
|
729 |
printf("sm501 disp ctrl : not implemented register read."
|
730 |
" addr=%x, offset=%x\n", addr, offset);
|
731 |
assert(0);
|
732 |
} |
733 |
|
734 |
return ret;
|
735 |
} |
736 |
|
737 |
static void sm501_disp_ctrl_write(void *opaque, |
738 |
target_phys_addr_t addr, |
739 |
uint32_t value) |
740 |
{ |
741 |
SM501State * s = (SM501State *)opaque; |
742 |
uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET + SM501_DC); |
743 |
SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, ofs=%x, val=%x\n",
|
744 |
addr, offset, value); |
745 |
|
746 |
switch(offset) {
|
747 |
case SM501_DC_PANEL_CONTROL:
|
748 |
s->dc_panel_control = value & 0x0FFF73FF;
|
749 |
break;
|
750 |
case SM501_DC_PANEL_PANNING_CONTROL:
|
751 |
s->dc_panel_panning_control = value & 0xFF3FFF3F;
|
752 |
break;
|
753 |
case SM501_DC_PANEL_FB_ADDR:
|
754 |
s->dc_panel_fb_addr = value & 0x8FFFFFF0;
|
755 |
break;
|
756 |
case SM501_DC_PANEL_FB_OFFSET:
|
757 |
s->dc_panel_fb_offset = value & 0x3FF03FF0;
|
758 |
break;
|
759 |
case SM501_DC_PANEL_FB_WIDTH:
|
760 |
s->dc_panel_fb_width = value & 0x0FFF0FFF;
|
761 |
break;
|
762 |
case SM501_DC_PANEL_FB_HEIGHT:
|
763 |
s->dc_panel_fb_height = value & 0x0FFF0FFF;
|
764 |
break;
|
765 |
case SM501_DC_PANEL_TL_LOC:
|
766 |
s->dc_panel_tl_location = value & 0x07FF07FF;
|
767 |
break;
|
768 |
case SM501_DC_PANEL_BR_LOC:
|
769 |
s->dc_panel_br_location = value & 0x07FF07FF;
|
770 |
break;
|
771 |
|
772 |
case SM501_DC_PANEL_H_TOT:
|
773 |
s->dc_panel_h_total = value & 0x0FFF0FFF;
|
774 |
break;
|
775 |
case SM501_DC_PANEL_H_SYNC:
|
776 |
s->dc_panel_h_sync = value & 0x00FF0FFF;
|
777 |
break;
|
778 |
case SM501_DC_PANEL_V_TOT:
|
779 |
s->dc_panel_v_total = value & 0x0FFF0FFF;
|
780 |
break;
|
781 |
case SM501_DC_PANEL_V_SYNC:
|
782 |
s->dc_panel_v_sync = value & 0x003F0FFF;
|
783 |
break;
|
784 |
|
785 |
case SM501_DC_PANEL_HWC_ADDR:
|
786 |
s->dc_panel_hwc_addr = value & 0x8FFFFFF0;
|
787 |
break;
|
788 |
case SM501_DC_PANEL_HWC_LOC:
|
789 |
s->dc_panel_hwc_addr = value & 0x0FFF0FFF;
|
790 |
break;
|
791 |
case SM501_DC_PANEL_HWC_COLOR_1_2:
|
792 |
s->dc_panel_hwc_addr = value; |
793 |
break;
|
794 |
case SM501_DC_PANEL_HWC_COLOR_3:
|
795 |
s->dc_panel_hwc_addr = value & 0x0000FFFF;
|
796 |
break;
|
797 |
|
798 |
case SM501_DC_CRT_CONTROL:
|
799 |
s->dc_crt_control = value & 0x0003FFFF;
|
800 |
break;
|
801 |
case SM501_DC_CRT_FB_ADDR:
|
802 |
s->dc_crt_fb_addr = value & 0x8FFFFFF0;
|
803 |
break;
|
804 |
case SM501_DC_CRT_FB_OFFSET:
|
805 |
s->dc_crt_fb_offset = value & 0x3FF03FF0;
|
806 |
break;
|
807 |
case SM501_DC_CRT_H_TOT:
|
808 |
s->dc_crt_h_total = value & 0x0FFF0FFF;
|
809 |
break;
|
810 |
case SM501_DC_CRT_H_SYNC:
|
811 |
s->dc_crt_h_sync = value & 0x00FF0FFF;
|
812 |
break;
|
813 |
case SM501_DC_CRT_V_TOT:
|
814 |
s->dc_crt_v_total = value & 0x0FFF0FFF;
|
815 |
break;
|
816 |
case SM501_DC_CRT_V_SYNC:
|
817 |
s->dc_crt_v_sync = value & 0x003F0FFF;
|
818 |
break;
|
819 |
|
820 |
case SM501_DC_CRT_HWC_ADDR:
|
821 |
s->dc_crt_hwc_addr = value & 0x8FFFFFF0;
|
822 |
break;
|
823 |
case SM501_DC_CRT_HWC_LOC:
|
824 |
s->dc_crt_hwc_addr = value & 0x0FFF0FFF;
|
825 |
break;
|
826 |
case SM501_DC_CRT_HWC_COLOR_1_2:
|
827 |
s->dc_crt_hwc_addr = value; |
828 |
break;
|
829 |
case SM501_DC_CRT_HWC_COLOR_3:
|
830 |
s->dc_crt_hwc_addr = value & 0x0000FFFF;
|
831 |
break;
|
832 |
|
833 |
default:
|
834 |
printf("sm501 disp ctrl : not implemented register write."
|
835 |
" addr=%x, val=%x\n", addr, value);
|
836 |
assert(0);
|
837 |
} |
838 |
} |
839 |
|
840 |
static CPUReadMemoryFunc *sm501_disp_ctrl_readfn[] = {
|
841 |
NULL,
|
842 |
NULL,
|
843 |
&sm501_disp_ctrl_read, |
844 |
}; |
845 |
|
846 |
static CPUWriteMemoryFunc *sm501_disp_ctrl_writefn[] = {
|
847 |
NULL,
|
848 |
NULL,
|
849 |
&sm501_disp_ctrl_write, |
850 |
}; |
851 |
|
852 |
static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr) |
853 |
{ |
854 |
SM501State * s = (SM501State *)opaque; |
855 |
uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET |
856 |
+ SM501_DC + SM501_DC_PANEL_PALETTE); |
857 |
SM501_DPRINTF("sm501 palette read addr=%x, offset=%x\n", addr, offset);
|
858 |
|
859 |
/* TODO : consider BYTE/WORD access */
|
860 |
/* TODO : consider endian */
|
861 |
|
862 |
assert(0 <= offset && offset < 0x400 * 3); |
863 |
return *(uint32_t*)&s->dc_palette[offset];
|
864 |
} |
865 |
|
866 |
static void sm501_palette_write(void *opaque, |
867 |
target_phys_addr_t addr, uint32_t value) |
868 |
{ |
869 |
SM501State * s = (SM501State *)opaque; |
870 |
uint32_t offset = addr - (s->base + MMIO_BASE_OFFSET |
871 |
+ SM501_DC + SM501_DC_PANEL_PALETTE); |
872 |
SM501_DPRINTF("sm501 palette write addr=%x, ofs=%x, val=%x\n",
|
873 |
addr, offset, value); |
874 |
|
875 |
/* TODO : consider BYTE/WORD access */
|
876 |
/* TODO : consider endian */
|
877 |
|
878 |
assert(0 <= offset && offset < 0x400 * 3); |
879 |
*(uint32_t*)&s->dc_palette[offset] = value; |
880 |
} |
881 |
|
882 |
static CPUReadMemoryFunc *sm501_palette_readfn[] = {
|
883 |
&sm501_palette_read, |
884 |
&sm501_palette_read, |
885 |
&sm501_palette_read, |
886 |
}; |
887 |
|
888 |
static CPUWriteMemoryFunc *sm501_palette_writefn[] = {
|
889 |
&sm501_palette_write, |
890 |
&sm501_palette_write, |
891 |
&sm501_palette_write, |
892 |
}; |
893 |
|
894 |
|
895 |
/* draw line functions for all console modes */
|
896 |
|
897 |
#include "pixel_ops.h" |
898 |
|
899 |
typedef void draw_line_func(uint8_t *d, const uint8_t *s, |
900 |
int width, const uint32_t *pal); |
901 |
|
902 |
#define DEPTH 8 |
903 |
#include "sm501_template.h" |
904 |
|
905 |
#define DEPTH 15 |
906 |
#include "sm501_template.h" |
907 |
|
908 |
#define BGR_FORMAT
|
909 |
#define DEPTH 15 |
910 |
#include "sm501_template.h" |
911 |
|
912 |
#define DEPTH 16 |
913 |
#include "sm501_template.h" |
914 |
|
915 |
#define BGR_FORMAT
|
916 |
#define DEPTH 16 |
917 |
#include "sm501_template.h" |
918 |
|
919 |
#define DEPTH 32 |
920 |
#include "sm501_template.h" |
921 |
|
922 |
#define BGR_FORMAT
|
923 |
#define DEPTH 32 |
924 |
#include "sm501_template.h" |
925 |
|
926 |
static draw_line_func * draw_line8_funcs[] = {
|
927 |
draw_line8_8, |
928 |
draw_line8_15, |
929 |
draw_line8_16, |
930 |
draw_line8_32, |
931 |
draw_line8_32bgr, |
932 |
draw_line8_15bgr, |
933 |
draw_line8_16bgr, |
934 |
}; |
935 |
|
936 |
static draw_line_func * draw_line16_funcs[] = {
|
937 |
draw_line16_8, |
938 |
draw_line16_15, |
939 |
draw_line16_16, |
940 |
draw_line16_32, |
941 |
draw_line16_32bgr, |
942 |
draw_line16_15bgr, |
943 |
draw_line16_16bgr, |
944 |
}; |
945 |
|
946 |
static draw_line_func * draw_line32_funcs[] = {
|
947 |
draw_line32_8, |
948 |
draw_line32_15, |
949 |
draw_line32_16, |
950 |
draw_line32_32, |
951 |
draw_line32_32bgr, |
952 |
draw_line32_15bgr, |
953 |
draw_line32_16bgr, |
954 |
}; |
955 |
|
956 |
static inline int get_depth_index(DisplayState *s) |
957 |
{ |
958 |
switch(s->depth) {
|
959 |
default:
|
960 |
case 8: |
961 |
return 0; |
962 |
case 15: |
963 |
if (s->bgr)
|
964 |
return 5; |
965 |
else
|
966 |
return 1; |
967 |
case 16: |
968 |
if (s->bgr)
|
969 |
return 6; |
970 |
else
|
971 |
return 2; |
972 |
case 32: |
973 |
if (s->bgr)
|
974 |
return 4; |
975 |
else
|
976 |
return 3; |
977 |
} |
978 |
} |
979 |
|
980 |
static void sm501_draw_crt(SM501State * s) |
981 |
{ |
982 |
int y;
|
983 |
int width = (s->dc_crt_h_total & 0x00000FFF) + 1; |
984 |
int height = (s->dc_crt_v_total & 0x00000FFF) + 1; |
985 |
|
986 |
uint8_t * src = s->local_mem; |
987 |
int src_bpp = 0; |
988 |
int dst_bpp = s->ds->depth / 8 + (s->ds->depth % 8 ? 1 : 0); |
989 |
uint32_t * palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE |
990 |
- SM501_DC_PANEL_PALETTE]; |
991 |
int ds_depth_index = get_depth_index(s->ds);
|
992 |
draw_line_func * draw_line = NULL;
|
993 |
int full_update = 0; |
994 |
int y_start = -1; |
995 |
int page_min = 0x7fffffff; |
996 |
int page_max = -1; |
997 |
|
998 |
/* choose draw_line function */
|
999 |
switch (s->dc_crt_control & 3) { |
1000 |
case SM501_DC_CRT_CONTROL_8BPP:
|
1001 |
src_bpp = 1;
|
1002 |
draw_line = draw_line8_funcs[ds_depth_index]; |
1003 |
break;
|
1004 |
case SM501_DC_CRT_CONTROL_16BPP:
|
1005 |
src_bpp = 2;
|
1006 |
draw_line = draw_line16_funcs[ds_depth_index]; |
1007 |
break;
|
1008 |
case SM501_DC_CRT_CONTROL_32BPP:
|
1009 |
src_bpp = 4;
|
1010 |
draw_line = draw_line32_funcs[ds_depth_index]; |
1011 |
break;
|
1012 |
default:
|
1013 |
printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
|
1014 |
s->dc_crt_control); |
1015 |
assert(0);
|
1016 |
break;
|
1017 |
} |
1018 |
|
1019 |
/* adjust console size */
|
1020 |
if (s->last_width != width || s->last_height != height) {
|
1021 |
qemu_console_resize(s->console, width, height); |
1022 |
s->last_width = width; |
1023 |
s->last_height = height; |
1024 |
full_update = 1;
|
1025 |
} |
1026 |
|
1027 |
/* draw each line according to conditions */
|
1028 |
for (y = 0; y < height; y++) { |
1029 |
int update = full_update;
|
1030 |
uint8_t * line_end = &src[width * src_bpp - 1];
|
1031 |
int page0 = (src - phys_ram_base) & TARGET_PAGE_MASK;
|
1032 |
int page1 = (line_end - phys_ram_base) & TARGET_PAGE_MASK;
|
1033 |
int page;
|
1034 |
|
1035 |
/* check dirty flags for each line */
|
1036 |
for (page = page0; page <= page1; page += TARGET_PAGE_SIZE)
|
1037 |
if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG))
|
1038 |
update = 1;
|
1039 |
|
1040 |
/* draw line and change status */
|
1041 |
if (update) {
|
1042 |
draw_line(&s->ds->data[y * width * dst_bpp], src, width, palette); |
1043 |
if (y_start < 0) |
1044 |
y_start = y; |
1045 |
if (page0 < page_min)
|
1046 |
page_min = page0; |
1047 |
if (page1 > page_max)
|
1048 |
page_max = page1; |
1049 |
} else {
|
1050 |
if (y_start >= 0) { |
1051 |
/* flush to display */
|
1052 |
dpy_update(s->ds, 0, y_start, width, y - y_start);
|
1053 |
y_start = -1;
|
1054 |
} |
1055 |
} |
1056 |
|
1057 |
src += width * src_bpp; |
1058 |
} |
1059 |
|
1060 |
/* complete flush to display */
|
1061 |
if (y_start >= 0) |
1062 |
dpy_update(s->ds, 0, y_start, width, y - y_start);
|
1063 |
|
1064 |
/* clear dirty flags */
|
1065 |
if (page_max != -1) |
1066 |
cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
1067 |
VGA_DIRTY_FLAG); |
1068 |
} |
1069 |
|
1070 |
static void sm501_update_display(void *opaque) |
1071 |
{ |
1072 |
SM501State * s = (SM501State *)opaque; |
1073 |
|
1074 |
if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE)
|
1075 |
sm501_draw_crt(s); |
1076 |
} |
1077 |
|
1078 |
void sm501_init(DisplayState *ds, uint32_t base, unsigned long local_mem_base, |
1079 |
uint32_t local_mem_bytes, CharDriverState *chr) |
1080 |
{ |
1081 |
SM501State * s; |
1082 |
int sm501_system_config_index;
|
1083 |
int sm501_disp_ctrl_index;
|
1084 |
int sm501_palette_index;
|
1085 |
|
1086 |
/* allocate management data region */
|
1087 |
s = (SM501State *)qemu_mallocz(sizeof(SM501State));
|
1088 |
s->base = base; |
1089 |
s->local_mem_size_index |
1090 |
= get_local_mem_size_index(local_mem_bytes); |
1091 |
SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
|
1092 |
s->local_mem_size_index); |
1093 |
s->system_control = 0x00100000;
|
1094 |
s->misc_control = 0x00001000; /* assumes SH, active=low */ |
1095 |
s->dc_panel_control = 0x00010000;
|
1096 |
s->dc_crt_control = 0x00010000;
|
1097 |
s->ds = ds; |
1098 |
|
1099 |
/* allocate local memory */
|
1100 |
s->local_mem = (uint8 *)phys_ram_base + local_mem_base; |
1101 |
cpu_register_physical_memory(base, local_mem_bytes, local_mem_base); |
1102 |
|
1103 |
/* map mmio */
|
1104 |
sm501_system_config_index |
1105 |
= cpu_register_io_memory(0, sm501_system_config_readfn,
|
1106 |
sm501_system_config_writefn, s); |
1107 |
cpu_register_physical_memory(base + MMIO_BASE_OFFSET, |
1108 |
0x6c, sm501_system_config_index);
|
1109 |
sm501_disp_ctrl_index = cpu_register_io_memory(0, sm501_disp_ctrl_readfn,
|
1110 |
sm501_disp_ctrl_writefn, s); |
1111 |
cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_DC, |
1112 |
0x400, sm501_disp_ctrl_index);
|
1113 |
|
1114 |
sm501_palette_index = cpu_register_io_memory(0, sm501_palette_readfn,
|
1115 |
sm501_palette_writefn, s); |
1116 |
cpu_register_physical_memory(base + MMIO_BASE_OFFSET |
1117 |
+ SM501_DC + SM501_DC_PANEL_PALETTE, |
1118 |
0x400 * 3, sm501_palette_index); |
1119 |
|
1120 |
/* bridge to serial emulation module */
|
1121 |
if (chr)
|
1122 |
serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
|
1123 |
0, /* TODO : chain irq to IRL */ |
1124 |
115200, chr, 1); |
1125 |
|
1126 |
/* create qemu graphic console */
|
1127 |
s->console = graphic_console_init(s->ds, sm501_update_display, NULL,
|
1128 |
NULL, NULL, s); |
1129 |
} |