root / target-arm / machine.c @ ffe47d33
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#include "hw/hw.h" |
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#include "hw/boards.h" |
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|
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void cpu_save(QEMUFile *f, void *opaque) |
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{
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int i;
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CPUARMState *env = (CPUARMState *)opaque; |
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|
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for (i = 0; i < 16; i++) { |
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qemu_put_be32(f, env->regs[i]); |
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} |
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qemu_put_be32(f, cpsr_read(env)); |
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qemu_put_be32(f, env->spsr); |
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for (i = 0; i < 6; i++) { |
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qemu_put_be32(f, env->banked_spsr[i]); |
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qemu_put_be32(f, env->banked_r13[i]); |
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qemu_put_be32(f, env->banked_r14[i]); |
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} |
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for (i = 0; i < 5; i++) { |
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qemu_put_be32(f, env->usr_regs[i]); |
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qemu_put_be32(f, env->fiq_regs[i]); |
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} |
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qemu_put_be32(f, env->cp15.c0_cpuid); |
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qemu_put_be32(f, env->cp15.c0_cachetype); |
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qemu_put_be32(f, env->cp15.c0_cssel); |
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qemu_put_be32(f, env->cp15.c1_sys); |
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qemu_put_be32(f, env->cp15.c1_coproc); |
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qemu_put_be32(f, env->cp15.c1_xscaleauxcr); |
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qemu_put_be32(f, env->cp15.c2_base0); |
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qemu_put_be32(f, env->cp15.c2_base1); |
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qemu_put_be32(f, env->cp15.c2_control); |
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qemu_put_be32(f, env->cp15.c2_mask); |
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qemu_put_be32(f, env->cp15.c2_base_mask); |
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qemu_put_be32(f, env->cp15.c2_data); |
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qemu_put_be32(f, env->cp15.c2_insn); |
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qemu_put_be32(f, env->cp15.c3); |
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qemu_put_be32(f, env->cp15.c5_insn); |
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qemu_put_be32(f, env->cp15.c5_data); |
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for (i = 0; i < 8; i++) { |
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qemu_put_be32(f, env->cp15.c6_region[i]); |
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} |
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qemu_put_be32(f, env->cp15.c6_insn); |
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qemu_put_be32(f, env->cp15.c6_data); |
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qemu_put_be32(f, env->cp15.c9_insn); |
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qemu_put_be32(f, env->cp15.c9_data); |
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qemu_put_be32(f, env->cp15.c13_fcse); |
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qemu_put_be32(f, env->cp15.c13_context); |
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qemu_put_be32(f, env->cp15.c13_tls1); |
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qemu_put_be32(f, env->cp15.c13_tls2); |
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qemu_put_be32(f, env->cp15.c13_tls3); |
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qemu_put_be32(f, env->cp15.c15_cpar); |
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|
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qemu_put_be32(f, env->features); |
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|
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if (arm_feature(env, ARM_FEATURE_VFP)) {
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for (i = 0; i < 16; i++) { |
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CPU_DoubleU u; |
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u.d = env->vfp.regs[i]; |
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qemu_put_be32(f, u.l.upper); |
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qemu_put_be32(f, u.l.lower); |
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} |
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for (i = 0; i < 16; i++) { |
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qemu_put_be32(f, env->vfp.xregs[i]); |
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} |
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/* TODO: Should use proper FPSCR access functions. */
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qemu_put_be32(f, env->vfp.vec_len); |
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qemu_put_be32(f, env->vfp.vec_stride); |
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if (arm_feature(env, ARM_FEATURE_VFP3)) {
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for (i = 16; i < 32; i++) { |
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CPU_DoubleU u; |
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u.d = env->vfp.regs[i]; |
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qemu_put_be32(f, u.l.upper); |
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qemu_put_be32(f, u.l.lower); |
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} |
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} |
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} |
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|
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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for (i = 0; i < 16; i++) { |
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qemu_put_be64(f, env->iwmmxt.regs[i]); |
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} |
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for (i = 0; i < 16; i++) { |
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qemu_put_be32(f, env->iwmmxt.cregs[i]); |
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} |
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} |
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if (arm_feature(env, ARM_FEATURE_M)) {
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qemu_put_be32(f, env->v7m.other_sp); |
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qemu_put_be32(f, env->v7m.vecbase); |
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qemu_put_be32(f, env->v7m.basepri); |
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qemu_put_be32(f, env->v7m.control); |
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qemu_put_be32(f, env->v7m.current_sp); |
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qemu_put_be32(f, env->v7m.exception); |
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} |
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if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
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qemu_put_be32(f, env->teecr); |
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qemu_put_be32(f, env->teehbr); |
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} |
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} |
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int cpu_load(QEMUFile *f, void *opaque, int version_id) |
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{
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CPUARMState *env = (CPUARMState *)opaque; |
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int i;
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uint32_t val; |
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if (version_id != CPU_SAVE_VERSION)
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return -EINVAL;
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for (i = 0; i < 16; i++) { |
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env->regs[i] = qemu_get_be32(f); |
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} |
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val = qemu_get_be32(f); |
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/* Avoid mode switch when restoring CPSR. */
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env->uncached_cpsr = val & CPSR_M; |
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cpsr_write(env, val, 0xffffffff);
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env->spsr = qemu_get_be32(f); |
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for (i = 0; i < 6; i++) { |
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env->banked_spsr[i] = qemu_get_be32(f); |
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env->banked_r13[i] = qemu_get_be32(f); |
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env->banked_r14[i] = qemu_get_be32(f); |
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} |
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for (i = 0; i < 5; i++) { |
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env->usr_regs[i] = qemu_get_be32(f); |
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env->fiq_regs[i] = qemu_get_be32(f); |
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} |
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env->cp15.c0_cpuid = qemu_get_be32(f); |
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env->cp15.c0_cachetype = qemu_get_be32(f); |
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env->cp15.c0_cssel = qemu_get_be32(f); |
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env->cp15.c1_sys = qemu_get_be32(f); |
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env->cp15.c1_coproc = qemu_get_be32(f); |
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env->cp15.c1_xscaleauxcr = qemu_get_be32(f); |
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env->cp15.c2_base0 = qemu_get_be32(f); |
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env->cp15.c2_base1 = qemu_get_be32(f); |
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env->cp15.c2_control = qemu_get_be32(f); |
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env->cp15.c2_mask = qemu_get_be32(f); |
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env->cp15.c2_base_mask = qemu_get_be32(f); |
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env->cp15.c2_data = qemu_get_be32(f); |
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env->cp15.c2_insn = qemu_get_be32(f); |
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env->cp15.c3 = qemu_get_be32(f); |
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env->cp15.c5_insn = qemu_get_be32(f); |
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env->cp15.c5_data = qemu_get_be32(f); |
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for (i = 0; i < 8; i++) { |
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env->cp15.c6_region[i] = qemu_get_be32(f); |
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} |
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env->cp15.c6_insn = qemu_get_be32(f); |
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env->cp15.c6_data = qemu_get_be32(f); |
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env->cp15.c9_insn = qemu_get_be32(f); |
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env->cp15.c9_data = qemu_get_be32(f); |
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env->cp15.c13_fcse = qemu_get_be32(f); |
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env->cp15.c13_context = qemu_get_be32(f); |
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env->cp15.c13_tls1 = qemu_get_be32(f); |
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env->cp15.c13_tls2 = qemu_get_be32(f); |
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env->cp15.c13_tls3 = qemu_get_be32(f); |
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env->cp15.c15_cpar = qemu_get_be32(f); |
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env->features = qemu_get_be32(f); |
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if (arm_feature(env, ARM_FEATURE_VFP)) {
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for (i = 0; i < 16; i++) { |
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CPU_DoubleU u; |
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u.l.upper = qemu_get_be32(f); |
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u.l.lower = qemu_get_be32(f); |
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env->vfp.regs[i] = u.d; |
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} |
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for (i = 0; i < 16; i++) { |
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env->vfp.xregs[i] = qemu_get_be32(f); |
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} |
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/* TODO: Should use proper FPSCR access functions. */
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env->vfp.vec_len = qemu_get_be32(f); |
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env->vfp.vec_stride = qemu_get_be32(f); |
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if (arm_feature(env, ARM_FEATURE_VFP3)) {
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for (i = 0; i < 16; i++) { |
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CPU_DoubleU u; |
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u.l.upper = qemu_get_be32(f); |
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u.l.lower = qemu_get_be32(f); |
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env->vfp.regs[i] = u.d; |
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} |
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} |
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} |
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|
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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for (i = 0; i < 16; i++) { |
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env->iwmmxt.regs[i] = qemu_get_be64(f); |
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} |
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for (i = 0; i < 16; i++) { |
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env->iwmmxt.cregs[i] = qemu_get_be32(f); |
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} |
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} |
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if (arm_feature(env, ARM_FEATURE_M)) {
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env->v7m.other_sp = qemu_get_be32(f); |
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env->v7m.vecbase = qemu_get_be32(f); |
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env->v7m.basepri = qemu_get_be32(f); |
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env->v7m.control = qemu_get_be32(f); |
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env->v7m.current_sp = qemu_get_be32(f); |
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env->v7m.exception = qemu_get_be32(f); |
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} |
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if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
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env->teecr = qemu_get_be32(f); |
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env->teehbr = qemu_get_be32(f); |
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} |
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return 0; |
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} |