Statistics
| Branch: | Revision:

root / target-mips / op_helper.c @ fff739cc

History | View | Annotate | Download (13.8 kB)

1
/*
2
 *  MIPS emulation helpers for qemu.
3
 * 
4
 *  Copyright (c) 2004-2005 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, write to the Free Software
18
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
 */
20
#include <stdlib.h>
21
#include "exec.h"
22

    
23
#define GETPC() (__builtin_return_address(0))
24

    
25
/*****************************************************************************/
26
/* Exceptions processing helpers */
27
void cpu_loop_exit(void)
28
{
29
    longjmp(env->jmp_env, 1);
30
}
31

    
32
void do_raise_exception_err (uint32_t exception, int error_code)
33
{
34
#if 1
35
    if (logfile && exception < 0x100)
36
        fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
37
#endif
38
    env->exception_index = exception;
39
    env->error_code = error_code;
40
    T0 = 0;
41
    cpu_loop_exit();
42
}
43

    
44
void do_raise_exception (uint32_t exception)
45
{
46
    do_raise_exception_err(exception, 0);
47
}
48

    
49
void do_restore_state (void *pc_ptr)
50
{
51
  TranslationBlock *tb;
52
  unsigned long pc = (unsigned long) pc_ptr;
53

    
54
  tb = tb_find_pc (pc);
55
  cpu_restore_state (tb, env, pc, NULL);
56
}
57

    
58
void do_raise_exception_direct_err (uint32_t exception, int error_code)
59
{
60
    do_restore_state (GETPC ());
61
    do_raise_exception_err (exception, error_code);
62
}
63

    
64
void do_raise_exception_direct (uint32_t exception)
65
{
66
    do_raise_exception_direct_err (exception, 0);
67
}
68

    
69
#define MEMSUFFIX _raw
70
#include "op_helper_mem.c"
71
#undef MEMSUFFIX
72
#if !defined(CONFIG_USER_ONLY)
73
#define MEMSUFFIX _user
74
#include "op_helper_mem.c"
75
#undef MEMSUFFIX
76
#define MEMSUFFIX _kernel
77
#include "op_helper_mem.c"
78
#undef MEMSUFFIX
79
#endif
80

    
81
#ifdef TARGET_MIPS64
82
#if TARGET_LONG_BITS > HOST_LONG_BITS
83
/* Those might call libgcc functions.  */
84
void do_dsll (void)
85
{
86
    T0 = T0 << T1;
87
}
88

    
89
void do_dsll32 (void)
90
{
91
    T0 = T0 << (T1 + 32);
92
}
93

    
94
void do_dsra (void)
95
{
96
    T0 = (int64_t)T0 >> T1;
97
}
98

    
99
void do_dsra32 (void)
100
{
101
    T0 = (int64_t)T0 >> (T1 + 32);
102
}
103

    
104
void do_dsrl (void)
105
{
106
    T0 = T0 >> T1;
107
}
108

    
109
void do_dsrl32 (void)
110
{
111
    T0 = T0 >> (T1 + 32);
112
}
113

    
114
void do_drotr (void)
115
{
116
    target_ulong tmp;
117

    
118
    if (T1) {
119
       tmp = T0 << (0x40 - T1);
120
       T0 = (T0 >> T1) | tmp;
121
    }
122
}
123

    
124
void do_drotr32 (void)
125
{
126
    target_ulong tmp;
127

    
128
    if (T1) {
129
       tmp = T0 << (0x40 - (32 + T1));
130
       T0 = (T0 >> (32 + T1)) | tmp;
131
    }
132
}
133

    
134
void do_dsllv (void)
135
{
136
    T0 = T1 << (T0 & 0x3F);
137
}
138

    
139
void do_dsrav (void)
140
{
141
    T0 = (int64_t)T1 >> (T0 & 0x3F);
142
}
143

    
144
void do_dsrlv (void)
145
{
146
    T0 = T1 >> (T0 & 0x3F);
147
}
148

    
149
void do_drotrv (void)
150
{
151
    target_ulong tmp;
152

    
153
    T0 &= 0x3F;
154
    if (T0) {
155
       tmp = T1 << (0x40 - T0);
156
       T0 = (T1 >> T0) | tmp;
157
    } else
158
       T0 = T1;
159
}
160
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
161
#endif /* TARGET_MIPS64 */
162

    
163
/* 64 bits arithmetic for 32 bits hosts */
164
#if TARGET_LONG_BITS > HOST_LONG_BITS
165
static inline uint64_t get_HILO (void)
166
{
167
    return (env->HI << 32) | (uint32_t)env->LO;
168
}
169

    
170
static inline void set_HILO (uint64_t HILO)
171
{
172
    env->LO = (int32_t)HILO;
173
    env->HI = (int32_t)(HILO >> 32);
174
}
175

    
176
void do_mult (void)
177
{
178
    set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
179
}
180

    
181
void do_multu (void)
182
{
183
    set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
184
}
185

    
186
void do_madd (void)
187
{
188
    int64_t tmp;
189

    
190
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
191
    set_HILO((int64_t)get_HILO() + tmp);
192
}
193

    
194
void do_maddu (void)
195
{
196
    uint64_t tmp;
197

    
198
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
199
    set_HILO(get_HILO() + tmp);
200
}
201

    
202
void do_msub (void)
203
{
204
    int64_t tmp;
205

    
206
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
207
    set_HILO((int64_t)get_HILO() - tmp);
208
}
209

    
210
void do_msubu (void)
211
{
212
    uint64_t tmp;
213

    
214
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
215
    set_HILO(get_HILO() - tmp);
216
}
217
#endif
218

    
219
#ifdef TARGET_MIPS64
220
void do_dmult (void)
221
{
222
    env->LO = (int64_t)T0 * (int64_t)T1;
223
    /* XXX */
224
    env->HI = (env->LO | (1ULL << 63)) ? ~0ULL : 0ULL;
225
}
226

    
227
void do_dmultu (void)
228
{
229
    env->LO = T0 * T1;
230
    /* XXX */
231
    env->HI = 0;
232
}
233

    
234
void do_ddiv (void)
235
{
236
    if (T1 != 0) {
237
        lldiv_t res = lldiv((int64_t)T0, (int64_t)T1);
238
        env->LO = res.quot;
239
        env->HI = res.rem;
240
    }
241
}
242

    
243
void do_ddivu (void)
244
{
245
    if (T1 != 0) {
246
        /* XXX: lldivu? */
247
        lldiv_t res = lldiv(T0, T1);
248
        env->LO = (uint64_t)res.quot;
249
        env->HI = (uint64_t)res.rem;
250
    }
251
}
252
#endif
253

    
254
#if defined(CONFIG_USER_ONLY) 
255
void do_mfc0_random (void)
256
{
257
    cpu_abort(env, "mfc0 random\n");
258
}
259

    
260
void do_mfc0_count (void)
261
{
262
    cpu_abort(env, "mfc0 count\n");
263
}
264

    
265
void cpu_mips_store_count(CPUState *env, uint32_t value)
266
{
267
    cpu_abort(env, "mtc0 count\n");
268
}
269

    
270
void cpu_mips_store_compare(CPUState *env, uint32_t value)
271
{
272
    cpu_abort(env, "mtc0 compare\n");
273
}
274

    
275
void cpu_mips_update_irq(CPUState *env)
276
{
277
    cpu_abort(env, "mtc0 status / mtc0 cause\n");
278
}
279

    
280
void do_mtc0_status_debug(uint32_t old, uint32_t val)
281
{
282
    cpu_abort(env, "mtc0 status debug\n");
283
}
284

    
285
void do_mtc0_status_irqraise_debug (void)
286
{
287
    cpu_abort(env, "mtc0 status irqraise debug\n");
288
}
289

    
290
void do_tlbwi (void)
291
{
292
    cpu_abort(env, "tlbwi\n");
293
}
294

    
295
void do_tlbwr (void)
296
{
297
    cpu_abort(env, "tlbwr\n");
298
}
299

    
300
void do_tlbp (void)
301
{
302
    cpu_abort(env, "tlbp\n");
303
}
304

    
305
void do_tlbr (void)
306
{
307
    cpu_abort(env, "tlbr\n");
308
}
309

    
310
void cpu_mips_tlb_flush (CPUState *env, int flush_global)
311
{
312
    cpu_abort(env, "mips_tlb_flush\n");
313
}
314

    
315
#else
316

    
317
/* CP0 helpers */
318
void do_mfc0_random (void)
319
{
320
    T0 = (int32_t)cpu_mips_get_random(env);
321
}
322

    
323
void do_mfc0_count (void)
324
{
325
    T0 = (int32_t)cpu_mips_get_count(env);
326
}
327

    
328
void do_mtc0_status_debug(uint32_t old, uint32_t val)
329
{
330
    fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
331
            old, old & env->CP0_Cause & CP0Ca_IP_mask,
332
            val, val & env->CP0_Cause & CP0Ca_IP_mask,
333
            env->CP0_Cause);
334
    (env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
335
                                  : fputs("\n", logfile);
336
}
337

    
338
void do_mtc0_status_irqraise_debug(void)
339
{
340
    fprintf(logfile, "Raise pending IRQs\n");
341
}
342

    
343
void fpu_handle_exception(void)
344
{
345
#ifdef CONFIG_SOFTFLOAT
346
    int flags = get_float_exception_flags(&env->fp_status);
347
    unsigned int cpuflags = 0, enable, cause = 0;
348

    
349
    enable = GET_FP_ENABLE(env->fcr31);
350

    
351
    /* determine current flags */   
352
    if (flags & float_flag_invalid) {
353
        cpuflags |= FP_INVALID;
354
        cause |= FP_INVALID & enable;
355
    }
356
    if (flags & float_flag_divbyzero) {
357
        cpuflags |= FP_DIV0;    
358
        cause |= FP_DIV0 & enable;
359
    }
360
    if (flags & float_flag_overflow) {
361
        cpuflags |= FP_OVERFLOW;    
362
        cause |= FP_OVERFLOW & enable;
363
    }
364
    if (flags & float_flag_underflow) {
365
        cpuflags |= FP_UNDERFLOW;   
366
        cause |= FP_UNDERFLOW & enable;
367
    }
368
    if (flags & float_flag_inexact) {
369
        cpuflags |= FP_INEXACT; 
370
        cause |= FP_INEXACT & enable;
371
    }
372
    SET_FP_FLAGS(env->fcr31, cpuflags);
373
    SET_FP_CAUSE(env->fcr31, cause);
374
#else
375
    SET_FP_FLAGS(env->fcr31, 0);
376
    SET_FP_CAUSE(env->fcr31, 0);
377
#endif
378
}
379

    
380
/* TLB management */
381
#if defined(MIPS_USES_R4K_TLB)
382
void cpu_mips_tlb_flush (CPUState *env, int flush_global)
383
{
384
    /* Flush qemu's TLB and discard all shadowed entries.  */
385
    tlb_flush (env, flush_global);
386
    env->tlb_in_use = MIPS_TLB_NB;
387
}
388

    
389
static void mips_tlb_flush_extra (CPUState *env, int first)
390
{
391
    /* Discard entries from env->tlb[first] onwards.  */
392
    while (env->tlb_in_use > first) {
393
        invalidate_tlb(env, --env->tlb_in_use, 0);
394
    }
395
}
396

    
397
static void fill_tlb (int idx)
398
{
399
    tlb_t *tlb;
400

    
401
    /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
402
    tlb = &env->tlb[idx];
403
    tlb->VPN = env->CP0_EntryHi & ~(target_ulong)0x1FFF;
404
    tlb->ASID = env->CP0_EntryHi & 0xFF;
405
    tlb->PageMask = env->CP0_PageMask;
406
    tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
407
    tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
408
    tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
409
    tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
410
    tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
411
    tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
412
    tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
413
    tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
414
    tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
415
}
416

    
417
void do_tlbwi (void)
418
{
419
    /* Discard cached TLB entries.  We could avoid doing this if the
420
       tlbwi is just upgrading access permissions on the current entry;
421
       that might be a further win.  */
422
    mips_tlb_flush_extra (env, MIPS_TLB_NB);
423

    
424
    /* Wildly undefined effects for CP0_Index containing a too high value and
425
       MIPS_TLB_NB not being a power of two.  But so does real silicon.  */
426
    invalidate_tlb(env, env->CP0_Index & (MIPS_TLB_NB - 1), 0);
427
    fill_tlb(env->CP0_Index & (MIPS_TLB_NB - 1));
428
}
429

    
430
void do_tlbwr (void)
431
{
432
    int r = cpu_mips_get_random(env);
433

    
434
    invalidate_tlb(env, r, 1);
435
    fill_tlb(r);
436
}
437

    
438
void do_tlbp (void)
439
{
440
    tlb_t *tlb;
441
    target_ulong tag;
442
    uint8_t ASID;
443
    int i;
444

    
445
    tag = env->CP0_EntryHi & (int32_t)0xFFFFE000;
446
    ASID = env->CP0_EntryHi & 0xFF;
447
    for (i = 0; i < MIPS_TLB_NB; i++) {
448
        tlb = &env->tlb[i];
449
        /* Check ASID, virtual page number & size */
450
        if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
451
            /* TLB match */
452
            env->CP0_Index = i;
453
            break;
454
        }
455
    }
456
    if (i == MIPS_TLB_NB) {
457
        /* No match.  Discard any shadow entries, if any of them match.  */
458
        for (i = MIPS_TLB_NB; i < env->tlb_in_use; i++) {
459
            tlb = &env->tlb[i];
460

    
461
            /* Check ASID, virtual page number & size */
462
            if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
463
                mips_tlb_flush_extra (env, i);
464
                break;
465
            }
466
        }
467

    
468
        env->CP0_Index |= 0x80000000;
469
    }
470
}
471

    
472
void do_tlbr (void)
473
{
474
    tlb_t *tlb;
475
    uint8_t ASID;
476

    
477
    ASID = env->CP0_EntryHi & 0xFF;
478
    tlb = &env->tlb[env->CP0_Index & (MIPS_TLB_NB - 1)];
479

    
480
    /* If this will change the current ASID, flush qemu's TLB.  */
481
    if (ASID != tlb->ASID)
482
        cpu_mips_tlb_flush (env, 1);
483

    
484
    mips_tlb_flush_extra(env, MIPS_TLB_NB);
485

    
486
    env->CP0_EntryHi = tlb->VPN | tlb->ASID;
487
    env->CP0_PageMask = tlb->PageMask;
488
    env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
489
                        (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
490
    env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
491
                        (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
492
}
493
#endif
494

    
495
#endif /* !CONFIG_USER_ONLY */
496

    
497
void dump_ldst (const unsigned char *func)
498
{
499
    if (loglevel)
500
        fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
501
}
502

    
503
void dump_sc (void)
504
{
505
    if (loglevel) {
506
        fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
507
                T1, T0, env->CP0_LLAddr);
508
    }
509
}
510

    
511
void debug_pre_eret (void)
512
{
513
    fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
514
            env->PC, env->CP0_EPC);
515
    if (env->CP0_Status & (1 << CP0St_ERL))
516
        fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
517
    if (env->hflags & MIPS_HFLAG_DM)
518
        fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
519
    fputs("\n", logfile);
520
}
521

    
522
void debug_post_eret (void)
523
{
524
    fprintf(logfile, "  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
525
            env->PC, env->CP0_EPC);
526
    if (env->CP0_Status & (1 << CP0St_ERL))
527
        fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
528
    if (env->hflags & MIPS_HFLAG_DM)
529
        fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
530
    if (env->hflags & MIPS_HFLAG_UM)
531
        fputs(", UM\n", logfile);
532
    else
533
        fputs("\n", logfile);
534
}
535

    
536
void do_pmon (int function)
537
{
538
    function /= 2;
539
    switch (function) {
540
    case 2: /* TODO: char inbyte(int waitflag); */
541
        if (env->gpr[4] == 0)
542
            env->gpr[2] = -1;
543
        /* Fall through */
544
    case 11: /* TODO: char inbyte (void); */
545
        env->gpr[2] = -1;
546
        break;
547
    case 3:
548
    case 12:
549
        printf("%c", (char)(env->gpr[4] & 0xFF));
550
        break;
551
    case 17:
552
        break;
553
    case 158:
554
        {
555
            unsigned char *fmt = (void *)(unsigned long)env->gpr[4];
556
            printf("%s", fmt);
557
        }
558
        break;
559
    }
560
}
561

    
562
#if !defined(CONFIG_USER_ONLY) 
563

    
564
static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
565

    
566
#define MMUSUFFIX _mmu
567
#define ALIGNED_ONLY
568

    
569
#define SHIFT 0
570
#include "softmmu_template.h"
571

    
572
#define SHIFT 1
573
#include "softmmu_template.h"
574

    
575
#define SHIFT 2
576
#include "softmmu_template.h"
577

    
578
#define SHIFT 3
579
#include "softmmu_template.h"
580

    
581
static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
582
{
583
    env->CP0_BadVAddr = addr;
584
    do_restore_state (retaddr);
585
    do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
586
}
587

    
588
void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
589
{
590
    TranslationBlock *tb;
591
    CPUState *saved_env;
592
    unsigned long pc;
593
    int ret;
594

    
595
    /* XXX: hack to restore env in all cases, even if not called from
596
       generated code */
597
    saved_env = env;
598
    env = cpu_single_env;
599
    ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
600
    if (ret) {
601
        if (retaddr) {
602
            /* now we have a real cpu fault */
603
            pc = (unsigned long)retaddr;
604
            tb = tb_find_pc(pc);
605
            if (tb) {
606
                /* the PC is inside the translated code. It means that we have
607
                   a virtual CPU fault */
608
                cpu_restore_state(tb, env, pc, NULL);
609
            }
610
        }
611
        do_raise_exception_err(env->exception_index, env->error_code);
612
    }
613
    env = saved_env;
614
}
615

    
616
#endif