root / hw / pci.c @ 008ff9d7
History | View | Annotate | Download (19.1 kB)
1 | 69b91039 | bellard | /*
|
---|---|---|---|
2 | 69b91039 | bellard | * QEMU PCI bus manager
|
3 | 69b91039 | bellard | *
|
4 | 69b91039 | bellard | * Copyright (c) 2004 Fabrice Bellard
|
5 | 5fafdf24 | ths | *
|
6 | 69b91039 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 69b91039 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | 69b91039 | bellard | * in the Software without restriction, including without limitation the rights
|
9 | 69b91039 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 69b91039 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | 69b91039 | bellard | * furnished to do so, subject to the following conditions:
|
12 | 69b91039 | bellard | *
|
13 | 69b91039 | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | 69b91039 | bellard | * all copies or substantial portions of the Software.
|
15 | 69b91039 | bellard | *
|
16 | 69b91039 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 69b91039 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 69b91039 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 69b91039 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 69b91039 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 69b91039 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 69b91039 | bellard | * THE SOFTWARE.
|
23 | 69b91039 | bellard | */
|
24 | 69b91039 | bellard | #include "vl.h" |
25 | 69b91039 | bellard | |
26 | 69b91039 | bellard | //#define DEBUG_PCI
|
27 | 69b91039 | bellard | |
28 | 30468f78 | bellard | struct PCIBus {
|
29 | 30468f78 | bellard | int bus_num;
|
30 | 30468f78 | bellard | int devfn_min;
|
31 | 502a5395 | pbrook | pci_set_irq_fn set_irq; |
32 | d2b59317 | pbrook | pci_map_irq_fn map_irq; |
33 | 30468f78 | bellard | uint32_t config_reg; /* XXX: suppress */
|
34 | 384d8876 | bellard | /* low level pic */
|
35 | 384d8876 | bellard | SetIRQFunc *low_set_irq; |
36 | d537cf6c | pbrook | qemu_irq *irq_opaque; |
37 | 30468f78 | bellard | PCIDevice *devices[256];
|
38 | 80b3ada7 | pbrook | PCIDevice *parent_dev; |
39 | 80b3ada7 | pbrook | PCIBus *next; |
40 | d2b59317 | pbrook | /* The bus IRQ state is the logical OR of the connected devices.
|
41 | d2b59317 | pbrook | Keep a count of the number of devices with raised IRQs. */
|
42 | 80b3ada7 | pbrook | int irq_count[];
|
43 | 30468f78 | bellard | }; |
44 | 69b91039 | bellard | |
45 | 1941d19c | bellard | static void pci_update_mappings(PCIDevice *d); |
46 | d537cf6c | pbrook | static void pci_set_irq(void *opaque, int irq_num, int level); |
47 | 1941d19c | bellard | |
48 | 69b91039 | bellard | target_phys_addr_t pci_mem_base; |
49 | 0ac32c83 | bellard | static int pci_irq_index; |
50 | 30468f78 | bellard | static PCIBus *first_bus;
|
51 | 30468f78 | bellard | |
52 | d2b59317 | pbrook | PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
53 | d537cf6c | pbrook | qemu_irq *pic, int devfn_min, int nirq) |
54 | 30468f78 | bellard | { |
55 | 30468f78 | bellard | PCIBus *bus; |
56 | 80b3ada7 | pbrook | bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int))); |
57 | 502a5395 | pbrook | bus->set_irq = set_irq; |
58 | d2b59317 | pbrook | bus->map_irq = map_irq; |
59 | 502a5395 | pbrook | bus->irq_opaque = pic; |
60 | 502a5395 | pbrook | bus->devfn_min = devfn_min; |
61 | 30468f78 | bellard | first_bus = bus; |
62 | 30468f78 | bellard | return bus;
|
63 | 30468f78 | bellard | } |
64 | 69b91039 | bellard | |
65 | 80b3ada7 | pbrook | PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq) |
66 | 80b3ada7 | pbrook | { |
67 | 80b3ada7 | pbrook | PCIBus *bus; |
68 | 80b3ada7 | pbrook | bus = qemu_mallocz(sizeof(PCIBus));
|
69 | 80b3ada7 | pbrook | bus->map_irq = map_irq; |
70 | 80b3ada7 | pbrook | bus->parent_dev = dev; |
71 | 80b3ada7 | pbrook | bus->next = dev->bus->next; |
72 | 80b3ada7 | pbrook | dev->bus->next = bus; |
73 | 80b3ada7 | pbrook | return bus;
|
74 | 80b3ada7 | pbrook | } |
75 | 80b3ada7 | pbrook | |
76 | 502a5395 | pbrook | int pci_bus_num(PCIBus *s)
|
77 | 502a5395 | pbrook | { |
78 | 502a5395 | pbrook | return s->bus_num;
|
79 | 502a5395 | pbrook | } |
80 | 502a5395 | pbrook | |
81 | 1941d19c | bellard | void pci_device_save(PCIDevice *s, QEMUFile *f)
|
82 | 30ca2aab | bellard | { |
83 | 1941d19c | bellard | qemu_put_be32(f, 1); /* PCI device version */ |
84 | 30ca2aab | bellard | qemu_put_buffer(f, s->config, 256);
|
85 | 30ca2aab | bellard | } |
86 | 30ca2aab | bellard | |
87 | 1941d19c | bellard | int pci_device_load(PCIDevice *s, QEMUFile *f)
|
88 | 30ca2aab | bellard | { |
89 | 1941d19c | bellard | uint32_t version_id; |
90 | 1941d19c | bellard | version_id = qemu_get_be32(f); |
91 | 30ca2aab | bellard | if (version_id != 1) |
92 | 30ca2aab | bellard | return -EINVAL;
|
93 | 30ca2aab | bellard | qemu_get_buffer(f, s->config, 256);
|
94 | 1941d19c | bellard | pci_update_mappings(s); |
95 | 30ca2aab | bellard | return 0; |
96 | 30ca2aab | bellard | } |
97 | 30ca2aab | bellard | |
98 | 69b91039 | bellard | /* -1 for devfn means auto assign */
|
99 | 5fafdf24 | ths | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
100 | 30468f78 | bellard | int instance_size, int devfn, |
101 | 5fafdf24 | ths | PCIConfigReadFunc *config_read, |
102 | 69b91039 | bellard | PCIConfigWriteFunc *config_write) |
103 | 69b91039 | bellard | { |
104 | 30468f78 | bellard | PCIDevice *pci_dev; |
105 | 69b91039 | bellard | |
106 | 0ac32c83 | bellard | if (pci_irq_index >= PCI_DEVICES_MAX)
|
107 | 0ac32c83 | bellard | return NULL; |
108 | 3b46e624 | ths | |
109 | 69b91039 | bellard | if (devfn < 0) { |
110 | 30468f78 | bellard | for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
111 | 30468f78 | bellard | if (!bus->devices[devfn])
|
112 | 69b91039 | bellard | goto found;
|
113 | 69b91039 | bellard | } |
114 | 69b91039 | bellard | return NULL; |
115 | 69b91039 | bellard | found: ;
|
116 | 69b91039 | bellard | } |
117 | 69b91039 | bellard | pci_dev = qemu_mallocz(instance_size); |
118 | 69b91039 | bellard | if (!pci_dev)
|
119 | 69b91039 | bellard | return NULL; |
120 | 30468f78 | bellard | pci_dev->bus = bus; |
121 | 69b91039 | bellard | pci_dev->devfn = devfn; |
122 | 69b91039 | bellard | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
|
123 | d2b59317 | pbrook | memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); |
124 | 0ac32c83 | bellard | |
125 | 0ac32c83 | bellard | if (!config_read)
|
126 | 0ac32c83 | bellard | config_read = pci_default_read_config; |
127 | 0ac32c83 | bellard | if (!config_write)
|
128 | 0ac32c83 | bellard | config_write = pci_default_write_config; |
129 | 69b91039 | bellard | pci_dev->config_read = config_read; |
130 | 69b91039 | bellard | pci_dev->config_write = config_write; |
131 | 0ac32c83 | bellard | pci_dev->irq_index = pci_irq_index++; |
132 | 30468f78 | bellard | bus->devices[devfn] = pci_dev; |
133 | d537cf6c | pbrook | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
|
134 | 69b91039 | bellard | return pci_dev;
|
135 | 69b91039 | bellard | } |
136 | 69b91039 | bellard | |
137 | 5fafdf24 | ths | void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
138 | 5fafdf24 | ths | uint32_t size, int type,
|
139 | 69b91039 | bellard | PCIMapIORegionFunc *map_func) |
140 | 69b91039 | bellard | { |
141 | 69b91039 | bellard | PCIIORegion *r; |
142 | d7ce493a | pbrook | uint32_t addr; |
143 | 69b91039 | bellard | |
144 | 8a8696a3 | bellard | if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
145 | 69b91039 | bellard | return;
|
146 | 69b91039 | bellard | r = &pci_dev->io_regions[region_num]; |
147 | 69b91039 | bellard | r->addr = -1;
|
148 | 69b91039 | bellard | r->size = size; |
149 | 69b91039 | bellard | r->type = type; |
150 | 69b91039 | bellard | r->map_func = map_func; |
151 | d7ce493a | pbrook | if (region_num == PCI_ROM_SLOT) {
|
152 | d7ce493a | pbrook | addr = 0x30;
|
153 | d7ce493a | pbrook | } else {
|
154 | d7ce493a | pbrook | addr = 0x10 + region_num * 4; |
155 | d7ce493a | pbrook | } |
156 | d7ce493a | pbrook | *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); |
157 | 69b91039 | bellard | } |
158 | 69b91039 | bellard | |
159 | 502a5395 | pbrook | target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr) |
160 | 69b91039 | bellard | { |
161 | 502a5395 | pbrook | return addr + pci_mem_base;
|
162 | 69b91039 | bellard | } |
163 | 69b91039 | bellard | |
164 | 0ac32c83 | bellard | static void pci_update_mappings(PCIDevice *d) |
165 | 0ac32c83 | bellard | { |
166 | 0ac32c83 | bellard | PCIIORegion *r; |
167 | 0ac32c83 | bellard | int cmd, i;
|
168 | 8a8696a3 | bellard | uint32_t last_addr, new_addr, config_ofs; |
169 | 3b46e624 | ths | |
170 | 0ac32c83 | bellard | cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
171 | 8a8696a3 | bellard | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
172 | 0ac32c83 | bellard | r = &d->io_regions[i]; |
173 | 8a8696a3 | bellard | if (i == PCI_ROM_SLOT) {
|
174 | 8a8696a3 | bellard | config_ofs = 0x30;
|
175 | 8a8696a3 | bellard | } else {
|
176 | 8a8696a3 | bellard | config_ofs = 0x10 + i * 4; |
177 | 8a8696a3 | bellard | } |
178 | 0ac32c83 | bellard | if (r->size != 0) { |
179 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
|
180 | 0ac32c83 | bellard | if (cmd & PCI_COMMAND_IO) {
|
181 | 5fafdf24 | ths | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
182 | 8a8696a3 | bellard | config_ofs)); |
183 | 0ac32c83 | bellard | new_addr = new_addr & ~(r->size - 1);
|
184 | 0ac32c83 | bellard | last_addr = new_addr + r->size - 1;
|
185 | 0ac32c83 | bellard | /* NOTE: we have only 64K ioports on PC */
|
186 | 0ac32c83 | bellard | if (last_addr <= new_addr || new_addr == 0 || |
187 | 0ac32c83 | bellard | last_addr >= 0x10000) {
|
188 | 0ac32c83 | bellard | new_addr = -1;
|
189 | 0ac32c83 | bellard | } |
190 | 0ac32c83 | bellard | } else {
|
191 | 0ac32c83 | bellard | new_addr = -1;
|
192 | 0ac32c83 | bellard | } |
193 | 0ac32c83 | bellard | } else {
|
194 | 0ac32c83 | bellard | if (cmd & PCI_COMMAND_MEMORY) {
|
195 | 5fafdf24 | ths | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
196 | 8a8696a3 | bellard | config_ofs)); |
197 | 8a8696a3 | bellard | /* the ROM slot has a specific enable bit */
|
198 | 8a8696a3 | bellard | if (i == PCI_ROM_SLOT && !(new_addr & 1)) |
199 | 8a8696a3 | bellard | goto no_mem_map;
|
200 | 0ac32c83 | bellard | new_addr = new_addr & ~(r->size - 1);
|
201 | 0ac32c83 | bellard | last_addr = new_addr + r->size - 1;
|
202 | 0ac32c83 | bellard | /* NOTE: we do not support wrapping */
|
203 | 0ac32c83 | bellard | /* XXX: as we cannot support really dynamic
|
204 | 0ac32c83 | bellard | mappings, we handle specific values as invalid
|
205 | 0ac32c83 | bellard | mappings. */
|
206 | 0ac32c83 | bellard | if (last_addr <= new_addr || new_addr == 0 || |
207 | 0ac32c83 | bellard | last_addr == -1) {
|
208 | 0ac32c83 | bellard | new_addr = -1;
|
209 | 0ac32c83 | bellard | } |
210 | 0ac32c83 | bellard | } else {
|
211 | 8a8696a3 | bellard | no_mem_map:
|
212 | 0ac32c83 | bellard | new_addr = -1;
|
213 | 0ac32c83 | bellard | } |
214 | 0ac32c83 | bellard | } |
215 | 0ac32c83 | bellard | /* now do the real mapping */
|
216 | 0ac32c83 | bellard | if (new_addr != r->addr) {
|
217 | 0ac32c83 | bellard | if (r->addr != -1) { |
218 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
|
219 | 0ac32c83 | bellard | int class;
|
220 | 0ac32c83 | bellard | /* NOTE: specific hack for IDE in PC case:
|
221 | 0ac32c83 | bellard | only one byte must be mapped. */
|
222 | 0ac32c83 | bellard | class = d->config[0x0a] | (d->config[0x0b] << 8); |
223 | 0ac32c83 | bellard | if (class == 0x0101 && r->size == 4) { |
224 | 0ac32c83 | bellard | isa_unassign_ioport(r->addr + 2, 1); |
225 | 0ac32c83 | bellard | } else {
|
226 | 0ac32c83 | bellard | isa_unassign_ioport(r->addr, r->size); |
227 | 0ac32c83 | bellard | } |
228 | 0ac32c83 | bellard | } else {
|
229 | 502a5395 | pbrook | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
230 | 5fafdf24 | ths | r->size, |
231 | 0ac32c83 | bellard | IO_MEM_UNASSIGNED); |
232 | 0ac32c83 | bellard | } |
233 | 0ac32c83 | bellard | } |
234 | 0ac32c83 | bellard | r->addr = new_addr; |
235 | 0ac32c83 | bellard | if (r->addr != -1) { |
236 | 0ac32c83 | bellard | r->map_func(d, i, r->addr, r->size, r->type); |
237 | 0ac32c83 | bellard | } |
238 | 0ac32c83 | bellard | } |
239 | 0ac32c83 | bellard | } |
240 | 0ac32c83 | bellard | } |
241 | 0ac32c83 | bellard | } |
242 | 0ac32c83 | bellard | |
243 | 5fafdf24 | ths | uint32_t pci_default_read_config(PCIDevice *d, |
244 | 0ac32c83 | bellard | uint32_t address, int len)
|
245 | 69b91039 | bellard | { |
246 | 0ac32c83 | bellard | uint32_t val; |
247 | a2d4e44b | ths | |
248 | 0ac32c83 | bellard | switch(len) {
|
249 | 0ac32c83 | bellard | default:
|
250 | 0ac32c83 | bellard | case 4: |
251 | a2d4e44b | ths | if (address <= 0xfc) { |
252 | a2d4e44b | ths | val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
253 | a2d4e44b | ths | break;
|
254 | a2d4e44b | ths | } |
255 | a2d4e44b | ths | /* fall through */
|
256 | a2d4e44b | ths | case 2: |
257 | a2d4e44b | ths | if (address <= 0xfe) { |
258 | a2d4e44b | ths | val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
259 | a2d4e44b | ths | break;
|
260 | a2d4e44b | ths | } |
261 | a2d4e44b | ths | /* fall through */
|
262 | a2d4e44b | ths | case 1: |
263 | a2d4e44b | ths | val = d->config[address]; |
264 | 0ac32c83 | bellard | break;
|
265 | 0ac32c83 | bellard | } |
266 | 0ac32c83 | bellard | return val;
|
267 | 0ac32c83 | bellard | } |
268 | 0ac32c83 | bellard | |
269 | 5fafdf24 | ths | void pci_default_write_config(PCIDevice *d,
|
270 | 0ac32c83 | bellard | uint32_t address, uint32_t val, int len)
|
271 | 0ac32c83 | bellard | { |
272 | 0ac32c83 | bellard | int can_write, i;
|
273 | 7bf5be70 | bellard | uint32_t end, addr; |
274 | 0ac32c83 | bellard | |
275 | 5fafdf24 | ths | if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || |
276 | 8a8696a3 | bellard | (address >= 0x30 && address < 0x34))) { |
277 | 0ac32c83 | bellard | PCIIORegion *r; |
278 | 0ac32c83 | bellard | int reg;
|
279 | 0ac32c83 | bellard | |
280 | 8a8696a3 | bellard | if ( address >= 0x30 ) { |
281 | 8a8696a3 | bellard | reg = PCI_ROM_SLOT; |
282 | 8a8696a3 | bellard | }else{
|
283 | 8a8696a3 | bellard | reg = (address - 0x10) >> 2; |
284 | 8a8696a3 | bellard | } |
285 | 0ac32c83 | bellard | r = &d->io_regions[reg]; |
286 | 0ac32c83 | bellard | if (r->size == 0) |
287 | 0ac32c83 | bellard | goto default_config;
|
288 | 0ac32c83 | bellard | /* compute the stored value */
|
289 | 8a8696a3 | bellard | if (reg == PCI_ROM_SLOT) {
|
290 | 8a8696a3 | bellard | /* keep ROM enable bit */
|
291 | 8a8696a3 | bellard | val &= (~(r->size - 1)) | 1; |
292 | 8a8696a3 | bellard | } else {
|
293 | 8a8696a3 | bellard | val &= ~(r->size - 1);
|
294 | 8a8696a3 | bellard | val |= r->type; |
295 | 8a8696a3 | bellard | } |
296 | 8a8696a3 | bellard | *(uint32_t *)(d->config + address) = cpu_to_le32(val); |
297 | 0ac32c83 | bellard | pci_update_mappings(d); |
298 | 69b91039 | bellard | return;
|
299 | 0ac32c83 | bellard | } |
300 | 0ac32c83 | bellard | default_config:
|
301 | 0ac32c83 | bellard | /* not efficient, but simple */
|
302 | 7bf5be70 | bellard | addr = address; |
303 | 0ac32c83 | bellard | for(i = 0; i < len; i++) { |
304 | 0ac32c83 | bellard | /* default read/write accesses */
|
305 | 1f62d938 | bellard | switch(d->config[0x0e]) { |
306 | 0ac32c83 | bellard | case 0x00: |
307 | 1f62d938 | bellard | case 0x80: |
308 | 1f62d938 | bellard | switch(addr) {
|
309 | 1f62d938 | bellard | case 0x00: |
310 | 1f62d938 | bellard | case 0x01: |
311 | 1f62d938 | bellard | case 0x02: |
312 | 1f62d938 | bellard | case 0x03: |
313 | 1f62d938 | bellard | case 0x08: |
314 | 1f62d938 | bellard | case 0x09: |
315 | 1f62d938 | bellard | case 0x0a: |
316 | 1f62d938 | bellard | case 0x0b: |
317 | 1f62d938 | bellard | case 0x0e: |
318 | 1f62d938 | bellard | case 0x10 ... 0x27: /* base */ |
319 | 1f62d938 | bellard | case 0x30 ... 0x33: /* rom */ |
320 | 1f62d938 | bellard | case 0x3d: |
321 | 1f62d938 | bellard | can_write = 0;
|
322 | 1f62d938 | bellard | break;
|
323 | 1f62d938 | bellard | default:
|
324 | 1f62d938 | bellard | can_write = 1;
|
325 | 1f62d938 | bellard | break;
|
326 | 1f62d938 | bellard | } |
327 | 0ac32c83 | bellard | break;
|
328 | 0ac32c83 | bellard | default:
|
329 | 1f62d938 | bellard | case 0x01: |
330 | 1f62d938 | bellard | switch(addr) {
|
331 | 1f62d938 | bellard | case 0x00: |
332 | 1f62d938 | bellard | case 0x01: |
333 | 1f62d938 | bellard | case 0x02: |
334 | 1f62d938 | bellard | case 0x03: |
335 | 1f62d938 | bellard | case 0x08: |
336 | 1f62d938 | bellard | case 0x09: |
337 | 1f62d938 | bellard | case 0x0a: |
338 | 1f62d938 | bellard | case 0x0b: |
339 | 1f62d938 | bellard | case 0x0e: |
340 | 1f62d938 | bellard | case 0x38 ... 0x3b: /* rom */ |
341 | 1f62d938 | bellard | case 0x3d: |
342 | 1f62d938 | bellard | can_write = 0;
|
343 | 1f62d938 | bellard | break;
|
344 | 1f62d938 | bellard | default:
|
345 | 1f62d938 | bellard | can_write = 1;
|
346 | 1f62d938 | bellard | break;
|
347 | 1f62d938 | bellard | } |
348 | 0ac32c83 | bellard | break;
|
349 | 0ac32c83 | bellard | } |
350 | 0ac32c83 | bellard | if (can_write) {
|
351 | 7bf5be70 | bellard | d->config[addr] = val; |
352 | 0ac32c83 | bellard | } |
353 | a2d4e44b | ths | if (++addr > 0xff) |
354 | a2d4e44b | ths | break;
|
355 | 0ac32c83 | bellard | val >>= 8;
|
356 | 0ac32c83 | bellard | } |
357 | 0ac32c83 | bellard | |
358 | 0ac32c83 | bellard | end = address + len; |
359 | 0ac32c83 | bellard | if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { |
360 | 0ac32c83 | bellard | /* if the command register is modified, we must modify the mappings */
|
361 | 0ac32c83 | bellard | pci_update_mappings(d); |
362 | 69b91039 | bellard | } |
363 | 69b91039 | bellard | } |
364 | 69b91039 | bellard | |
365 | 502a5395 | pbrook | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) |
366 | 69b91039 | bellard | { |
367 | 30468f78 | bellard | PCIBus *s = opaque; |
368 | 30468f78 | bellard | PCIDevice *pci_dev; |
369 | 30468f78 | bellard | int config_addr, bus_num;
|
370 | 3b46e624 | ths | |
371 | 69b91039 | bellard | #if defined(DEBUG_PCI) && 0 |
372 | 69b91039 | bellard | printf("pci_data_write: addr=%08x val=%08x len=%d\n",
|
373 | 502a5395 | pbrook | addr, val, len); |
374 | 69b91039 | bellard | #endif
|
375 | 502a5395 | pbrook | bus_num = (addr >> 16) & 0xff; |
376 | 80b3ada7 | pbrook | while (s && s->bus_num != bus_num)
|
377 | 80b3ada7 | pbrook | s = s->next; |
378 | 80b3ada7 | pbrook | if (!s)
|
379 | 69b91039 | bellard | return;
|
380 | 502a5395 | pbrook | pci_dev = s->devices[(addr >> 8) & 0xff]; |
381 | 69b91039 | bellard | if (!pci_dev)
|
382 | 69b91039 | bellard | return;
|
383 | 502a5395 | pbrook | config_addr = addr & 0xff;
|
384 | 69b91039 | bellard | #if defined(DEBUG_PCI)
|
385 | 69b91039 | bellard | printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
|
386 | 69b91039 | bellard | pci_dev->name, config_addr, val, len); |
387 | 69b91039 | bellard | #endif
|
388 | 0ac32c83 | bellard | pci_dev->config_write(pci_dev, config_addr, val, len); |
389 | 69b91039 | bellard | } |
390 | 69b91039 | bellard | |
391 | 502a5395 | pbrook | uint32_t pci_data_read(void *opaque, uint32_t addr, int len) |
392 | 69b91039 | bellard | { |
393 | 30468f78 | bellard | PCIBus *s = opaque; |
394 | 30468f78 | bellard | PCIDevice *pci_dev; |
395 | 30468f78 | bellard | int config_addr, bus_num;
|
396 | 69b91039 | bellard | uint32_t val; |
397 | 69b91039 | bellard | |
398 | 502a5395 | pbrook | bus_num = (addr >> 16) & 0xff; |
399 | 80b3ada7 | pbrook | while (s && s->bus_num != bus_num)
|
400 | 80b3ada7 | pbrook | s= s->next; |
401 | 80b3ada7 | pbrook | if (!s)
|
402 | 69b91039 | bellard | goto fail;
|
403 | 502a5395 | pbrook | pci_dev = s->devices[(addr >> 8) & 0xff]; |
404 | 69b91039 | bellard | if (!pci_dev) {
|
405 | 69b91039 | bellard | fail:
|
406 | 63ce9e0a | bellard | switch(len) {
|
407 | 63ce9e0a | bellard | case 1: |
408 | 63ce9e0a | bellard | val = 0xff;
|
409 | 63ce9e0a | bellard | break;
|
410 | 63ce9e0a | bellard | case 2: |
411 | 63ce9e0a | bellard | val = 0xffff;
|
412 | 63ce9e0a | bellard | break;
|
413 | 63ce9e0a | bellard | default:
|
414 | 63ce9e0a | bellard | case 4: |
415 | 63ce9e0a | bellard | val = 0xffffffff;
|
416 | 63ce9e0a | bellard | break;
|
417 | 63ce9e0a | bellard | } |
418 | 69b91039 | bellard | goto the_end;
|
419 | 69b91039 | bellard | } |
420 | 502a5395 | pbrook | config_addr = addr & 0xff;
|
421 | 69b91039 | bellard | val = pci_dev->config_read(pci_dev, config_addr, len); |
422 | 69b91039 | bellard | #if defined(DEBUG_PCI)
|
423 | 69b91039 | bellard | printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
424 | 69b91039 | bellard | pci_dev->name, config_addr, val, len); |
425 | 69b91039 | bellard | #endif
|
426 | 69b91039 | bellard | the_end:
|
427 | 69b91039 | bellard | #if defined(DEBUG_PCI) && 0 |
428 | 69b91039 | bellard | printf("pci_data_read: addr=%08x val=%08x len=%d\n",
|
429 | 502a5395 | pbrook | addr, val, len); |
430 | 69b91039 | bellard | #endif
|
431 | 69b91039 | bellard | return val;
|
432 | 69b91039 | bellard | } |
433 | 69b91039 | bellard | |
434 | 502a5395 | pbrook | /***********************************************************/
|
435 | 502a5395 | pbrook | /* generic PCI irq support */
|
436 | 30468f78 | bellard | |
437 | 502a5395 | pbrook | /* 0 <= irq_num <= 3. level must be 0 or 1 */
|
438 | d537cf6c | pbrook | static void pci_set_irq(void *opaque, int irq_num, int level) |
439 | 69b91039 | bellard | { |
440 | d537cf6c | pbrook | PCIDevice *pci_dev = (PCIDevice *)opaque; |
441 | 80b3ada7 | pbrook | PCIBus *bus; |
442 | 80b3ada7 | pbrook | int change;
|
443 | 3b46e624 | ths | |
444 | 80b3ada7 | pbrook | change = level - pci_dev->irq_state[irq_num]; |
445 | 80b3ada7 | pbrook | if (!change)
|
446 | 80b3ada7 | pbrook | return;
|
447 | d2b59317 | pbrook | |
448 | d2b59317 | pbrook | pci_dev->irq_state[irq_num] = level; |
449 | 5e966ce6 | pbrook | for (;;) {
|
450 | 5e966ce6 | pbrook | bus = pci_dev->bus; |
451 | 80b3ada7 | pbrook | irq_num = bus->map_irq(pci_dev, irq_num); |
452 | 5e966ce6 | pbrook | if (bus->set_irq)
|
453 | 5e966ce6 | pbrook | break;
|
454 | 80b3ada7 | pbrook | pci_dev = bus->parent_dev; |
455 | 80b3ada7 | pbrook | } |
456 | 80b3ada7 | pbrook | bus->irq_count[irq_num] += change; |
457 | d2b59317 | pbrook | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
|
458 | 69b91039 | bellard | } |
459 | 69b91039 | bellard | |
460 | 502a5395 | pbrook | /***********************************************************/
|
461 | 502a5395 | pbrook | /* monitor info on PCI */
|
462 | 0ac32c83 | bellard | |
463 | 6650ee6d | pbrook | typedef struct { |
464 | 6650ee6d | pbrook | uint16_t class; |
465 | 6650ee6d | pbrook | const char *desc; |
466 | 6650ee6d | pbrook | } pci_class_desc; |
467 | 6650ee6d | pbrook | |
468 | 5fafdf24 | ths | static pci_class_desc pci_class_descriptions[] =
|
469 | 6650ee6d | pbrook | { |
470 | 4ca9c76f | pbrook | { 0x0100, "SCSI controller"}, |
471 | 6650ee6d | pbrook | { 0x0101, "IDE controller"}, |
472 | dcb5b19a | ths | { 0x0102, "Floppy controller"}, |
473 | dcb5b19a | ths | { 0x0103, "IPI controller"}, |
474 | dcb5b19a | ths | { 0x0104, "RAID controller"}, |
475 | dcb5b19a | ths | { 0x0106, "SATA controller"}, |
476 | dcb5b19a | ths | { 0x0107, "SAS controller"}, |
477 | dcb5b19a | ths | { 0x0180, "Storage controller"}, |
478 | 6650ee6d | pbrook | { 0x0200, "Ethernet controller"}, |
479 | dcb5b19a | ths | { 0x0201, "Token Ring controller"}, |
480 | dcb5b19a | ths | { 0x0202, "FDDI controller"}, |
481 | dcb5b19a | ths | { 0x0203, "ATM controller"}, |
482 | dcb5b19a | ths | { 0x0280, "Network controller"}, |
483 | 6650ee6d | pbrook | { 0x0300, "VGA controller"}, |
484 | dcb5b19a | ths | { 0x0301, "XGA controller"}, |
485 | dcb5b19a | ths | { 0x0302, "3D controller"}, |
486 | dcb5b19a | ths | { 0x0380, "Display controller"}, |
487 | dcb5b19a | ths | { 0x0400, "Video controller"}, |
488 | dcb5b19a | ths | { 0x0401, "Audio controller"}, |
489 | dcb5b19a | ths | { 0x0402, "Phone"}, |
490 | dcb5b19a | ths | { 0x0480, "Multimedia controller"}, |
491 | dcb5b19a | ths | { 0x0500, "RAM controller"}, |
492 | dcb5b19a | ths | { 0x0501, "Flash controller"}, |
493 | dcb5b19a | ths | { 0x0580, "Memory controller"}, |
494 | 6650ee6d | pbrook | { 0x0600, "Host bridge"}, |
495 | 6650ee6d | pbrook | { 0x0601, "ISA bridge"}, |
496 | dcb5b19a | ths | { 0x0602, "EISA bridge"}, |
497 | dcb5b19a | ths | { 0x0603, "MC bridge"}, |
498 | 6650ee6d | pbrook | { 0x0604, "PCI bridge"}, |
499 | dcb5b19a | ths | { 0x0605, "PCMCIA bridge"}, |
500 | dcb5b19a | ths | { 0x0606, "NUBUS bridge"}, |
501 | dcb5b19a | ths | { 0x0607, "CARDBUS bridge"}, |
502 | dcb5b19a | ths | { 0x0608, "RACEWAY bridge"}, |
503 | dcb5b19a | ths | { 0x0680, "Bridge"}, |
504 | 6650ee6d | pbrook | { 0x0c03, "USB controller"}, |
505 | 6650ee6d | pbrook | { 0, NULL} |
506 | 6650ee6d | pbrook | }; |
507 | 6650ee6d | pbrook | |
508 | 502a5395 | pbrook | static void pci_info_device(PCIDevice *d) |
509 | 30468f78 | bellard | { |
510 | 502a5395 | pbrook | int i, class;
|
511 | 502a5395 | pbrook | PCIIORegion *r; |
512 | 6650ee6d | pbrook | pci_class_desc *desc; |
513 | 30468f78 | bellard | |
514 | 502a5395 | pbrook | term_printf(" Bus %2d, device %3d, function %d:\n",
|
515 | 502a5395 | pbrook | d->bus->bus_num, d->devfn >> 3, d->devfn & 7); |
516 | 502a5395 | pbrook | class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
517 | 502a5395 | pbrook | term_printf(" ");
|
518 | 6650ee6d | pbrook | desc = pci_class_descriptions; |
519 | 6650ee6d | pbrook | while (desc->desc && class != desc->class)
|
520 | 6650ee6d | pbrook | desc++; |
521 | 6650ee6d | pbrook | if (desc->desc) {
|
522 | 6650ee6d | pbrook | term_printf("%s", desc->desc);
|
523 | 6650ee6d | pbrook | } else {
|
524 | 502a5395 | pbrook | term_printf("Class %04x", class);
|
525 | 72cc6cfe | bellard | } |
526 | 502a5395 | pbrook | term_printf(": PCI device %04x:%04x\n",
|
527 | 502a5395 | pbrook | le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
528 | 502a5395 | pbrook | le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
529 | 30468f78 | bellard | |
530 | 502a5395 | pbrook | if (d->config[PCI_INTERRUPT_PIN] != 0) { |
531 | 502a5395 | pbrook | term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
532 | 30468f78 | bellard | } |
533 | 80b3ada7 | pbrook | if (class == 0x0604) { |
534 | 80b3ada7 | pbrook | term_printf(" BUS %d.\n", d->config[0x19]); |
535 | 80b3ada7 | pbrook | } |
536 | 502a5395 | pbrook | for(i = 0;i < PCI_NUM_REGIONS; i++) { |
537 | 502a5395 | pbrook | r = &d->io_regions[i]; |
538 | 502a5395 | pbrook | if (r->size != 0) { |
539 | 502a5395 | pbrook | term_printf(" BAR%d: ", i);
|
540 | 502a5395 | pbrook | if (r->type & PCI_ADDRESS_SPACE_IO) {
|
541 | 5fafdf24 | ths | term_printf("I/O at 0x%04x [0x%04x].\n",
|
542 | 502a5395 | pbrook | r->addr, r->addr + r->size - 1);
|
543 | 502a5395 | pbrook | } else {
|
544 | 5fafdf24 | ths | term_printf("32 bit memory at 0x%08x [0x%08x].\n",
|
545 | 502a5395 | pbrook | r->addr, r->addr + r->size - 1);
|
546 | 502a5395 | pbrook | } |
547 | 502a5395 | pbrook | } |
548 | 77d4bc34 | bellard | } |
549 | 80b3ada7 | pbrook | if (class == 0x0604 && d->config[0x19] != 0) { |
550 | 80b3ada7 | pbrook | pci_for_each_device(d->config[0x19], pci_info_device);
|
551 | 80b3ada7 | pbrook | } |
552 | 384d8876 | bellard | } |
553 | 384d8876 | bellard | |
554 | 80b3ada7 | pbrook | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)) |
555 | 384d8876 | bellard | { |
556 | 502a5395 | pbrook | PCIBus *bus = first_bus; |
557 | 384d8876 | bellard | PCIDevice *d; |
558 | 502a5395 | pbrook | int devfn;
|
559 | 3b46e624 | ths | |
560 | 80b3ada7 | pbrook | while (bus && bus->bus_num != bus_num)
|
561 | 80b3ada7 | pbrook | bus = bus->next; |
562 | 502a5395 | pbrook | if (bus) {
|
563 | 502a5395 | pbrook | for(devfn = 0; devfn < 256; devfn++) { |
564 | 502a5395 | pbrook | d = bus->devices[devfn]; |
565 | 502a5395 | pbrook | if (d)
|
566 | 502a5395 | pbrook | fn(d); |
567 | 502a5395 | pbrook | } |
568 | f2aa58c6 | bellard | } |
569 | f2aa58c6 | bellard | } |
570 | f2aa58c6 | bellard | |
571 | 502a5395 | pbrook | void pci_info(void) |
572 | f2aa58c6 | bellard | { |
573 | 80b3ada7 | pbrook | pci_for_each_device(0, pci_info_device);
|
574 | 77d4bc34 | bellard | } |
575 | a41b2ff2 | pbrook | |
576 | a41b2ff2 | pbrook | /* Initialize a PCI NIC. */
|
577 | abcebc7e | ths | void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn) |
578 | a41b2ff2 | pbrook | { |
579 | a41b2ff2 | pbrook | if (strcmp(nd->model, "ne2k_pci") == 0) { |
580 | abcebc7e | ths | pci_ne2000_init(bus, nd, devfn); |
581 | 663e8e51 | ths | } else if (strcmp(nd->model, "i82551") == 0) { |
582 | 663e8e51 | ths | pci_i82551_init(bus, nd, devfn); |
583 | 663e8e51 | ths | } else if (strcmp(nd->model, "i82557b") == 0) { |
584 | 663e8e51 | ths | pci_i82557b_init(bus, nd, devfn); |
585 | 663e8e51 | ths | } else if (strcmp(nd->model, "i82559er") == 0) { |
586 | 663e8e51 | ths | pci_i82559er_init(bus, nd, devfn); |
587 | a41b2ff2 | pbrook | } else if (strcmp(nd->model, "rtl8139") == 0) { |
588 | abcebc7e | ths | pci_rtl8139_init(bus, nd, devfn); |
589 | e3c2613f | bellard | } else if (strcmp(nd->model, "pcnet") == 0) { |
590 | abcebc7e | ths | pci_pcnet_init(bus, nd, devfn); |
591 | c4a7060c | blueswir1 | } else if (strcmp(nd->model, "?") == 0) { |
592 | c4a7060c | blueswir1 | fprintf(stderr, "qemu: Supported PCI NICs: i82551 i82557b i82559er"
|
593 | c4a7060c | blueswir1 | " ne2k_pci pcnet rtl8139\n");
|
594 | c4a7060c | blueswir1 | exit (1);
|
595 | a41b2ff2 | pbrook | } else {
|
596 | a41b2ff2 | pbrook | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
|
597 | a41b2ff2 | pbrook | exit (1);
|
598 | a41b2ff2 | pbrook | } |
599 | a41b2ff2 | pbrook | } |
600 | a41b2ff2 | pbrook | |
601 | 80b3ada7 | pbrook | typedef struct { |
602 | 80b3ada7 | pbrook | PCIDevice dev; |
603 | 80b3ada7 | pbrook | PCIBus *bus; |
604 | 80b3ada7 | pbrook | } PCIBridge; |
605 | 80b3ada7 | pbrook | |
606 | 5fafdf24 | ths | void pci_bridge_write_config(PCIDevice *d,
|
607 | 80b3ada7 | pbrook | uint32_t address, uint32_t val, int len)
|
608 | 80b3ada7 | pbrook | { |
609 | 80b3ada7 | pbrook | PCIBridge *s = (PCIBridge *)d; |
610 | 80b3ada7 | pbrook | |
611 | 80b3ada7 | pbrook | if (address == 0x19 || (address == 0x18 && len > 1)) { |
612 | 80b3ada7 | pbrook | if (address == 0x19) |
613 | 80b3ada7 | pbrook | s->bus->bus_num = val & 0xff;
|
614 | 80b3ada7 | pbrook | else
|
615 | 80b3ada7 | pbrook | s->bus->bus_num = (val >> 8) & 0xff; |
616 | 80b3ada7 | pbrook | #if defined(DEBUG_PCI)
|
617 | 80b3ada7 | pbrook | printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
|
618 | 80b3ada7 | pbrook | #endif
|
619 | 80b3ada7 | pbrook | } |
620 | 80b3ada7 | pbrook | pci_default_write_config(d, address, val, len); |
621 | 80b3ada7 | pbrook | } |
622 | 80b3ada7 | pbrook | |
623 | 80b3ada7 | pbrook | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
|
624 | 80b3ada7 | pbrook | pci_map_irq_fn map_irq, const char *name) |
625 | 80b3ada7 | pbrook | { |
626 | 80b3ada7 | pbrook | PCIBridge *s; |
627 | 5fafdf24 | ths | s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
|
628 | 80b3ada7 | pbrook | devfn, NULL, pci_bridge_write_config);
|
629 | 80b3ada7 | pbrook | s->dev.config[0x00] = id >> 16; |
630 | 451a4212 | ths | s->dev.config[0x01] = id >> 24; |
631 | 80b3ada7 | pbrook | s->dev.config[0x02] = id; // device_id |
632 | 80b3ada7 | pbrook | s->dev.config[0x03] = id >> 8; |
633 | 80b3ada7 | pbrook | s->dev.config[0x04] = 0x06; // command = bus master, pci mem |
634 | 80b3ada7 | pbrook | s->dev.config[0x05] = 0x00; |
635 | 80b3ada7 | pbrook | s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
636 | 80b3ada7 | pbrook | s->dev.config[0x07] = 0x00; // status = fast devsel |
637 | 80b3ada7 | pbrook | s->dev.config[0x08] = 0x00; // revision |
638 | 80b3ada7 | pbrook | s->dev.config[0x09] = 0x00; // programming i/f |
639 | 80b3ada7 | pbrook | s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge |
640 | 80b3ada7 | pbrook | s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge |
641 | 80b3ada7 | pbrook | s->dev.config[0x0D] = 0x10; // latency_timer |
642 | 80b3ada7 | pbrook | s->dev.config[0x0E] = 0x81; // header_type |
643 | 80b3ada7 | pbrook | s->dev.config[0x1E] = 0xa0; // secondary status |
644 | 80b3ada7 | pbrook | |
645 | 80b3ada7 | pbrook | s->bus = pci_register_secondary_bus(&s->dev, map_irq); |
646 | 80b3ada7 | pbrook | return s->bus;
|
647 | 80b3ada7 | pbrook | } |