root / hw / ppce500_pci.c @ 00c3a05b
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1 | 74c62ba8 | aurel32 | /*
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2 | 74c62ba8 | aurel32 | * QEMU PowerPC E500 embedded processors pci controller emulation
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3 | 74c62ba8 | aurel32 | *
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4 | 74c62ba8 | aurel32 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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5 | 74c62ba8 | aurel32 | *
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6 | 74c62ba8 | aurel32 | * Author: Yu Liu, <yu.liu@freescale.com>
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7 | 74c62ba8 | aurel32 | *
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8 | 74c62ba8 | aurel32 | * This file is derived from hw/ppc4xx_pci.c,
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9 | 74c62ba8 | aurel32 | * the copyright for that material belongs to the original owners.
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10 | 74c62ba8 | aurel32 | *
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11 | 74c62ba8 | aurel32 | * This is free software; you can redistribute it and/or modify
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12 | 74c62ba8 | aurel32 | * it under the terms of the GNU General Public License as published by
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13 | 74c62ba8 | aurel32 | * the Free Software Foundation; either version 2 of the License, or
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14 | 74c62ba8 | aurel32 | * (at your option) any later version.
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15 | 74c62ba8 | aurel32 | */
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16 | 74c62ba8 | aurel32 | |
17 | 74c62ba8 | aurel32 | #include "hw.h" |
18 | 74c62ba8 | aurel32 | #include "pci.h" |
19 | 74c62ba8 | aurel32 | #include "pci_host.h" |
20 | 74c62ba8 | aurel32 | #include "bswap.h" |
21 | 74c62ba8 | aurel32 | |
22 | 74c62ba8 | aurel32 | #ifdef DEBUG_PCI
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23 | 001faf32 | Blue Swirl | #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) |
24 | 74c62ba8 | aurel32 | #else
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25 | 001faf32 | Blue Swirl | #define pci_debug(fmt, ...)
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26 | 74c62ba8 | aurel32 | #endif
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27 | 74c62ba8 | aurel32 | |
28 | 74c62ba8 | aurel32 | #define PCIE500_CFGADDR 0x0 |
29 | 74c62ba8 | aurel32 | #define PCIE500_CFGDATA 0x4 |
30 | 74c62ba8 | aurel32 | #define PCIE500_REG_BASE 0xC00 |
31 | be13cc7a | Alexander Graf | #define PCIE500_ALL_SIZE 0x1000 |
32 | be13cc7a | Alexander Graf | #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
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33 | 74c62ba8 | aurel32 | |
34 | 74c62ba8 | aurel32 | #define PPCE500_PCI_CONFIG_ADDR 0x0 |
35 | 74c62ba8 | aurel32 | #define PPCE500_PCI_CONFIG_DATA 0x4 |
36 | 74c62ba8 | aurel32 | #define PPCE500_PCI_INTACK 0x8 |
37 | 74c62ba8 | aurel32 | |
38 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE) |
39 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE) |
40 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE) |
41 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE) |
42 | 74c62ba8 | aurel32 | #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE) |
43 | 74c62ba8 | aurel32 | #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE) |
44 | 74c62ba8 | aurel32 | #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE) |
45 | 74c62ba8 | aurel32 | |
46 | 74c62ba8 | aurel32 | #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE) |
47 | 74c62ba8 | aurel32 | |
48 | 74c62ba8 | aurel32 | #define PCI_POTAR 0x0 |
49 | 74c62ba8 | aurel32 | #define PCI_POTEAR 0x4 |
50 | 74c62ba8 | aurel32 | #define PCI_POWBAR 0x8 |
51 | 74c62ba8 | aurel32 | #define PCI_POWAR 0x10 |
52 | 74c62ba8 | aurel32 | |
53 | 74c62ba8 | aurel32 | #define PCI_PITAR 0x0 |
54 | 74c62ba8 | aurel32 | #define PCI_PIWBAR 0x8 |
55 | 74c62ba8 | aurel32 | #define PCI_PIWBEAR 0xC |
56 | 74c62ba8 | aurel32 | #define PCI_PIWAR 0x10 |
57 | 74c62ba8 | aurel32 | |
58 | 74c62ba8 | aurel32 | #define PPCE500_PCI_NR_POBS 5 |
59 | 74c62ba8 | aurel32 | #define PPCE500_PCI_NR_PIBS 3 |
60 | 74c62ba8 | aurel32 | |
61 | 74c62ba8 | aurel32 | struct pci_outbound {
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62 | 74c62ba8 | aurel32 | uint32_t potar; |
63 | 74c62ba8 | aurel32 | uint32_t potear; |
64 | 74c62ba8 | aurel32 | uint32_t powbar; |
65 | 74c62ba8 | aurel32 | uint32_t powar; |
66 | 74c62ba8 | aurel32 | }; |
67 | 74c62ba8 | aurel32 | |
68 | 74c62ba8 | aurel32 | struct pci_inbound {
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69 | 74c62ba8 | aurel32 | uint32_t pitar; |
70 | 74c62ba8 | aurel32 | uint32_t piwbar; |
71 | 74c62ba8 | aurel32 | uint32_t piwbear; |
72 | 74c62ba8 | aurel32 | uint32_t piwar; |
73 | 74c62ba8 | aurel32 | }; |
74 | 74c62ba8 | aurel32 | |
75 | 74c62ba8 | aurel32 | struct PPCE500PCIState {
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76 | be13cc7a | Alexander Graf | PCIHostState pci_state; |
77 | 74c62ba8 | aurel32 | struct pci_outbound pob[PPCE500_PCI_NR_POBS];
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78 | 74c62ba8 | aurel32 | struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
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79 | 74c62ba8 | aurel32 | uint32_t gasket_time; |
80 | be13cc7a | Alexander Graf | qemu_irq irq[4];
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81 | be13cc7a | Alexander Graf | /* mmio maps */
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82 | cd5cba79 | Avi Kivity | MemoryRegion iomem; |
83 | 74c62ba8 | aurel32 | }; |
84 | 74c62ba8 | aurel32 | |
85 | 74c62ba8 | aurel32 | typedef struct PPCE500PCIState PPCE500PCIState; |
86 | 74c62ba8 | aurel32 | |
87 | cd5cba79 | Avi Kivity | static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr, |
88 | cd5cba79 | Avi Kivity | unsigned size)
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89 | 74c62ba8 | aurel32 | { |
90 | 74c62ba8 | aurel32 | PPCE500PCIState *pci = opaque; |
91 | 74c62ba8 | aurel32 | unsigned long win; |
92 | 74c62ba8 | aurel32 | uint32_t value = 0;
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93 | eeae2e7b | Liu Yu-B13201 | int idx;
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94 | 74c62ba8 | aurel32 | |
95 | 74c62ba8 | aurel32 | win = addr & 0xfe0;
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96 | 74c62ba8 | aurel32 | |
97 | 74c62ba8 | aurel32 | switch (win) {
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98 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW1:
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99 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW2:
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100 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW3:
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101 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW4:
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102 | eeae2e7b | Liu Yu-B13201 | idx = (addr >> 5) & 0x7; |
103 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
104 | 6875dc8e | Liu Yu-B13201 | case PCI_POTAR:
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105 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].potar; |
106 | 6875dc8e | Liu Yu-B13201 | break;
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107 | 6875dc8e | Liu Yu-B13201 | case PCI_POTEAR:
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108 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].potear; |
109 | 6875dc8e | Liu Yu-B13201 | break;
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110 | 6875dc8e | Liu Yu-B13201 | case PCI_POWBAR:
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111 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].powbar; |
112 | 6875dc8e | Liu Yu-B13201 | break;
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113 | 6875dc8e | Liu Yu-B13201 | case PCI_POWAR:
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114 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].powar; |
115 | 6875dc8e | Liu Yu-B13201 | break;
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116 | 6875dc8e | Liu Yu-B13201 | default:
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117 | 6875dc8e | Liu Yu-B13201 | break;
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118 | 74c62ba8 | aurel32 | } |
119 | 74c62ba8 | aurel32 | break;
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120 | 74c62ba8 | aurel32 | |
121 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW3:
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122 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW2:
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123 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW1:
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124 | eeae2e7b | Liu Yu-B13201 | idx = ((addr >> 5) & 0x3) - 1; |
125 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
126 | 6875dc8e | Liu Yu-B13201 | case PCI_PITAR:
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127 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].pitar; |
128 | 6875dc8e | Liu Yu-B13201 | break;
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129 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBAR:
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130 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].piwbar; |
131 | 6875dc8e | Liu Yu-B13201 | break;
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132 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBEAR:
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133 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].piwbear; |
134 | 6875dc8e | Liu Yu-B13201 | break;
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135 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWAR:
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136 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].piwar; |
137 | 6875dc8e | Liu Yu-B13201 | break;
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138 | 6875dc8e | Liu Yu-B13201 | default:
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139 | 6875dc8e | Liu Yu-B13201 | break;
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140 | 74c62ba8 | aurel32 | }; |
141 | 74c62ba8 | aurel32 | break;
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142 | 74c62ba8 | aurel32 | |
143 | 74c62ba8 | aurel32 | case PPCE500_PCI_GASKET_TIMR:
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144 | 74c62ba8 | aurel32 | value = pci->gasket_time; |
145 | 74c62ba8 | aurel32 | break;
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146 | 74c62ba8 | aurel32 | |
147 | 74c62ba8 | aurel32 | default:
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148 | 74c62ba8 | aurel32 | break;
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149 | 74c62ba8 | aurel32 | } |
150 | 74c62ba8 | aurel32 | |
151 | c0a2a096 | Blue Swirl | pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, |
152 | c0a2a096 | Blue Swirl | win, addr, value); |
153 | 74c62ba8 | aurel32 | return value;
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154 | 74c62ba8 | aurel32 | } |
155 | 74c62ba8 | aurel32 | |
156 | c227f099 | Anthony Liguori | static void pci_reg_write4(void *opaque, target_phys_addr_t addr, |
157 | cd5cba79 | Avi Kivity | uint64_t value, unsigned size)
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158 | 74c62ba8 | aurel32 | { |
159 | 74c62ba8 | aurel32 | PPCE500PCIState *pci = opaque; |
160 | 74c62ba8 | aurel32 | unsigned long win; |
161 | eeae2e7b | Liu Yu-B13201 | int idx;
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162 | 74c62ba8 | aurel32 | |
163 | 74c62ba8 | aurel32 | win = addr & 0xfe0;
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164 | 74c62ba8 | aurel32 | |
165 | c0a2a096 | Blue Swirl | pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n", |
166 | cd5cba79 | Avi Kivity | __func__, (unsigned)value, win, addr);
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167 | 74c62ba8 | aurel32 | |
168 | 74c62ba8 | aurel32 | switch (win) {
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169 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW1:
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170 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW2:
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171 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW3:
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172 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW4:
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173 | eeae2e7b | Liu Yu-B13201 | idx = (addr >> 5) & 0x7; |
174 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
175 | 6875dc8e | Liu Yu-B13201 | case PCI_POTAR:
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176 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].potar = value; |
177 | 6875dc8e | Liu Yu-B13201 | break;
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178 | 6875dc8e | Liu Yu-B13201 | case PCI_POTEAR:
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179 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].potear = value; |
180 | 6875dc8e | Liu Yu-B13201 | break;
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181 | 6875dc8e | Liu Yu-B13201 | case PCI_POWBAR:
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182 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].powbar = value; |
183 | 6875dc8e | Liu Yu-B13201 | break;
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184 | 6875dc8e | Liu Yu-B13201 | case PCI_POWAR:
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185 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].powar = value; |
186 | 6875dc8e | Liu Yu-B13201 | break;
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187 | 6875dc8e | Liu Yu-B13201 | default:
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188 | 6875dc8e | Liu Yu-B13201 | break;
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189 | 74c62ba8 | aurel32 | }; |
190 | 74c62ba8 | aurel32 | break;
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191 | 74c62ba8 | aurel32 | |
192 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW3:
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193 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW2:
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194 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW1:
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195 | eeae2e7b | Liu Yu-B13201 | idx = ((addr >> 5) & 0x3) - 1; |
196 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
197 | 6875dc8e | Liu Yu-B13201 | case PCI_PITAR:
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198 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].pitar = value; |
199 | 6875dc8e | Liu Yu-B13201 | break;
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200 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBAR:
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201 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].piwbar = value; |
202 | 6875dc8e | Liu Yu-B13201 | break;
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203 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBEAR:
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204 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].piwbear = value; |
205 | 6875dc8e | Liu Yu-B13201 | break;
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206 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWAR:
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207 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].piwar = value; |
208 | 6875dc8e | Liu Yu-B13201 | break;
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209 | 6875dc8e | Liu Yu-B13201 | default:
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210 | 6875dc8e | Liu Yu-B13201 | break;
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211 | 74c62ba8 | aurel32 | }; |
212 | 74c62ba8 | aurel32 | break;
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213 | 74c62ba8 | aurel32 | |
214 | 74c62ba8 | aurel32 | case PPCE500_PCI_GASKET_TIMR:
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215 | 74c62ba8 | aurel32 | pci->gasket_time = value; |
216 | 74c62ba8 | aurel32 | break;
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217 | 74c62ba8 | aurel32 | |
218 | 74c62ba8 | aurel32 | default:
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219 | 74c62ba8 | aurel32 | break;
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220 | 74c62ba8 | aurel32 | }; |
221 | 74c62ba8 | aurel32 | } |
222 | 74c62ba8 | aurel32 | |
223 | cd5cba79 | Avi Kivity | static const MemoryRegionOps e500_pci_reg_ops = { |
224 | cd5cba79 | Avi Kivity | .read = pci_reg_read4, |
225 | cd5cba79 | Avi Kivity | .write = pci_reg_write4, |
226 | cd5cba79 | Avi Kivity | .endianness = DEVICE_BIG_ENDIAN, |
227 | 74c62ba8 | aurel32 | }; |
228 | 74c62ba8 | aurel32 | |
229 | 74c62ba8 | aurel32 | static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) |
230 | 74c62ba8 | aurel32 | { |
231 | 74c62ba8 | aurel32 | int devno = pci_dev->devfn >> 3, ret = 0; |
232 | 74c62ba8 | aurel32 | |
233 | 74c62ba8 | aurel32 | switch (devno) {
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234 | 74c62ba8 | aurel32 | /* Two PCI slot */
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235 | 74c62ba8 | aurel32 | case 0x11: |
236 | 74c62ba8 | aurel32 | case 0x12: |
237 | 74c62ba8 | aurel32 | ret = (irq_num + devno - 0x10) % 4; |
238 | 74c62ba8 | aurel32 | break;
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239 | 74c62ba8 | aurel32 | default:
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240 | 72b310e9 | Scott Wood | printf("Error:%s:unknown dev number\n", __func__);
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241 | 74c62ba8 | aurel32 | } |
242 | 74c62ba8 | aurel32 | |
243 | 74c62ba8 | aurel32 | pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
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244 | 74c62ba8 | aurel32 | pci_dev->devfn, irq_num, ret, devno); |
245 | 74c62ba8 | aurel32 | |
246 | 74c62ba8 | aurel32 | return ret;
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247 | 74c62ba8 | aurel32 | } |
248 | 74c62ba8 | aurel32 | |
249 | 5d4e84c8 | Juan Quintela | static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level) |
250 | 74c62ba8 | aurel32 | { |
251 | 5d4e84c8 | Juan Quintela | qemu_irq *pic = opaque; |
252 | 5d4e84c8 | Juan Quintela | |
253 | 74c62ba8 | aurel32 | pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
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254 | 74c62ba8 | aurel32 | |
255 | 74c62ba8 | aurel32 | qemu_set_irq(pic[irq_num], level); |
256 | 74c62ba8 | aurel32 | } |
257 | 74c62ba8 | aurel32 | |
258 | e0433ecc | Juan Quintela | static const VMStateDescription vmstate_pci_outbound = { |
259 | e0433ecc | Juan Quintela | .name = "pci_outbound",
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260 | e0433ecc | Juan Quintela | .version_id = 0,
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261 | e0433ecc | Juan Quintela | .minimum_version_id = 0,
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262 | e0433ecc | Juan Quintela | .minimum_version_id_old = 0,
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263 | e0433ecc | Juan Quintela | .fields = (VMStateField[]) { |
264 | e0433ecc | Juan Quintela | VMSTATE_UINT32(potar, struct pci_outbound),
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265 | e0433ecc | Juan Quintela | VMSTATE_UINT32(potear, struct pci_outbound),
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266 | e0433ecc | Juan Quintela | VMSTATE_UINT32(powbar, struct pci_outbound),
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267 | e0433ecc | Juan Quintela | VMSTATE_UINT32(powar, struct pci_outbound),
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268 | e0433ecc | Juan Quintela | VMSTATE_END_OF_LIST() |
269 | 74c62ba8 | aurel32 | } |
270 | e0433ecc | Juan Quintela | }; |
271 | 74c62ba8 | aurel32 | |
272 | e0433ecc | Juan Quintela | static const VMStateDescription vmstate_pci_inbound = { |
273 | e0433ecc | Juan Quintela | .name = "pci_inbound",
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274 | e0433ecc | Juan Quintela | .version_id = 0,
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275 | e0433ecc | Juan Quintela | .minimum_version_id = 0,
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276 | e0433ecc | Juan Quintela | .minimum_version_id_old = 0,
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277 | e0433ecc | Juan Quintela | .fields = (VMStateField[]) { |
278 | e0433ecc | Juan Quintela | VMSTATE_UINT32(pitar, struct pci_inbound),
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279 | e0433ecc | Juan Quintela | VMSTATE_UINT32(piwbar, struct pci_inbound),
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280 | e0433ecc | Juan Quintela | VMSTATE_UINT32(piwbear, struct pci_inbound),
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281 | e0433ecc | Juan Quintela | VMSTATE_UINT32(piwar, struct pci_inbound),
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282 | e0433ecc | Juan Quintela | VMSTATE_END_OF_LIST() |
283 | 74c62ba8 | aurel32 | } |
284 | e0433ecc | Juan Quintela | }; |
285 | 74c62ba8 | aurel32 | |
286 | e0433ecc | Juan Quintela | static const VMStateDescription vmstate_ppce500_pci = { |
287 | e0433ecc | Juan Quintela | .name = "ppce500_pci",
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288 | e0433ecc | Juan Quintela | .version_id = 1,
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289 | e0433ecc | Juan Quintela | .minimum_version_id = 1,
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290 | e0433ecc | Juan Quintela | .minimum_version_id_old = 1,
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291 | e0433ecc | Juan Quintela | .fields = (VMStateField[]) { |
292 | e0433ecc | Juan Quintela | VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
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293 | e0433ecc | Juan Quintela | vmstate_pci_outbound, struct pci_outbound),
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294 | e0433ecc | Juan Quintela | VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
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295 | e0433ecc | Juan Quintela | vmstate_pci_outbound, struct pci_inbound),
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296 | e0433ecc | Juan Quintela | VMSTATE_UINT32(gasket_time, PPCE500PCIState), |
297 | e0433ecc | Juan Quintela | VMSTATE_END_OF_LIST() |
298 | 74c62ba8 | aurel32 | } |
299 | e0433ecc | Juan Quintela | }; |
300 | 74c62ba8 | aurel32 | |
301 | be13cc7a | Alexander Graf | static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base) |
302 | be13cc7a | Alexander Graf | { |
303 | be13cc7a | Alexander Graf | PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); |
304 | be13cc7a | Alexander Graf | PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h); |
305 | be13cc7a | Alexander Graf | |
306 | d0ed8076 | Avi Kivity | sysbus_add_memory(dev, base + PCIE500_CFGADDR, &h->conf_mem); |
307 | d0ed8076 | Avi Kivity | sysbus_add_memory(dev, base + PCIE500_CFGDATA, &h->data_mem); |
308 | cd5cba79 | Avi Kivity | sysbus_add_memory(dev, base + PCIE500_REG_BASE, &s->iomem); |
309 | be13cc7a | Alexander Graf | } |
310 | be13cc7a | Alexander Graf | |
311 | cd0fa1e6 | Avi Kivity | static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base) |
312 | cd0fa1e6 | Avi Kivity | { |
313 | d0ed8076 | Avi Kivity | PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); |
314 | cd5cba79 | Avi Kivity | PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h); |
315 | d0ed8076 | Avi Kivity | |
316 | d0ed8076 | Avi Kivity | sysbus_del_memory(dev, &h->conf_mem); |
317 | d0ed8076 | Avi Kivity | sysbus_del_memory(dev, &h->data_mem); |
318 | cd5cba79 | Avi Kivity | sysbus_del_memory(dev, &s->iomem); |
319 | cd0fa1e6 | Avi Kivity | } |
320 | cd0fa1e6 | Avi Kivity | |
321 | 1e39101c | Avi Kivity | #include "exec-memory.h" |
322 | 1e39101c | Avi Kivity | |
323 | be13cc7a | Alexander Graf | static int e500_pcihost_initfn(SysBusDevice *dev) |
324 | be13cc7a | Alexander Graf | { |
325 | be13cc7a | Alexander Graf | PCIHostState *h; |
326 | be13cc7a | Alexander Graf | PPCE500PCIState *s; |
327 | be13cc7a | Alexander Graf | PCIBus *b; |
328 | be13cc7a | Alexander Graf | int i;
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329 | aee97b84 | Avi Kivity | MemoryRegion *address_space_mem = get_system_memory(); |
330 | aee97b84 | Avi Kivity | MemoryRegion *address_space_io = get_system_io(); |
331 | be13cc7a | Alexander Graf | |
332 | be13cc7a | Alexander Graf | h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); |
333 | be13cc7a | Alexander Graf | s = DO_UPCAST(PPCE500PCIState, pci_state, h); |
334 | be13cc7a | Alexander Graf | |
335 | be13cc7a | Alexander Graf | for (i = 0; i < ARRAY_SIZE(s->irq); i++) { |
336 | be13cc7a | Alexander Graf | sysbus_init_irq(dev, &s->irq[i]); |
337 | be13cc7a | Alexander Graf | } |
338 | be13cc7a | Alexander Graf | |
339 | be13cc7a | Alexander Graf | b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq,
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340 | aee97b84 | Avi Kivity | mpc85xx_pci_map_irq, s->irq, address_space_mem, |
341 | aee97b84 | Avi Kivity | address_space_io, PCI_DEVFN(0x11, 0), 4); |
342 | be13cc7a | Alexander Graf | s->pci_state.bus = b; |
343 | be13cc7a | Alexander Graf | |
344 | be13cc7a | Alexander Graf | pci_create_simple(b, 0, "e500-host-bridge"); |
345 | be13cc7a | Alexander Graf | |
346 | d0ed8076 | Avi Kivity | memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h, |
347 | d0ed8076 | Avi Kivity | "pci-conf-idx", 4); |
348 | d0ed8076 | Avi Kivity | memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h, |
349 | d0ed8076 | Avi Kivity | "pci-conf-data", 4); |
350 | cd5cba79 | Avi Kivity | memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s, |
351 | cd5cba79 | Avi Kivity | "pci.reg", PCIE500_REG_SIZE);
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352 | cd0fa1e6 | Avi Kivity | sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap); |
353 | be13cc7a | Alexander Graf | |
354 | be13cc7a | Alexander Graf | return 0; |
355 | be13cc7a | Alexander Graf | } |
356 | be13cc7a | Alexander Graf | |
357 | be13cc7a | Alexander Graf | static PCIDeviceInfo e500_host_bridge_info = {
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358 | be13cc7a | Alexander Graf | .qdev.name = "e500-host-bridge",
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359 | be13cc7a | Alexander Graf | .qdev.desc = "Host bridge",
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360 | be13cc7a | Alexander Graf | .qdev.size = sizeof(PCIDevice),
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361 | cdfdec7f | Michael S. Tsirkin | .vendor_id = PCI_VENDOR_ID_FREESCALE, |
362 | cdfdec7f | Michael S. Tsirkin | .device_id = PCI_DEVICE_ID_MPC8533E, |
363 | cdfdec7f | Michael S. Tsirkin | .class_id = PCI_CLASS_PROCESSOR_POWERPC, |
364 | be13cc7a | Alexander Graf | }; |
365 | be13cc7a | Alexander Graf | |
366 | be13cc7a | Alexander Graf | static SysBusDeviceInfo e500_pcihost_info = {
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367 | be13cc7a | Alexander Graf | .init = e500_pcihost_initfn, |
368 | be13cc7a | Alexander Graf | .qdev.name = "e500-pcihost",
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369 | be13cc7a | Alexander Graf | .qdev.size = sizeof(PPCE500PCIState),
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370 | be13cc7a | Alexander Graf | .qdev.vmsd = &vmstate_ppce500_pci, |
371 | be13cc7a | Alexander Graf | }; |
372 | be13cc7a | Alexander Graf | |
373 | be13cc7a | Alexander Graf | static void e500_pci_register(void) |
374 | 74c62ba8 | aurel32 | { |
375 | be13cc7a | Alexander Graf | sysbus_register_withprop(&e500_pcihost_info); |
376 | be13cc7a | Alexander Graf | pci_qdev_register(&e500_host_bridge_info); |
377 | 74c62ba8 | aurel32 | } |
378 | be13cc7a | Alexander Graf | device_init(e500_pci_register); |