root / hw / usb-uhci.c @ 00dbbb03
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1 | bb36d470 | bellard | /*
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2 | bb36d470 | bellard | * USB UHCI controller emulation
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3 | 5fafdf24 | ths | *
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4 | bb36d470 | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 54f254f9 | aliguori | * Copyright (c) 2008 Max Krasnyansky
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7 | 54f254f9 | aliguori | * Magor rewrite of the UHCI data structures parser and frame processor
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8 | 54f254f9 | aliguori | * Support for fully async operation and multiple outstanding transactions
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9 | 54f254f9 | aliguori | *
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10 | bb36d470 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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11 | bb36d470 | bellard | * of this software and associated documentation files (the "Software"), to deal
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12 | bb36d470 | bellard | * in the Software without restriction, including without limitation the rights
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13 | bb36d470 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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14 | bb36d470 | bellard | * copies of the Software, and to permit persons to whom the Software is
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15 | bb36d470 | bellard | * furnished to do so, subject to the following conditions:
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16 | bb36d470 | bellard | *
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17 | bb36d470 | bellard | * The above copyright notice and this permission notice shall be included in
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18 | bb36d470 | bellard | * all copies or substantial portions of the Software.
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19 | bb36d470 | bellard | *
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20 | bb36d470 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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21 | bb36d470 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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22 | bb36d470 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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23 | bb36d470 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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24 | bb36d470 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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25 | bb36d470 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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26 | bb36d470 | bellard | * THE SOFTWARE.
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27 | bb36d470 | bellard | */
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28 | 87ecb68b | pbrook | #include "hw.h" |
29 | 87ecb68b | pbrook | #include "usb.h" |
30 | 87ecb68b | pbrook | #include "pci.h" |
31 | 87ecb68b | pbrook | #include "qemu-timer.h" |
32 | bb36d470 | bellard | |
33 | bb36d470 | bellard | //#define DEBUG
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34 | 54f254f9 | aliguori | //#define DEBUG_DUMP_DATA
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35 | bb36d470 | bellard | |
36 | 96217e31 | ths | #define UHCI_CMD_FGR (1 << 4) |
37 | 96217e31 | ths | #define UHCI_CMD_EGSM (1 << 3) |
38 | bb36d470 | bellard | #define UHCI_CMD_GRESET (1 << 2) |
39 | bb36d470 | bellard | #define UHCI_CMD_HCRESET (1 << 1) |
40 | bb36d470 | bellard | #define UHCI_CMD_RS (1 << 0) |
41 | bb36d470 | bellard | |
42 | bb36d470 | bellard | #define UHCI_STS_HCHALTED (1 << 5) |
43 | bb36d470 | bellard | #define UHCI_STS_HCPERR (1 << 4) |
44 | bb36d470 | bellard | #define UHCI_STS_HSERR (1 << 3) |
45 | bb36d470 | bellard | #define UHCI_STS_RD (1 << 2) |
46 | bb36d470 | bellard | #define UHCI_STS_USBERR (1 << 1) |
47 | bb36d470 | bellard | #define UHCI_STS_USBINT (1 << 0) |
48 | bb36d470 | bellard | |
49 | bb36d470 | bellard | #define TD_CTRL_SPD (1 << 29) |
50 | bb36d470 | bellard | #define TD_CTRL_ERROR_SHIFT 27 |
51 | bb36d470 | bellard | #define TD_CTRL_IOS (1 << 25) |
52 | bb36d470 | bellard | #define TD_CTRL_IOC (1 << 24) |
53 | bb36d470 | bellard | #define TD_CTRL_ACTIVE (1 << 23) |
54 | bb36d470 | bellard | #define TD_CTRL_STALL (1 << 22) |
55 | bb36d470 | bellard | #define TD_CTRL_BABBLE (1 << 20) |
56 | bb36d470 | bellard | #define TD_CTRL_NAK (1 << 19) |
57 | bb36d470 | bellard | #define TD_CTRL_TIMEOUT (1 << 18) |
58 | bb36d470 | bellard | |
59 | bb36d470 | bellard | #define UHCI_PORT_RESET (1 << 9) |
60 | bb36d470 | bellard | #define UHCI_PORT_LSDA (1 << 8) |
61 | bb36d470 | bellard | #define UHCI_PORT_ENC (1 << 3) |
62 | bb36d470 | bellard | #define UHCI_PORT_EN (1 << 2) |
63 | bb36d470 | bellard | #define UHCI_PORT_CSC (1 << 1) |
64 | bb36d470 | bellard | #define UHCI_PORT_CCS (1 << 0) |
65 | bb36d470 | bellard | |
66 | bb36d470 | bellard | #define FRAME_TIMER_FREQ 1000 |
67 | bb36d470 | bellard | |
68 | bb36d470 | bellard | #define FRAME_MAX_LOOPS 100 |
69 | bb36d470 | bellard | |
70 | bb36d470 | bellard | #define NB_PORTS 2 |
71 | bb36d470 | bellard | |
72 | 54f254f9 | aliguori | #ifdef DEBUG
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73 | 54f254f9 | aliguori | #define dprintf printf
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74 | 54f254f9 | aliguori | |
75 | 54f254f9 | aliguori | const char *pid2str(int pid) |
76 | 54f254f9 | aliguori | { |
77 | 54f254f9 | aliguori | switch (pid) {
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78 | 54f254f9 | aliguori | case USB_TOKEN_SETUP: return "SETUP"; |
79 | 54f254f9 | aliguori | case USB_TOKEN_IN: return "IN"; |
80 | 54f254f9 | aliguori | case USB_TOKEN_OUT: return "OUT"; |
81 | 54f254f9 | aliguori | } |
82 | 54f254f9 | aliguori | return "?"; |
83 | 54f254f9 | aliguori | } |
84 | 54f254f9 | aliguori | |
85 | 54f254f9 | aliguori | #else
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86 | 54f254f9 | aliguori | #define dprintf(...)
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87 | 54f254f9 | aliguori | #endif
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88 | 54f254f9 | aliguori | |
89 | 54f254f9 | aliguori | #ifdef DEBUG_DUMP_DATA
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90 | 54f254f9 | aliguori | static void dump_data(const uint8_t *data, int len) |
91 | 54f254f9 | aliguori | { |
92 | 54f254f9 | aliguori | int i;
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93 | 54f254f9 | aliguori | |
94 | 54f254f9 | aliguori | printf("uhci: data: ");
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95 | 54f254f9 | aliguori | for(i = 0; i < len; i++) |
96 | 54f254f9 | aliguori | printf(" %02x", data[i]);
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97 | 54f254f9 | aliguori | printf("\n");
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98 | 54f254f9 | aliguori | } |
99 | 54f254f9 | aliguori | #else
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100 | 54f254f9 | aliguori | static void dump_data(const uint8_t *data, int len) {} |
101 | 54f254f9 | aliguori | #endif
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102 | 54f254f9 | aliguori | |
103 | 54f254f9 | aliguori | /*
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104 | 54f254f9 | aliguori | * Pending async transaction.
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105 | 54f254f9 | aliguori | * 'packet' must be the first field because completion
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106 | 54f254f9 | aliguori | * handler does "(UHCIAsync *) pkt" cast.
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107 | 54f254f9 | aliguori | */
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108 | 54f254f9 | aliguori | typedef struct UHCIAsync { |
109 | 54f254f9 | aliguori | USBPacket packet; |
110 | 54f254f9 | aliguori | struct UHCIAsync *next;
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111 | 54f254f9 | aliguori | uint32_t td; |
112 | 54f254f9 | aliguori | uint32_t token; |
113 | 54f254f9 | aliguori | int8_t valid; |
114 | 54f254f9 | aliguori | uint8_t done; |
115 | 54f254f9 | aliguori | uint8_t buffer[2048];
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116 | 54f254f9 | aliguori | } UHCIAsync; |
117 | 54f254f9 | aliguori | |
118 | bb36d470 | bellard | typedef struct UHCIPort { |
119 | bb36d470 | bellard | USBPort port; |
120 | bb36d470 | bellard | uint16_t ctrl; |
121 | bb36d470 | bellard | } UHCIPort; |
122 | bb36d470 | bellard | |
123 | bb36d470 | bellard | typedef struct UHCIState { |
124 | bb36d470 | bellard | PCIDevice dev; |
125 | bb36d470 | bellard | uint16_t cmd; /* cmd register */
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126 | bb36d470 | bellard | uint16_t status; |
127 | bb36d470 | bellard | uint16_t intr; /* interrupt enable register */
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128 | bb36d470 | bellard | uint16_t frnum; /* frame number */
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129 | bb36d470 | bellard | uint32_t fl_base_addr; /* frame list base address */
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130 | bb36d470 | bellard | uint8_t sof_timing; |
131 | bb36d470 | bellard | uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
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132 | bb36d470 | bellard | QEMUTimer *frame_timer; |
133 | bb36d470 | bellard | UHCIPort ports[NB_PORTS]; |
134 | 4d611c9a | pbrook | |
135 | 4d611c9a | pbrook | /* Interrupts that should be raised at the end of the current frame. */
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136 | 4d611c9a | pbrook | uint32_t pending_int_mask; |
137 | 54f254f9 | aliguori | |
138 | 54f254f9 | aliguori | /* Active packets */
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139 | 54f254f9 | aliguori | UHCIAsync *async_pending; |
140 | 54f254f9 | aliguori | UHCIAsync *async_pool; |
141 | bb36d470 | bellard | } UHCIState; |
142 | bb36d470 | bellard | |
143 | bb36d470 | bellard | typedef struct UHCI_TD { |
144 | bb36d470 | bellard | uint32_t link; |
145 | bb36d470 | bellard | uint32_t ctrl; /* see TD_CTRL_xxx */
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146 | bb36d470 | bellard | uint32_t token; |
147 | bb36d470 | bellard | uint32_t buffer; |
148 | bb36d470 | bellard | } UHCI_TD; |
149 | bb36d470 | bellard | |
150 | bb36d470 | bellard | typedef struct UHCI_QH { |
151 | bb36d470 | bellard | uint32_t link; |
152 | bb36d470 | bellard | uint32_t el_link; |
153 | bb36d470 | bellard | } UHCI_QH; |
154 | bb36d470 | bellard | |
155 | 54f254f9 | aliguori | static UHCIAsync *uhci_async_alloc(UHCIState *s)
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156 | 54f254f9 | aliguori | { |
157 | 54f254f9 | aliguori | UHCIAsync *async = qemu_malloc(sizeof(UHCIAsync));
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158 | 54f254f9 | aliguori | if (async) {
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159 | 54f254f9 | aliguori | memset(&async->packet, 0, sizeof(async->packet)); |
160 | 54f254f9 | aliguori | async->valid = 0;
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161 | 54f254f9 | aliguori | async->td = 0;
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162 | 54f254f9 | aliguori | async->token = 0;
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163 | 54f254f9 | aliguori | async->done = 0;
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164 | 54f254f9 | aliguori | async->next = NULL;
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165 | 54f254f9 | aliguori | } |
166 | 54f254f9 | aliguori | |
167 | 54f254f9 | aliguori | return async;
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168 | 54f254f9 | aliguori | } |
169 | 54f254f9 | aliguori | |
170 | 54f254f9 | aliguori | static void uhci_async_free(UHCIState *s, UHCIAsync *async) |
171 | 54f254f9 | aliguori | { |
172 | 54f254f9 | aliguori | qemu_free(async); |
173 | 54f254f9 | aliguori | } |
174 | 54f254f9 | aliguori | |
175 | 54f254f9 | aliguori | static void uhci_async_link(UHCIState *s, UHCIAsync *async) |
176 | 54f254f9 | aliguori | { |
177 | 54f254f9 | aliguori | async->next = s->async_pending; |
178 | 54f254f9 | aliguori | s->async_pending = async; |
179 | 54f254f9 | aliguori | } |
180 | 54f254f9 | aliguori | |
181 | 54f254f9 | aliguori | static void uhci_async_unlink(UHCIState *s, UHCIAsync *async) |
182 | 54f254f9 | aliguori | { |
183 | 54f254f9 | aliguori | UHCIAsync *curr = s->async_pending; |
184 | 54f254f9 | aliguori | UHCIAsync **prev = &s->async_pending; |
185 | 54f254f9 | aliguori | |
186 | 54f254f9 | aliguori | while (curr) {
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187 | 54f254f9 | aliguori | if (curr == async) {
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188 | 54f254f9 | aliguori | *prev = curr->next; |
189 | 54f254f9 | aliguori | return;
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190 | 54f254f9 | aliguori | } |
191 | 54f254f9 | aliguori | |
192 | 54f254f9 | aliguori | prev = &curr->next; |
193 | 54f254f9 | aliguori | curr = curr->next; |
194 | 54f254f9 | aliguori | } |
195 | 54f254f9 | aliguori | } |
196 | 54f254f9 | aliguori | |
197 | 54f254f9 | aliguori | static void uhci_async_cancel(UHCIState *s, UHCIAsync *async) |
198 | 54f254f9 | aliguori | { |
199 | 54f254f9 | aliguori | dprintf("uhci: cancel td 0x%x token 0x%x done %u\n",
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200 | 54f254f9 | aliguori | async->td, async->token, async->done); |
201 | 54f254f9 | aliguori | |
202 | 54f254f9 | aliguori | if (!async->done)
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203 | 54f254f9 | aliguori | usb_cancel_packet(&async->packet); |
204 | 54f254f9 | aliguori | uhci_async_free(s, async); |
205 | 54f254f9 | aliguori | } |
206 | 54f254f9 | aliguori | |
207 | 54f254f9 | aliguori | /*
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208 | 54f254f9 | aliguori | * Mark all outstanding async packets as invalid.
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209 | 54f254f9 | aliguori | * This is used for canceling them when TDs are removed by the HCD.
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210 | 54f254f9 | aliguori | */
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211 | 54f254f9 | aliguori | static UHCIAsync *uhci_async_validate_begin(UHCIState *s)
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212 | 54f254f9 | aliguori | { |
213 | 54f254f9 | aliguori | UHCIAsync *async = s->async_pending; |
214 | 54f254f9 | aliguori | |
215 | 54f254f9 | aliguori | while (async) {
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216 | 54f254f9 | aliguori | async->valid--; |
217 | 54f254f9 | aliguori | async = async->next; |
218 | 54f254f9 | aliguori | } |
219 | 54f254f9 | aliguori | return NULL; |
220 | 54f254f9 | aliguori | } |
221 | 54f254f9 | aliguori | |
222 | 54f254f9 | aliguori | /*
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223 | 54f254f9 | aliguori | * Cancel async packets that are no longer valid
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224 | 54f254f9 | aliguori | */
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225 | 54f254f9 | aliguori | static void uhci_async_validate_end(UHCIState *s) |
226 | 54f254f9 | aliguori | { |
227 | 54f254f9 | aliguori | UHCIAsync *curr = s->async_pending; |
228 | 54f254f9 | aliguori | UHCIAsync **prev = &s->async_pending; |
229 | 54f254f9 | aliguori | UHCIAsync *next; |
230 | 54f254f9 | aliguori | |
231 | 54f254f9 | aliguori | while (curr) {
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232 | 54f254f9 | aliguori | if (curr->valid > 0) { |
233 | 54f254f9 | aliguori | prev = &curr->next; |
234 | 54f254f9 | aliguori | curr = curr->next; |
235 | 54f254f9 | aliguori | continue;
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236 | 54f254f9 | aliguori | } |
237 | 54f254f9 | aliguori | |
238 | 54f254f9 | aliguori | next = curr->next; |
239 | 54f254f9 | aliguori | |
240 | 54f254f9 | aliguori | /* Unlink */
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241 | 54f254f9 | aliguori | *prev = next; |
242 | 54f254f9 | aliguori | |
243 | 54f254f9 | aliguori | uhci_async_cancel(s, curr); |
244 | 54f254f9 | aliguori | |
245 | 54f254f9 | aliguori | curr = next; |
246 | 54f254f9 | aliguori | } |
247 | 54f254f9 | aliguori | } |
248 | 54f254f9 | aliguori | |
249 | 54f254f9 | aliguori | static void uhci_async_cancel_all(UHCIState *s) |
250 | 54f254f9 | aliguori | { |
251 | 54f254f9 | aliguori | UHCIAsync *curr = s->async_pending; |
252 | 54f254f9 | aliguori | UHCIAsync *next; |
253 | 54f254f9 | aliguori | |
254 | 54f254f9 | aliguori | while (curr) {
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255 | 54f254f9 | aliguori | next = curr->next; |
256 | 54f254f9 | aliguori | |
257 | 54f254f9 | aliguori | uhci_async_cancel(s, curr); |
258 | 54f254f9 | aliguori | |
259 | 54f254f9 | aliguori | curr = next; |
260 | 54f254f9 | aliguori | } |
261 | 54f254f9 | aliguori | |
262 | 54f254f9 | aliguori | s->async_pending = NULL;
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263 | 54f254f9 | aliguori | } |
264 | 54f254f9 | aliguori | |
265 | 54f254f9 | aliguori | static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, uint32_t token)
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266 | 54f254f9 | aliguori | { |
267 | 54f254f9 | aliguori | UHCIAsync *async = s->async_pending; |
268 | e8ee3c72 | aurel32 | UHCIAsync *match = NULL;
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269 | e8ee3c72 | aurel32 | int count = 0; |
270 | e8ee3c72 | aurel32 | |
271 | e8ee3c72 | aurel32 | /*
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272 | e8ee3c72 | aurel32 | * We're looking for the best match here. ie both td addr and token.
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273 | e8ee3c72 | aurel32 | * Otherwise we return last good match. ie just token.
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274 | e8ee3c72 | aurel32 | * It's ok to match just token because it identifies the transaction
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275 | e8ee3c72 | aurel32 | * rather well, token includes: device addr, endpoint, size, etc.
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276 | e8ee3c72 | aurel32 | *
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277 | e8ee3c72 | aurel32 | * Also since we queue async transactions in reverse order by returning
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278 | e8ee3c72 | aurel32 | * last good match we restores the order.
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279 | e8ee3c72 | aurel32 | *
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280 | e8ee3c72 | aurel32 | * It's expected that we wont have a ton of outstanding transactions.
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281 | e8ee3c72 | aurel32 | * If we ever do we'd want to optimize this algorithm.
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282 | e8ee3c72 | aurel32 | */
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283 | 54f254f9 | aliguori | |
284 | 54f254f9 | aliguori | while (async) {
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285 | e8ee3c72 | aurel32 | if (async->token == token) {
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286 | e8ee3c72 | aurel32 | /* Good match */
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287 | e8ee3c72 | aurel32 | match = async; |
288 | e8ee3c72 | aurel32 | |
289 | e8ee3c72 | aurel32 | if (async->td == addr) {
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290 | e8ee3c72 | aurel32 | /* Best match */
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291 | e8ee3c72 | aurel32 | break;
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292 | 54f254f9 | aliguori | } |
293 | 54f254f9 | aliguori | } |
294 | 54f254f9 | aliguori | |
295 | 54f254f9 | aliguori | async = async->next; |
296 | e8ee3c72 | aurel32 | count++; |
297 | 54f254f9 | aliguori | } |
298 | e8ee3c72 | aurel32 | |
299 | e8ee3c72 | aurel32 | if (count > 64) |
300 | e8ee3c72 | aurel32 | fprintf(stderr, "uhci: warning lots of async transactions\n");
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301 | e8ee3c72 | aurel32 | |
302 | e8ee3c72 | aurel32 | return match;
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303 | 54f254f9 | aliguori | } |
304 | 54f254f9 | aliguori | |
305 | bb36d470 | bellard | static void uhci_attach(USBPort *port1, USBDevice *dev); |
306 | bb36d470 | bellard | |
307 | bb36d470 | bellard | static void uhci_update_irq(UHCIState *s) |
308 | bb36d470 | bellard | { |
309 | bb36d470 | bellard | int level;
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310 | bb36d470 | bellard | if (((s->status2 & 1) && (s->intr & (1 << 2))) || |
311 | bb36d470 | bellard | ((s->status2 & 2) && (s->intr & (1 << 3))) || |
312 | bb36d470 | bellard | ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || |
313 | bb36d470 | bellard | ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || |
314 | bb36d470 | bellard | (s->status & UHCI_STS_HSERR) || |
315 | bb36d470 | bellard | (s->status & UHCI_STS_HCPERR)) { |
316 | bb36d470 | bellard | level = 1;
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317 | bb36d470 | bellard | } else {
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318 | bb36d470 | bellard | level = 0;
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319 | bb36d470 | bellard | } |
320 | d537cf6c | pbrook | qemu_set_irq(s->dev.irq[3], level);
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321 | bb36d470 | bellard | } |
322 | bb36d470 | bellard | |
323 | bb36d470 | bellard | static void uhci_reset(UHCIState *s) |
324 | bb36d470 | bellard | { |
325 | bb36d470 | bellard | uint8_t *pci_conf; |
326 | bb36d470 | bellard | int i;
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327 | bb36d470 | bellard | UHCIPort *port; |
328 | bb36d470 | bellard | |
329 | 6f382b5e | aliguori | dprintf("uhci: full reset\n");
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330 | 6f382b5e | aliguori | |
331 | bb36d470 | bellard | pci_conf = s->dev.config; |
332 | bb36d470 | bellard | |
333 | bb36d470 | bellard | pci_conf[0x6a] = 0x01; /* usb clock */ |
334 | bb36d470 | bellard | pci_conf[0x6b] = 0x00; |
335 | bb36d470 | bellard | s->cmd = 0;
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336 | bb36d470 | bellard | s->status = 0;
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337 | bb36d470 | bellard | s->status2 = 0;
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338 | bb36d470 | bellard | s->intr = 0;
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339 | bb36d470 | bellard | s->fl_base_addr = 0;
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340 | bb36d470 | bellard | s->sof_timing = 64;
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341 | 54f254f9 | aliguori | |
342 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
343 | bb36d470 | bellard | port = &s->ports[i]; |
344 | bb36d470 | bellard | port->ctrl = 0x0080;
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345 | a594cfbf | bellard | if (port->port.dev)
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346 | a594cfbf | bellard | uhci_attach(&port->port, port->port.dev); |
347 | bb36d470 | bellard | } |
348 | 54f254f9 | aliguori | |
349 | 54f254f9 | aliguori | uhci_async_cancel_all(s); |
350 | bb36d470 | bellard | } |
351 | bb36d470 | bellard | |
352 | b9dc033c | balrog | static void uhci_save(QEMUFile *f, void *opaque) |
353 | b9dc033c | balrog | { |
354 | b9dc033c | balrog | UHCIState *s = opaque; |
355 | b9dc033c | balrog | uint8_t num_ports = NB_PORTS; |
356 | b9dc033c | balrog | int i;
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357 | b9dc033c | balrog | |
358 | 6f382b5e | aliguori | uhci_async_cancel_all(s); |
359 | 6f382b5e | aliguori | |
360 | b9dc033c | balrog | pci_device_save(&s->dev, f); |
361 | b9dc033c | balrog | |
362 | b9dc033c | balrog | qemu_put_8s(f, &num_ports); |
363 | b9dc033c | balrog | for (i = 0; i < num_ports; ++i) |
364 | b9dc033c | balrog | qemu_put_be16s(f, &s->ports[i].ctrl); |
365 | b9dc033c | balrog | qemu_put_be16s(f, &s->cmd); |
366 | b9dc033c | balrog | qemu_put_be16s(f, &s->status); |
367 | b9dc033c | balrog | qemu_put_be16s(f, &s->intr); |
368 | b9dc033c | balrog | qemu_put_be16s(f, &s->frnum); |
369 | b9dc033c | balrog | qemu_put_be32s(f, &s->fl_base_addr); |
370 | b9dc033c | balrog | qemu_put_8s(f, &s->sof_timing); |
371 | b9dc033c | balrog | qemu_put_8s(f, &s->status2); |
372 | b9dc033c | balrog | qemu_put_timer(f, s->frame_timer); |
373 | b9dc033c | balrog | } |
374 | b9dc033c | balrog | |
375 | b9dc033c | balrog | static int uhci_load(QEMUFile *f, void *opaque, int version_id) |
376 | b9dc033c | balrog | { |
377 | b9dc033c | balrog | UHCIState *s = opaque; |
378 | b9dc033c | balrog | uint8_t num_ports; |
379 | b9dc033c | balrog | int i, ret;
|
380 | b9dc033c | balrog | |
381 | b9dc033c | balrog | if (version_id > 1) |
382 | b9dc033c | balrog | return -EINVAL;
|
383 | b9dc033c | balrog | |
384 | b9dc033c | balrog | ret = pci_device_load(&s->dev, f); |
385 | b9dc033c | balrog | if (ret < 0) |
386 | b9dc033c | balrog | return ret;
|
387 | b9dc033c | balrog | |
388 | b9dc033c | balrog | qemu_get_8s(f, &num_ports); |
389 | b9dc033c | balrog | if (num_ports != NB_PORTS)
|
390 | b9dc033c | balrog | return -EINVAL;
|
391 | b9dc033c | balrog | |
392 | b9dc033c | balrog | for (i = 0; i < num_ports; ++i) |
393 | b9dc033c | balrog | qemu_get_be16s(f, &s->ports[i].ctrl); |
394 | b9dc033c | balrog | qemu_get_be16s(f, &s->cmd); |
395 | b9dc033c | balrog | qemu_get_be16s(f, &s->status); |
396 | b9dc033c | balrog | qemu_get_be16s(f, &s->intr); |
397 | b9dc033c | balrog | qemu_get_be16s(f, &s->frnum); |
398 | b9dc033c | balrog | qemu_get_be32s(f, &s->fl_base_addr); |
399 | b9dc033c | balrog | qemu_get_8s(f, &s->sof_timing); |
400 | b9dc033c | balrog | qemu_get_8s(f, &s->status2); |
401 | b9dc033c | balrog | qemu_get_timer(f, s->frame_timer); |
402 | b9dc033c | balrog | |
403 | b9dc033c | balrog | return 0; |
404 | b9dc033c | balrog | } |
405 | b9dc033c | balrog | |
406 | bb36d470 | bellard | static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
407 | bb36d470 | bellard | { |
408 | bb36d470 | bellard | UHCIState *s = opaque; |
409 | 3b46e624 | ths | |
410 | bb36d470 | bellard | addr &= 0x1f;
|
411 | bb36d470 | bellard | switch(addr) {
|
412 | bb36d470 | bellard | case 0x0c: |
413 | bb36d470 | bellard | s->sof_timing = val; |
414 | bb36d470 | bellard | break;
|
415 | bb36d470 | bellard | } |
416 | bb36d470 | bellard | } |
417 | bb36d470 | bellard | |
418 | bb36d470 | bellard | static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) |
419 | bb36d470 | bellard | { |
420 | bb36d470 | bellard | UHCIState *s = opaque; |
421 | bb36d470 | bellard | uint32_t val; |
422 | bb36d470 | bellard | |
423 | bb36d470 | bellard | addr &= 0x1f;
|
424 | bb36d470 | bellard | switch(addr) {
|
425 | bb36d470 | bellard | case 0x0c: |
426 | bb36d470 | bellard | val = s->sof_timing; |
427 | d80cfb3f | pbrook | break;
|
428 | bb36d470 | bellard | default:
|
429 | bb36d470 | bellard | val = 0xff;
|
430 | bb36d470 | bellard | break;
|
431 | bb36d470 | bellard | } |
432 | bb36d470 | bellard | return val;
|
433 | bb36d470 | bellard | } |
434 | bb36d470 | bellard | |
435 | bb36d470 | bellard | static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
436 | bb36d470 | bellard | { |
437 | bb36d470 | bellard | UHCIState *s = opaque; |
438 | 3b46e624 | ths | |
439 | bb36d470 | bellard | addr &= 0x1f;
|
440 | 54f254f9 | aliguori | dprintf("uhci: writew port=0x%04x val=0x%04x\n", addr, val);
|
441 | 54f254f9 | aliguori | |
442 | bb36d470 | bellard | switch(addr) {
|
443 | bb36d470 | bellard | case 0x00: |
444 | bb36d470 | bellard | if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
|
445 | bb36d470 | bellard | /* start frame processing */
|
446 | bb36d470 | bellard | qemu_mod_timer(s->frame_timer, qemu_get_clock(vm_clock)); |
447 | 52328140 | bellard | s->status &= ~UHCI_STS_HCHALTED; |
448 | 467d409f | bellard | } else if (!(val & UHCI_CMD_RS)) { |
449 | 52328140 | bellard | s->status |= UHCI_STS_HCHALTED; |
450 | bb36d470 | bellard | } |
451 | bb36d470 | bellard | if (val & UHCI_CMD_GRESET) {
|
452 | bb36d470 | bellard | UHCIPort *port; |
453 | bb36d470 | bellard | USBDevice *dev; |
454 | bb36d470 | bellard | int i;
|
455 | bb36d470 | bellard | |
456 | bb36d470 | bellard | /* send reset on the USB bus */
|
457 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
458 | bb36d470 | bellard | port = &s->ports[i]; |
459 | a594cfbf | bellard | dev = port->port.dev; |
460 | bb36d470 | bellard | if (dev) {
|
461 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_RESET); |
462 | bb36d470 | bellard | } |
463 | bb36d470 | bellard | } |
464 | bb36d470 | bellard | uhci_reset(s); |
465 | bb36d470 | bellard | return;
|
466 | bb36d470 | bellard | } |
467 | 5e9ab4c4 | bellard | if (val & UHCI_CMD_HCRESET) {
|
468 | bb36d470 | bellard | uhci_reset(s); |
469 | bb36d470 | bellard | return;
|
470 | bb36d470 | bellard | } |
471 | bb36d470 | bellard | s->cmd = val; |
472 | bb36d470 | bellard | break;
|
473 | bb36d470 | bellard | case 0x02: |
474 | bb36d470 | bellard | s->status &= ~val; |
475 | bb36d470 | bellard | /* XXX: the chip spec is not coherent, so we add a hidden
|
476 | bb36d470 | bellard | register to distinguish between IOC and SPD */
|
477 | bb36d470 | bellard | if (val & UHCI_STS_USBINT)
|
478 | bb36d470 | bellard | s->status2 = 0;
|
479 | bb36d470 | bellard | uhci_update_irq(s); |
480 | bb36d470 | bellard | break;
|
481 | bb36d470 | bellard | case 0x04: |
482 | bb36d470 | bellard | s->intr = val; |
483 | bb36d470 | bellard | uhci_update_irq(s); |
484 | bb36d470 | bellard | break;
|
485 | bb36d470 | bellard | case 0x06: |
486 | bb36d470 | bellard | if (s->status & UHCI_STS_HCHALTED)
|
487 | bb36d470 | bellard | s->frnum = val & 0x7ff;
|
488 | bb36d470 | bellard | break;
|
489 | bb36d470 | bellard | case 0x10 ... 0x1f: |
490 | bb36d470 | bellard | { |
491 | bb36d470 | bellard | UHCIPort *port; |
492 | bb36d470 | bellard | USBDevice *dev; |
493 | bb36d470 | bellard | int n;
|
494 | bb36d470 | bellard | |
495 | bb36d470 | bellard | n = (addr >> 1) & 7; |
496 | bb36d470 | bellard | if (n >= NB_PORTS)
|
497 | bb36d470 | bellard | return;
|
498 | bb36d470 | bellard | port = &s->ports[n]; |
499 | a594cfbf | bellard | dev = port->port.dev; |
500 | bb36d470 | bellard | if (dev) {
|
501 | bb36d470 | bellard | /* port reset */
|
502 | 5fafdf24 | ths | if ( (val & UHCI_PORT_RESET) &&
|
503 | bb36d470 | bellard | !(port->ctrl & UHCI_PORT_RESET) ) { |
504 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_RESET); |
505 | bb36d470 | bellard | } |
506 | bb36d470 | bellard | } |
507 | bb36d470 | bellard | port->ctrl = (port->ctrl & 0x01fb) | (val & ~0x01fb); |
508 | bb36d470 | bellard | /* some bits are reset when a '1' is written to them */
|
509 | bb36d470 | bellard | port->ctrl &= ~(val & 0x000a);
|
510 | bb36d470 | bellard | } |
511 | bb36d470 | bellard | break;
|
512 | bb36d470 | bellard | } |
513 | bb36d470 | bellard | } |
514 | bb36d470 | bellard | |
515 | bb36d470 | bellard | static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) |
516 | bb36d470 | bellard | { |
517 | bb36d470 | bellard | UHCIState *s = opaque; |
518 | bb36d470 | bellard | uint32_t val; |
519 | bb36d470 | bellard | |
520 | bb36d470 | bellard | addr &= 0x1f;
|
521 | bb36d470 | bellard | switch(addr) {
|
522 | bb36d470 | bellard | case 0x00: |
523 | bb36d470 | bellard | val = s->cmd; |
524 | bb36d470 | bellard | break;
|
525 | bb36d470 | bellard | case 0x02: |
526 | bb36d470 | bellard | val = s->status; |
527 | bb36d470 | bellard | break;
|
528 | bb36d470 | bellard | case 0x04: |
529 | bb36d470 | bellard | val = s->intr; |
530 | bb36d470 | bellard | break;
|
531 | bb36d470 | bellard | case 0x06: |
532 | bb36d470 | bellard | val = s->frnum; |
533 | bb36d470 | bellard | break;
|
534 | bb36d470 | bellard | case 0x10 ... 0x1f: |
535 | bb36d470 | bellard | { |
536 | bb36d470 | bellard | UHCIPort *port; |
537 | bb36d470 | bellard | int n;
|
538 | bb36d470 | bellard | n = (addr >> 1) & 7; |
539 | 5fafdf24 | ths | if (n >= NB_PORTS)
|
540 | bb36d470 | bellard | goto read_default;
|
541 | bb36d470 | bellard | port = &s->ports[n]; |
542 | bb36d470 | bellard | val = port->ctrl; |
543 | bb36d470 | bellard | } |
544 | bb36d470 | bellard | break;
|
545 | bb36d470 | bellard | default:
|
546 | bb36d470 | bellard | read_default:
|
547 | bb36d470 | bellard | val = 0xff7f; /* disabled port */ |
548 | bb36d470 | bellard | break;
|
549 | bb36d470 | bellard | } |
550 | 54f254f9 | aliguori | |
551 | 54f254f9 | aliguori | dprintf("uhci: readw port=0x%04x val=0x%04x\n", addr, val);
|
552 | 54f254f9 | aliguori | |
553 | bb36d470 | bellard | return val;
|
554 | bb36d470 | bellard | } |
555 | bb36d470 | bellard | |
556 | bb36d470 | bellard | static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
557 | bb36d470 | bellard | { |
558 | bb36d470 | bellard | UHCIState *s = opaque; |
559 | bb36d470 | bellard | |
560 | bb36d470 | bellard | addr &= 0x1f;
|
561 | 54f254f9 | aliguori | dprintf("uhci: writel port=0x%04x val=0x%08x\n", addr, val);
|
562 | 54f254f9 | aliguori | |
563 | bb36d470 | bellard | switch(addr) {
|
564 | bb36d470 | bellard | case 0x08: |
565 | bb36d470 | bellard | s->fl_base_addr = val & ~0xfff;
|
566 | bb36d470 | bellard | break;
|
567 | bb36d470 | bellard | } |
568 | bb36d470 | bellard | } |
569 | bb36d470 | bellard | |
570 | bb36d470 | bellard | static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) |
571 | bb36d470 | bellard | { |
572 | bb36d470 | bellard | UHCIState *s = opaque; |
573 | bb36d470 | bellard | uint32_t val; |
574 | bb36d470 | bellard | |
575 | bb36d470 | bellard | addr &= 0x1f;
|
576 | bb36d470 | bellard | switch(addr) {
|
577 | bb36d470 | bellard | case 0x08: |
578 | bb36d470 | bellard | val = s->fl_base_addr; |
579 | bb36d470 | bellard | break;
|
580 | bb36d470 | bellard | default:
|
581 | bb36d470 | bellard | val = 0xffffffff;
|
582 | bb36d470 | bellard | break;
|
583 | bb36d470 | bellard | } |
584 | bb36d470 | bellard | return val;
|
585 | bb36d470 | bellard | } |
586 | bb36d470 | bellard | |
587 | 96217e31 | ths | /* signal resume if controller suspended */
|
588 | 96217e31 | ths | static void uhci_resume (void *opaque) |
589 | 96217e31 | ths | { |
590 | 96217e31 | ths | UHCIState *s = (UHCIState *)opaque; |
591 | 96217e31 | ths | |
592 | 96217e31 | ths | if (!s)
|
593 | 96217e31 | ths | return;
|
594 | 96217e31 | ths | |
595 | 96217e31 | ths | if (s->cmd & UHCI_CMD_EGSM) {
|
596 | 96217e31 | ths | s->cmd |= UHCI_CMD_FGR; |
597 | 96217e31 | ths | s->status |= UHCI_STS_RD; |
598 | 96217e31 | ths | uhci_update_irq(s); |
599 | 96217e31 | ths | } |
600 | 96217e31 | ths | } |
601 | 96217e31 | ths | |
602 | bb36d470 | bellard | static void uhci_attach(USBPort *port1, USBDevice *dev) |
603 | bb36d470 | bellard | { |
604 | bb36d470 | bellard | UHCIState *s = port1->opaque; |
605 | bb36d470 | bellard | UHCIPort *port = &s->ports[port1->index]; |
606 | bb36d470 | bellard | |
607 | bb36d470 | bellard | if (dev) {
|
608 | a594cfbf | bellard | if (port->port.dev) {
|
609 | bb36d470 | bellard | usb_attach(port1, NULL);
|
610 | bb36d470 | bellard | } |
611 | bb36d470 | bellard | /* set connect status */
|
612 | 61064870 | pbrook | port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; |
613 | 61064870 | pbrook | |
614 | bb36d470 | bellard | /* update speed */
|
615 | bb36d470 | bellard | if (dev->speed == USB_SPEED_LOW)
|
616 | bb36d470 | bellard | port->ctrl |= UHCI_PORT_LSDA; |
617 | bb36d470 | bellard | else
|
618 | bb36d470 | bellard | port->ctrl &= ~UHCI_PORT_LSDA; |
619 | 96217e31 | ths | |
620 | 96217e31 | ths | uhci_resume(s); |
621 | 96217e31 | ths | |
622 | a594cfbf | bellard | port->port.dev = dev; |
623 | bb36d470 | bellard | /* send the attach message */
|
624 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_ATTACH); |
625 | bb36d470 | bellard | } else {
|
626 | bb36d470 | bellard | /* set connect status */
|
627 | 61064870 | pbrook | if (port->ctrl & UHCI_PORT_CCS) {
|
628 | 61064870 | pbrook | port->ctrl &= ~UHCI_PORT_CCS; |
629 | 61064870 | pbrook | port->ctrl |= UHCI_PORT_CSC; |
630 | bb36d470 | bellard | } |
631 | bb36d470 | bellard | /* disable port */
|
632 | bb36d470 | bellard | if (port->ctrl & UHCI_PORT_EN) {
|
633 | bb36d470 | bellard | port->ctrl &= ~UHCI_PORT_EN; |
634 | bb36d470 | bellard | port->ctrl |= UHCI_PORT_ENC; |
635 | bb36d470 | bellard | } |
636 | 96217e31 | ths | |
637 | 96217e31 | ths | uhci_resume(s); |
638 | 96217e31 | ths | |
639 | a594cfbf | bellard | dev = port->port.dev; |
640 | bb36d470 | bellard | if (dev) {
|
641 | bb36d470 | bellard | /* send the detach message */
|
642 | 4d611c9a | pbrook | usb_send_msg(dev, USB_MSG_DETACH); |
643 | bb36d470 | bellard | } |
644 | a594cfbf | bellard | port->port.dev = NULL;
|
645 | bb36d470 | bellard | } |
646 | bb36d470 | bellard | } |
647 | bb36d470 | bellard | |
648 | 4d611c9a | pbrook | static int uhci_broadcast_packet(UHCIState *s, USBPacket *p) |
649 | bb36d470 | bellard | { |
650 | bb36d470 | bellard | int i, ret;
|
651 | bb36d470 | bellard | |
652 | 54f254f9 | aliguori | dprintf("uhci: packet enter. pid %s addr 0x%02x ep %d len %d\n",
|
653 | 54f254f9 | aliguori | pid2str(p->pid), p->devaddr, p->devep, p->len); |
654 | 5d808245 | aurel32 | if (p->pid == USB_TOKEN_OUT || p->pid == USB_TOKEN_SETUP)
|
655 | 54f254f9 | aliguori | dump_data(p->data, p->len); |
656 | 54f254f9 | aliguori | |
657 | 54f254f9 | aliguori | ret = USB_RET_NODEV; |
658 | 54f254f9 | aliguori | for (i = 0; i < NB_PORTS && ret == USB_RET_NODEV; i++) { |
659 | 54f254f9 | aliguori | UHCIPort *port = &s->ports[i]; |
660 | 54f254f9 | aliguori | USBDevice *dev = port->port.dev; |
661 | 54f254f9 | aliguori | |
662 | 54f254f9 | aliguori | if (dev && (port->ctrl & UHCI_PORT_EN))
|
663 | 4d611c9a | pbrook | ret = dev->handle_packet(dev, p); |
664 | bb36d470 | bellard | } |
665 | 54f254f9 | aliguori | |
666 | 54f254f9 | aliguori | dprintf("uhci: packet exit. ret %d len %d\n", ret, p->len);
|
667 | 54f254f9 | aliguori | if (p->pid == USB_TOKEN_IN && ret > 0) |
668 | 54f254f9 | aliguori | dump_data(p->data, ret); |
669 | 54f254f9 | aliguori | |
670 | 54f254f9 | aliguori | return ret;
|
671 | bb36d470 | bellard | } |
672 | bb36d470 | bellard | |
673 | 54f254f9 | aliguori | static void uhci_async_complete(USBPacket * packet, void *opaque); |
674 | 54f254f9 | aliguori | static void uhci_process_frame(UHCIState *s); |
675 | 4d611c9a | pbrook | |
676 | bb36d470 | bellard | /* return -1 if fatal error (frame must be stopped)
|
677 | bb36d470 | bellard | 0 if TD successful
|
678 | bb36d470 | bellard | 1 if TD unsuccessful or inactive
|
679 | bb36d470 | bellard | */
|
680 | 54f254f9 | aliguori | static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) |
681 | bb36d470 | bellard | { |
682 | 54f254f9 | aliguori | int len = 0, max_len, err, ret; |
683 | bb36d470 | bellard | uint8_t pid; |
684 | bb36d470 | bellard | |
685 | 54f254f9 | aliguori | max_len = ((td->token >> 21) + 1) & 0x7ff; |
686 | 54f254f9 | aliguori | pid = td->token & 0xff;
|
687 | 54f254f9 | aliguori | |
688 | 54f254f9 | aliguori | ret = async->packet.len; |
689 | 54f254f9 | aliguori | |
690 | 54f254f9 | aliguori | if (td->ctrl & TD_CTRL_IOC)
|
691 | bb36d470 | bellard | *int_mask |= 0x01;
|
692 | 3b46e624 | ths | |
693 | 54f254f9 | aliguori | if (td->ctrl & TD_CTRL_IOS)
|
694 | 54f254f9 | aliguori | td->ctrl &= ~TD_CTRL_ACTIVE; |
695 | bb36d470 | bellard | |
696 | 54f254f9 | aliguori | if (ret < 0) |
697 | 54f254f9 | aliguori | goto out;
|
698 | b9dc033c | balrog | |
699 | 54f254f9 | aliguori | len = async->packet.len; |
700 | 54f254f9 | aliguori | td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
701 | 54f254f9 | aliguori | |
702 | 54f254f9 | aliguori | /* The NAK bit may have been set by a previous frame, so clear it
|
703 | 54f254f9 | aliguori | here. The docs are somewhat unclear, but win2k relies on this
|
704 | 54f254f9 | aliguori | behavior. */
|
705 | 54f254f9 | aliguori | td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); |
706 | 54f254f9 | aliguori | |
707 | 54f254f9 | aliguori | if (pid == USB_TOKEN_IN) {
|
708 | 54f254f9 | aliguori | if (len > max_len) {
|
709 | 4d611c9a | pbrook | len = max_len; |
710 | 54f254f9 | aliguori | ret = USB_RET_BABBLE; |
711 | 54f254f9 | aliguori | goto out;
|
712 | 4d611c9a | pbrook | } |
713 | b9dc033c | balrog | |
714 | 54f254f9 | aliguori | if (len > 0) { |
715 | 54f254f9 | aliguori | /* write the data back */
|
716 | 54f254f9 | aliguori | cpu_physical_memory_write(td->buffer, async->buffer, len); |
717 | 54f254f9 | aliguori | } |
718 | 54f254f9 | aliguori | |
719 | 54f254f9 | aliguori | if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
|
720 | bb36d470 | bellard | *int_mask |= 0x02;
|
721 | bb36d470 | bellard | /* short packet: do not update QH */
|
722 | 54f254f9 | aliguori | dprintf("uhci: short packet. td 0x%x token 0x%x\n", async->td, async->token);
|
723 | bb36d470 | bellard | return 1; |
724 | bb36d470 | bellard | } |
725 | 54f254f9 | aliguori | } |
726 | 54f254f9 | aliguori | |
727 | 54f254f9 | aliguori | /* success */
|
728 | 54f254f9 | aliguori | return 0; |
729 | 54f254f9 | aliguori | |
730 | 54f254f9 | aliguori | out:
|
731 | 54f254f9 | aliguori | switch(ret) {
|
732 | 54f254f9 | aliguori | case USB_RET_STALL:
|
733 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_STALL; |
734 | 54f254f9 | aliguori | td->ctrl &= ~TD_CTRL_ACTIVE; |
735 | 54f254f9 | aliguori | return 1; |
736 | 54f254f9 | aliguori | |
737 | 54f254f9 | aliguori | case USB_RET_BABBLE:
|
738 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; |
739 | 54f254f9 | aliguori | td->ctrl &= ~TD_CTRL_ACTIVE; |
740 | 54f254f9 | aliguori | /* frame interrupted */
|
741 | 54f254f9 | aliguori | return -1; |
742 | 54f254f9 | aliguori | |
743 | 54f254f9 | aliguori | case USB_RET_NAK:
|
744 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_NAK; |
745 | 54f254f9 | aliguori | if (pid == USB_TOKEN_SETUP)
|
746 | 54f254f9 | aliguori | break;
|
747 | 54f254f9 | aliguori | return 1; |
748 | 54f254f9 | aliguori | |
749 | 54f254f9 | aliguori | case USB_RET_NODEV:
|
750 | 54f254f9 | aliguori | default:
|
751 | 54f254f9 | aliguori | break;
|
752 | 54f254f9 | aliguori | } |
753 | 54f254f9 | aliguori | |
754 | 54f254f9 | aliguori | /* Retry the TD if error count is not zero */
|
755 | 54f254f9 | aliguori | |
756 | 54f254f9 | aliguori | td->ctrl |= TD_CTRL_TIMEOUT; |
757 | 54f254f9 | aliguori | err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
|
758 | 54f254f9 | aliguori | if (err != 0) { |
759 | 54f254f9 | aliguori | err--; |
760 | 54f254f9 | aliguori | if (err == 0) { |
761 | bb36d470 | bellard | td->ctrl &= ~TD_CTRL_ACTIVE; |
762 | 54f254f9 | aliguori | s->status |= UHCI_STS_USBERR; |
763 | 54f254f9 | aliguori | uhci_update_irq(s); |
764 | bb36d470 | bellard | } |
765 | bb36d470 | bellard | } |
766 | 54f254f9 | aliguori | td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
|
767 | 54f254f9 | aliguori | (err << TD_CTRL_ERROR_SHIFT); |
768 | 54f254f9 | aliguori | return 1; |
769 | bb36d470 | bellard | } |
770 | bb36d470 | bellard | |
771 | 54f254f9 | aliguori | static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask) |
772 | 54f254f9 | aliguori | { |
773 | 54f254f9 | aliguori | UHCIAsync *async; |
774 | 5d808245 | aurel32 | int len = 0, max_len; |
775 | 54f254f9 | aliguori | uint8_t pid; |
776 | 54f254f9 | aliguori | |
777 | 54f254f9 | aliguori | /* Is active ? */
|
778 | 54f254f9 | aliguori | if (!(td->ctrl & TD_CTRL_ACTIVE))
|
779 | 54f254f9 | aliguori | return 1; |
780 | 54f254f9 | aliguori | |
781 | 54f254f9 | aliguori | async = uhci_async_find_td(s, addr, td->token); |
782 | 54f254f9 | aliguori | if (async) {
|
783 | 54f254f9 | aliguori | /* Already submitted */
|
784 | 54f254f9 | aliguori | async->valid = 10;
|
785 | 54f254f9 | aliguori | |
786 | 54f254f9 | aliguori | if (!async->done)
|
787 | 54f254f9 | aliguori | return 1; |
788 | 54f254f9 | aliguori | |
789 | 54f254f9 | aliguori | uhci_async_unlink(s, async); |
790 | 54f254f9 | aliguori | goto done;
|
791 | 54f254f9 | aliguori | } |
792 | 54f254f9 | aliguori | |
793 | 54f254f9 | aliguori | /* Allocate new packet */
|
794 | 54f254f9 | aliguori | async = uhci_async_alloc(s); |
795 | 54f254f9 | aliguori | if (!async)
|
796 | 54f254f9 | aliguori | return 1; |
797 | 54f254f9 | aliguori | |
798 | 54f254f9 | aliguori | async->valid = 10;
|
799 | 54f254f9 | aliguori | async->td = addr; |
800 | 54f254f9 | aliguori | async->token = td->token; |
801 | 54f254f9 | aliguori | |
802 | 54f254f9 | aliguori | max_len = ((td->token >> 21) + 1) & 0x7ff; |
803 | 54f254f9 | aliguori | pid = td->token & 0xff;
|
804 | 54f254f9 | aliguori | |
805 | 54f254f9 | aliguori | async->packet.pid = pid; |
806 | 54f254f9 | aliguori | async->packet.devaddr = (td->token >> 8) & 0x7f; |
807 | 54f254f9 | aliguori | async->packet.devep = (td->token >> 15) & 0xf; |
808 | 54f254f9 | aliguori | async->packet.data = async->buffer; |
809 | 54f254f9 | aliguori | async->packet.len = max_len; |
810 | 54f254f9 | aliguori | async->packet.complete_cb = uhci_async_complete; |
811 | 54f254f9 | aliguori | async->packet.complete_opaque = s; |
812 | 54f254f9 | aliguori | |
813 | 54f254f9 | aliguori | switch(pid) {
|
814 | 54f254f9 | aliguori | case USB_TOKEN_OUT:
|
815 | 54f254f9 | aliguori | case USB_TOKEN_SETUP:
|
816 | 54f254f9 | aliguori | cpu_physical_memory_read(td->buffer, async->buffer, max_len); |
817 | 5d808245 | aurel32 | len = uhci_broadcast_packet(s, &async->packet); |
818 | 5d808245 | aurel32 | if (len >= 0) |
819 | 5d808245 | aurel32 | len = max_len; |
820 | 54f254f9 | aliguori | break;
|
821 | 54f254f9 | aliguori | |
822 | 54f254f9 | aliguori | case USB_TOKEN_IN:
|
823 | 5d808245 | aurel32 | len = uhci_broadcast_packet(s, &async->packet); |
824 | 54f254f9 | aliguori | break;
|
825 | 54f254f9 | aliguori | |
826 | 54f254f9 | aliguori | default:
|
827 | 54f254f9 | aliguori | /* invalid pid : frame interrupted */
|
828 | 54f254f9 | aliguori | uhci_async_free(s, async); |
829 | 54f254f9 | aliguori | s->status |= UHCI_STS_HCPERR; |
830 | 54f254f9 | aliguori | uhci_update_irq(s); |
831 | 54f254f9 | aliguori | return -1; |
832 | 54f254f9 | aliguori | } |
833 | 54f254f9 | aliguori | |
834 | 5d808245 | aurel32 | if (len == USB_RET_ASYNC) {
|
835 | 54f254f9 | aliguori | uhci_async_link(s, async); |
836 | 54f254f9 | aliguori | return 2; |
837 | 54f254f9 | aliguori | } |
838 | 54f254f9 | aliguori | |
839 | 5d808245 | aurel32 | async->packet.len = len; |
840 | 54f254f9 | aliguori | |
841 | 54f254f9 | aliguori | done:
|
842 | 5d808245 | aurel32 | len = uhci_complete_td(s, td, async, int_mask); |
843 | 54f254f9 | aliguori | uhci_async_free(s, async); |
844 | 5d808245 | aurel32 | return len;
|
845 | 54f254f9 | aliguori | } |
846 | 54f254f9 | aliguori | |
847 | 54f254f9 | aliguori | static void uhci_async_complete(USBPacket *packet, void *opaque) |
848 | 4d611c9a | pbrook | { |
849 | 4d611c9a | pbrook | UHCIState *s = opaque; |
850 | 54f254f9 | aliguori | UHCIAsync *async = (UHCIAsync *) packet; |
851 | 54f254f9 | aliguori | |
852 | 54f254f9 | aliguori | dprintf("uhci: async complete. td 0x%x token 0x%x\n", async->td, async->token);
|
853 | 54f254f9 | aliguori | |
854 | 54f254f9 | aliguori | async->done = 1;
|
855 | 54f254f9 | aliguori | |
856 | 54f254f9 | aliguori | uhci_process_frame(s); |
857 | 54f254f9 | aliguori | } |
858 | 54f254f9 | aliguori | |
859 | 54f254f9 | aliguori | static int is_valid(uint32_t link) |
860 | 54f254f9 | aliguori | { |
861 | 54f254f9 | aliguori | return (link & 1) == 0; |
862 | 54f254f9 | aliguori | } |
863 | 54f254f9 | aliguori | |
864 | 54f254f9 | aliguori | static int is_qh(uint32_t link) |
865 | 54f254f9 | aliguori | { |
866 | 54f254f9 | aliguori | return (link & 2) != 0; |
867 | 54f254f9 | aliguori | } |
868 | 54f254f9 | aliguori | |
869 | 54f254f9 | aliguori | static int depth_first(uint32_t link) |
870 | 54f254f9 | aliguori | { |
871 | 54f254f9 | aliguori | return (link & 4) != 0; |
872 | 54f254f9 | aliguori | } |
873 | 54f254f9 | aliguori | |
874 | 54f254f9 | aliguori | /* QH DB used for detecting QH loops */
|
875 | 54f254f9 | aliguori | #define UHCI_MAX_QUEUES 128 |
876 | 54f254f9 | aliguori | typedef struct { |
877 | 54f254f9 | aliguori | uint32_t addr[UHCI_MAX_QUEUES]; |
878 | 54f254f9 | aliguori | int count;
|
879 | 54f254f9 | aliguori | } QhDb; |
880 | 54f254f9 | aliguori | |
881 | 54f254f9 | aliguori | static void qhdb_reset(QhDb *db) |
882 | 54f254f9 | aliguori | { |
883 | 54f254f9 | aliguori | db->count = 0;
|
884 | 54f254f9 | aliguori | } |
885 | 54f254f9 | aliguori | |
886 | 54f254f9 | aliguori | /* Add QH to DB. Returns 1 if already present or DB is full. */
|
887 | 54f254f9 | aliguori | static int qhdb_insert(QhDb *db, uint32_t addr) |
888 | 54f254f9 | aliguori | { |
889 | 54f254f9 | aliguori | int i;
|
890 | 54f254f9 | aliguori | for (i = 0; i < db->count; i++) |
891 | 54f254f9 | aliguori | if (db->addr[i] == addr)
|
892 | 54f254f9 | aliguori | return 1; |
893 | 54f254f9 | aliguori | |
894 | 54f254f9 | aliguori | if (db->count >= UHCI_MAX_QUEUES)
|
895 | 54f254f9 | aliguori | return 1; |
896 | 54f254f9 | aliguori | |
897 | 54f254f9 | aliguori | db->addr[db->count++] = addr; |
898 | 54f254f9 | aliguori | return 0; |
899 | 54f254f9 | aliguori | } |
900 | 54f254f9 | aliguori | |
901 | 54f254f9 | aliguori | static void uhci_process_frame(UHCIState *s) |
902 | 54f254f9 | aliguori | { |
903 | 54f254f9 | aliguori | uint32_t frame_addr, link, old_td_ctrl, val, int_mask; |
904 | 54f254f9 | aliguori | uint32_t curr_qh; |
905 | 54f254f9 | aliguori | int cnt, ret;
|
906 | 4d611c9a | pbrook | UHCI_TD td; |
907 | 54f254f9 | aliguori | UHCI_QH qh; |
908 | 54f254f9 | aliguori | QhDb qhdb; |
909 | 4d611c9a | pbrook | |
910 | 54f254f9 | aliguori | frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
911 | 54f254f9 | aliguori | |
912 | 54f254f9 | aliguori | dprintf("uhci: processing frame %d addr 0x%x\n" , s->frnum, frame_addr);
|
913 | 54f254f9 | aliguori | |
914 | 54f254f9 | aliguori | cpu_physical_memory_read(frame_addr, (uint8_t *)&link, 4);
|
915 | 54f254f9 | aliguori | le32_to_cpus(&link); |
916 | b9dc033c | balrog | |
917 | 54f254f9 | aliguori | int_mask = 0;
|
918 | 54f254f9 | aliguori | curr_qh = 0;
|
919 | 54f254f9 | aliguori | |
920 | 54f254f9 | aliguori | qhdb_reset(&qhdb); |
921 | 54f254f9 | aliguori | |
922 | 54f254f9 | aliguori | for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
|
923 | 54f254f9 | aliguori | if (is_qh(link)) {
|
924 | 54f254f9 | aliguori | /* QH */
|
925 | 54f254f9 | aliguori | |
926 | 54f254f9 | aliguori | if (qhdb_insert(&qhdb, link)) {
|
927 | 54f254f9 | aliguori | /*
|
928 | 54f254f9 | aliguori | * We're going in circles. Which is not a bug because
|
929 | 54f254f9 | aliguori | * HCD is allowed to do that as part of the BW management.
|
930 | 54f254f9 | aliguori | * In our case though it makes no sense to spin here. Sync transations
|
931 | 54f254f9 | aliguori | * are already done, and async completion handler will re-process
|
932 | 54f254f9 | aliguori | * the frame when something is ready.
|
933 | 54f254f9 | aliguori | */
|
934 | 54f254f9 | aliguori | dprintf("uhci: detected loop. qh 0x%x\n", link);
|
935 | 54f254f9 | aliguori | break;
|
936 | 54f254f9 | aliguori | } |
937 | 54f254f9 | aliguori | |
938 | 54f254f9 | aliguori | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &qh, sizeof(qh)); |
939 | 54f254f9 | aliguori | le32_to_cpus(&qh.link); |
940 | 54f254f9 | aliguori | le32_to_cpus(&qh.el_link); |
941 | 54f254f9 | aliguori | |
942 | 54f254f9 | aliguori | dprintf("uhci: QH 0x%x load. link 0x%x elink 0x%x\n",
|
943 | 54f254f9 | aliguori | link, qh.link, qh.el_link); |
944 | 54f254f9 | aliguori | |
945 | 54f254f9 | aliguori | if (!is_valid(qh.el_link)) {
|
946 | 54f254f9 | aliguori | /* QH w/o elements */
|
947 | 54f254f9 | aliguori | curr_qh = 0;
|
948 | 54f254f9 | aliguori | link = qh.link; |
949 | 54f254f9 | aliguori | } else {
|
950 | 54f254f9 | aliguori | /* QH with elements */
|
951 | 54f254f9 | aliguori | curr_qh = link; |
952 | 54f254f9 | aliguori | link = qh.el_link; |
953 | 54f254f9 | aliguori | } |
954 | 54f254f9 | aliguori | continue;
|
955 | 54f254f9 | aliguori | } |
956 | 54f254f9 | aliguori | |
957 | 54f254f9 | aliguori | /* TD */
|
958 | 54f254f9 | aliguori | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &td, sizeof(td)); |
959 | b9dc033c | balrog | le32_to_cpus(&td.link); |
960 | b9dc033c | balrog | le32_to_cpus(&td.ctrl); |
961 | b9dc033c | balrog | le32_to_cpus(&td.token); |
962 | b9dc033c | balrog | le32_to_cpus(&td.buffer); |
963 | b9dc033c | balrog | |
964 | 54f254f9 | aliguori | dprintf("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
965 | 54f254f9 | aliguori | link, td.link, td.ctrl, td.token, curr_qh); |
966 | 54f254f9 | aliguori | |
967 | 54f254f9 | aliguori | old_td_ctrl = td.ctrl; |
968 | 54f254f9 | aliguori | ret = uhci_handle_td(s, link, &td, &int_mask); |
969 | b9dc033c | balrog | if (old_td_ctrl != td.ctrl) {
|
970 | 54f254f9 | aliguori | /* update the status bits of the TD */
|
971 | b9dc033c | balrog | val = cpu_to_le32(td.ctrl); |
972 | b9dc033c | balrog | cpu_physical_memory_write((link & ~0xf) + 4, |
973 | 54f254f9 | aliguori | (const uint8_t *)&val, sizeof(val)); |
974 | b9dc033c | balrog | } |
975 | 54f254f9 | aliguori | |
976 | 54f254f9 | aliguori | if (ret < 0) { |
977 | 54f254f9 | aliguori | /* interrupted frame */
|
978 | 54f254f9 | aliguori | break;
|
979 | b9dc033c | balrog | } |
980 | b9dc033c | balrog | |
981 | 54f254f9 | aliguori | if (ret == 2 || ret == 1) { |
982 | 54f254f9 | aliguori | dprintf("uhci: TD 0x%x %s. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
983 | 54f254f9 | aliguori | link, ret == 2 ? "pend" : "skip", |
984 | 54f254f9 | aliguori | td.link, td.ctrl, td.token, curr_qh); |
985 | b9dc033c | balrog | |
986 | 54f254f9 | aliguori | link = curr_qh ? qh.link : td.link; |
987 | 54f254f9 | aliguori | continue;
|
988 | 4d611c9a | pbrook | } |
989 | 54f254f9 | aliguori | |
990 | 54f254f9 | aliguori | /* completed TD */
|
991 | 54f254f9 | aliguori | |
992 | 54f254f9 | aliguori | dprintf("uhci: TD 0x%x done. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
993 | 54f254f9 | aliguori | link, td.link, td.ctrl, td.token, curr_qh); |
994 | 54f254f9 | aliguori | |
995 | 54f254f9 | aliguori | link = td.link; |
996 | 54f254f9 | aliguori | |
997 | 54f254f9 | aliguori | if (curr_qh) {
|
998 | 54f254f9 | aliguori | /* update QH element link */
|
999 | 54f254f9 | aliguori | qh.el_link = link; |
1000 | 4d611c9a | pbrook | val = cpu_to_le32(qh.el_link); |
1001 | 54f254f9 | aliguori | cpu_physical_memory_write((curr_qh & ~0xf) + 4, |
1002 | 54f254f9 | aliguori | (const uint8_t *)&val, sizeof(val)); |
1003 | 54f254f9 | aliguori | |
1004 | 54f254f9 | aliguori | if (!depth_first(link)) {
|
1005 | 54f254f9 | aliguori | /* done with this QH */
|
1006 | 54f254f9 | aliguori | |
1007 | 54f254f9 | aliguori | dprintf("uhci: QH 0x%x done. link 0x%x elink 0x%x\n",
|
1008 | 54f254f9 | aliguori | curr_qh, qh.link, qh.el_link); |
1009 | 54f254f9 | aliguori | |
1010 | 54f254f9 | aliguori | curr_qh = 0;
|
1011 | 54f254f9 | aliguori | link = qh.link; |
1012 | 54f254f9 | aliguori | } |
1013 | 4d611c9a | pbrook | } |
1014 | 54f254f9 | aliguori | |
1015 | 54f254f9 | aliguori | /* go to the next entry */
|
1016 | 4d611c9a | pbrook | } |
1017 | 54f254f9 | aliguori | |
1018 | 54f254f9 | aliguori | s->pending_int_mask = int_mask; |
1019 | 4d611c9a | pbrook | } |
1020 | 4d611c9a | pbrook | |
1021 | bb36d470 | bellard | static void uhci_frame_timer(void *opaque) |
1022 | bb36d470 | bellard | { |
1023 | bb36d470 | bellard | UHCIState *s = opaque; |
1024 | bb36d470 | bellard | int64_t expire_time; |
1025 | bb36d470 | bellard | |
1026 | bb36d470 | bellard | if (!(s->cmd & UHCI_CMD_RS)) {
|
1027 | 54f254f9 | aliguori | /* Full stop */
|
1028 | bb36d470 | bellard | qemu_del_timer(s->frame_timer); |
1029 | 52328140 | bellard | /* set hchalted bit in status - UHCI11D 2.1.2 */
|
1030 | 52328140 | bellard | s->status |= UHCI_STS_HCHALTED; |
1031 | 6f382b5e | aliguori | |
1032 | 6f382b5e | aliguori | dprintf("uhci: halted\n");
|
1033 | bb36d470 | bellard | return;
|
1034 | bb36d470 | bellard | } |
1035 | 54f254f9 | aliguori | |
1036 | 54f254f9 | aliguori | /* Complete the previous frame */
|
1037 | 4d611c9a | pbrook | if (s->pending_int_mask) {
|
1038 | 4d611c9a | pbrook | s->status2 |= s->pending_int_mask; |
1039 | 54f254f9 | aliguori | s->status |= UHCI_STS_USBINT; |
1040 | 4d611c9a | pbrook | uhci_update_irq(s); |
1041 | 4d611c9a | pbrook | } |
1042 | b9dc033c | balrog | |
1043 | 54f254f9 | aliguori | /* Start new frame */
|
1044 | 54f254f9 | aliguori | s->frnum = (s->frnum + 1) & 0x7ff; |
1045 | 54f254f9 | aliguori | |
1046 | 54f254f9 | aliguori | dprintf("uhci: new frame #%u\n" , s->frnum);
|
1047 | 54f254f9 | aliguori | |
1048 | 54f254f9 | aliguori | uhci_async_validate_begin(s); |
1049 | 54f254f9 | aliguori | |
1050 | 54f254f9 | aliguori | uhci_process_frame(s); |
1051 | 54f254f9 | aliguori | |
1052 | 54f254f9 | aliguori | uhci_async_validate_end(s); |
1053 | b9dc033c | balrog | |
1054 | bb36d470 | bellard | /* prepare the timer for the next frame */
|
1055 | 5fafdf24 | ths | expire_time = qemu_get_clock(vm_clock) + |
1056 | bb36d470 | bellard | (ticks_per_sec / FRAME_TIMER_FREQ); |
1057 | bb36d470 | bellard | qemu_mod_timer(s->frame_timer, expire_time); |
1058 | bb36d470 | bellard | } |
1059 | bb36d470 | bellard | |
1060 | 5fafdf24 | ths | static void uhci_map(PCIDevice *pci_dev, int region_num, |
1061 | bb36d470 | bellard | uint32_t addr, uint32_t size, int type)
|
1062 | bb36d470 | bellard | { |
1063 | bb36d470 | bellard | UHCIState *s = (UHCIState *)pci_dev; |
1064 | bb36d470 | bellard | |
1065 | bb36d470 | bellard | register_ioport_write(addr, 32, 2, uhci_ioport_writew, s); |
1066 | bb36d470 | bellard | register_ioport_read(addr, 32, 2, uhci_ioport_readw, s); |
1067 | bb36d470 | bellard | register_ioport_write(addr, 32, 4, uhci_ioport_writel, s); |
1068 | bb36d470 | bellard | register_ioport_read(addr, 32, 4, uhci_ioport_readl, s); |
1069 | bb36d470 | bellard | register_ioport_write(addr, 32, 1, uhci_ioport_writeb, s); |
1070 | bb36d470 | bellard | register_ioport_read(addr, 32, 1, uhci_ioport_readb, s); |
1071 | bb36d470 | bellard | } |
1072 | bb36d470 | bellard | |
1073 | afcc3cdf | ths | void usb_uhci_piix3_init(PCIBus *bus, int devfn) |
1074 | bb36d470 | bellard | { |
1075 | bb36d470 | bellard | UHCIState *s; |
1076 | bb36d470 | bellard | uint8_t *pci_conf; |
1077 | bb36d470 | bellard | int i;
|
1078 | bb36d470 | bellard | |
1079 | bb36d470 | bellard | s = (UHCIState *)pci_register_device(bus, |
1080 | bb36d470 | bellard | "USB-UHCI", sizeof(UHCIState), |
1081 | 502a5395 | pbrook | devfn, NULL, NULL); |
1082 | bb36d470 | bellard | pci_conf = s->dev.config; |
1083 | bb36d470 | bellard | pci_conf[0x00] = 0x86; |
1084 | bb36d470 | bellard | pci_conf[0x01] = 0x80; |
1085 | bb36d470 | bellard | pci_conf[0x02] = 0x20; |
1086 | bb36d470 | bellard | pci_conf[0x03] = 0x70; |
1087 | bb36d470 | bellard | pci_conf[0x08] = 0x01; // revision number |
1088 | bb36d470 | bellard | pci_conf[0x09] = 0x00; |
1089 | bb36d470 | bellard | pci_conf[0x0a] = 0x03; |
1090 | bb36d470 | bellard | pci_conf[0x0b] = 0x0c; |
1091 | bb36d470 | bellard | pci_conf[0x0e] = 0x00; // header_type |
1092 | f04308e4 | bellard | pci_conf[0x3d] = 4; // interrupt pin 3 |
1093 | 38ca0f6d | pbrook | pci_conf[0x60] = 0x10; // release number |
1094 | 3b46e624 | ths | |
1095 | bb36d470 | bellard | for(i = 0; i < NB_PORTS; i++) { |
1096 | 0d92ed30 | pbrook | qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach); |
1097 | bb36d470 | bellard | } |
1098 | bb36d470 | bellard | s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s); |
1099 | bb36d470 | bellard | |
1100 | bb36d470 | bellard | uhci_reset(s); |
1101 | bb36d470 | bellard | |
1102 | 38ca0f6d | pbrook | /* Use region 4 for consistency with real hardware. BSD guests seem
|
1103 | 38ca0f6d | pbrook | to rely on this. */
|
1104 | 5fafdf24 | ths | pci_register_io_region(&s->dev, 4, 0x20, |
1105 | bb36d470 | bellard | PCI_ADDRESS_SPACE_IO, uhci_map); |
1106 | 6f382b5e | aliguori | |
1107 | 6f382b5e | aliguori | register_savevm("uhci", 0, 1, uhci_save, uhci_load, s); |
1108 | bb36d470 | bellard | } |
1109 | afcc3cdf | ths | |
1110 | afcc3cdf | ths | void usb_uhci_piix4_init(PCIBus *bus, int devfn) |
1111 | afcc3cdf | ths | { |
1112 | afcc3cdf | ths | UHCIState *s; |
1113 | afcc3cdf | ths | uint8_t *pci_conf; |
1114 | afcc3cdf | ths | int i;
|
1115 | afcc3cdf | ths | |
1116 | afcc3cdf | ths | s = (UHCIState *)pci_register_device(bus, |
1117 | afcc3cdf | ths | "USB-UHCI", sizeof(UHCIState), |
1118 | afcc3cdf | ths | devfn, NULL, NULL); |
1119 | afcc3cdf | ths | pci_conf = s->dev.config; |
1120 | afcc3cdf | ths | pci_conf[0x00] = 0x86; |
1121 | afcc3cdf | ths | pci_conf[0x01] = 0x80; |
1122 | afcc3cdf | ths | pci_conf[0x02] = 0x12; |
1123 | afcc3cdf | ths | pci_conf[0x03] = 0x71; |
1124 | afcc3cdf | ths | pci_conf[0x08] = 0x01; // revision number |
1125 | afcc3cdf | ths | pci_conf[0x09] = 0x00; |
1126 | afcc3cdf | ths | pci_conf[0x0a] = 0x03; |
1127 | afcc3cdf | ths | pci_conf[0x0b] = 0x0c; |
1128 | afcc3cdf | ths | pci_conf[0x0e] = 0x00; // header_type |
1129 | afcc3cdf | ths | pci_conf[0x3d] = 4; // interrupt pin 3 |
1130 | afcc3cdf | ths | pci_conf[0x60] = 0x10; // release number |
1131 | afcc3cdf | ths | |
1132 | afcc3cdf | ths | for(i = 0; i < NB_PORTS; i++) { |
1133 | afcc3cdf | ths | qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach); |
1134 | afcc3cdf | ths | } |
1135 | afcc3cdf | ths | s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s); |
1136 | afcc3cdf | ths | |
1137 | afcc3cdf | ths | uhci_reset(s); |
1138 | afcc3cdf | ths | |
1139 | afcc3cdf | ths | /* Use region 4 for consistency with real hardware. BSD guests seem
|
1140 | afcc3cdf | ths | to rely on this. */
|
1141 | afcc3cdf | ths | pci_register_io_region(&s->dev, 4, 0x20, |
1142 | afcc3cdf | ths | PCI_ADDRESS_SPACE_IO, uhci_map); |
1143 | 54f254f9 | aliguori | |
1144 | 54f254f9 | aliguori | register_savevm("uhci", 0, 1, uhci_save, uhci_load, s); |
1145 | afcc3cdf | ths | } |