root / target-i386 / seg_helper.c @ 00f5e6f2
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| 1 | eaa728ee | bellard | /*
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| 2 | 10774999 | Blue Swirl | * x86 segmentation related helpers:
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| 3 | 10774999 | Blue Swirl | * TSS, interrupts, system calls, jumps and call/task gates, descriptors
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| 4 | eaa728ee | bellard | *
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| 5 | eaa728ee | bellard | * Copyright (c) 2003 Fabrice Bellard
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| 6 | eaa728ee | bellard | *
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| 7 | eaa728ee | bellard | * This library is free software; you can redistribute it and/or
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| 8 | eaa728ee | bellard | * modify it under the terms of the GNU Lesser General Public
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| 9 | eaa728ee | bellard | * License as published by the Free Software Foundation; either
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| 10 | eaa728ee | bellard | * version 2 of the License, or (at your option) any later version.
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| 11 | eaa728ee | bellard | *
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| 12 | eaa728ee | bellard | * This library is distributed in the hope that it will be useful,
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| 13 | eaa728ee | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 14 | eaa728ee | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 15 | eaa728ee | bellard | * Lesser General Public License for more details.
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| 16 | eaa728ee | bellard | *
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| 17 | eaa728ee | bellard | * You should have received a copy of the GNU Lesser General Public
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| 18 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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| 19 | eaa728ee | bellard | */
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| 20 | 83dae095 | Paolo Bonzini | |
| 21 | 3e457172 | Blue Swirl | #include "cpu.h" |
| 22 | 1de7afc9 | Paolo Bonzini | #include "qemu/log.h" |
| 23 | 3e457172 | Blue Swirl | #include "helper.h" |
| 24 | eaa728ee | bellard | |
| 25 | 3e457172 | Blue Swirl | //#define DEBUG_PCALL
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| 26 | d12d51d5 | aliguori | |
| 27 | 92fc4b58 | Blue Swirl | #if !defined(CONFIG_USER_ONLY)
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| 28 | 022c62cb | Paolo Bonzini | #include "exec/softmmu_exec.h" |
| 29 | 92fc4b58 | Blue Swirl | #endif /* !defined(CONFIG_USER_ONLY) */ |
| 30 | 92fc4b58 | Blue Swirl | |
| 31 | d12d51d5 | aliguori | #ifdef DEBUG_PCALL
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| 32 | 20054ef0 | Blue Swirl | # define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__) |
| 33 | 20054ef0 | Blue Swirl | # define LOG_PCALL_STATE(env) \
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| 34 | 6fd2a026 | Peter Maydell | log_cpu_state_mask(CPU_LOG_PCALL, (env), CPU_DUMP_CCOP) |
| 35 | d12d51d5 | aliguori | #else
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| 36 | 20054ef0 | Blue Swirl | # define LOG_PCALL(...) do { } while (0) |
| 37 | 20054ef0 | Blue Swirl | # define LOG_PCALL_STATE(env) do { } while (0) |
| 38 | d12d51d5 | aliguori | #endif
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| 39 | d12d51d5 | aliguori | |
| 40 | eaa728ee | bellard | /* return non zero if error */
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| 41 | 2999a0b2 | Blue Swirl | static inline int load_segment(CPUX86State *env, uint32_t *e1_ptr, |
| 42 | 2999a0b2 | Blue Swirl | uint32_t *e2_ptr, int selector)
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| 43 | eaa728ee | bellard | {
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| 44 | eaa728ee | bellard | SegmentCache *dt; |
| 45 | eaa728ee | bellard | int index;
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| 46 | eaa728ee | bellard | target_ulong ptr; |
| 47 | eaa728ee | bellard | |
| 48 | 20054ef0 | Blue Swirl | if (selector & 0x4) { |
| 49 | eaa728ee | bellard | dt = &env->ldt; |
| 50 | 20054ef0 | Blue Swirl | } else {
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| 51 | eaa728ee | bellard | dt = &env->gdt; |
| 52 | 20054ef0 | Blue Swirl | } |
| 53 | eaa728ee | bellard | index = selector & ~7;
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| 54 | 20054ef0 | Blue Swirl | if ((index + 7) > dt->limit) { |
| 55 | eaa728ee | bellard | return -1; |
| 56 | 20054ef0 | Blue Swirl | } |
| 57 | eaa728ee | bellard | ptr = dt->base + index; |
| 58 | 329e607d | Blue Swirl | *e1_ptr = cpu_ldl_kernel(env, ptr); |
| 59 | 329e607d | Blue Swirl | *e2_ptr = cpu_ldl_kernel(env, ptr + 4);
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| 60 | eaa728ee | bellard | return 0; |
| 61 | eaa728ee | bellard | } |
| 62 | eaa728ee | bellard | |
| 63 | eaa728ee | bellard | static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2) |
| 64 | eaa728ee | bellard | {
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| 65 | eaa728ee | bellard | unsigned int limit; |
| 66 | 20054ef0 | Blue Swirl | |
| 67 | eaa728ee | bellard | limit = (e1 & 0xffff) | (e2 & 0x000f0000); |
| 68 | 20054ef0 | Blue Swirl | if (e2 & DESC_G_MASK) {
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| 69 | eaa728ee | bellard | limit = (limit << 12) | 0xfff; |
| 70 | 20054ef0 | Blue Swirl | } |
| 71 | eaa728ee | bellard | return limit;
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| 72 | eaa728ee | bellard | } |
| 73 | eaa728ee | bellard | |
| 74 | eaa728ee | bellard | static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2) |
| 75 | eaa728ee | bellard | {
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| 76 | 20054ef0 | Blue Swirl | return (e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000); |
| 77 | eaa728ee | bellard | } |
| 78 | eaa728ee | bellard | |
| 79 | 20054ef0 | Blue Swirl | static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, |
| 80 | 20054ef0 | Blue Swirl | uint32_t e2) |
| 81 | eaa728ee | bellard | {
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| 82 | eaa728ee | bellard | sc->base = get_seg_base(e1, e2); |
| 83 | eaa728ee | bellard | sc->limit = get_seg_limit(e1, e2); |
| 84 | eaa728ee | bellard | sc->flags = e2; |
| 85 | eaa728ee | bellard | } |
| 86 | eaa728ee | bellard | |
| 87 | eaa728ee | bellard | /* init the segment cache in vm86 mode. */
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| 88 | 2999a0b2 | Blue Swirl | static inline void load_seg_vm(CPUX86State *env, int seg, int selector) |
| 89 | eaa728ee | bellard | {
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| 90 | eaa728ee | bellard | selector &= 0xffff;
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| 91 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, seg, selector, |
| 92 | eaa728ee | bellard | (selector << 4), 0xffff, 0); |
| 93 | eaa728ee | bellard | } |
| 94 | eaa728ee | bellard | |
| 95 | 2999a0b2 | Blue Swirl | static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr, |
| 96 | eaa728ee | bellard | uint32_t *esp_ptr, int dpl)
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| 97 | eaa728ee | bellard | {
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| 98 | eaa728ee | bellard | int type, index, shift;
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| 99 | eaa728ee | bellard | |
| 100 | eaa728ee | bellard | #if 0
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| 101 | eaa728ee | bellard | {
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| 102 | eaa728ee | bellard | int i;
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| 103 | eaa728ee | bellard | printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
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| 104 | 20054ef0 | Blue Swirl | for (i = 0; i < env->tr.limit; i++) {
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| 105 | eaa728ee | bellard | printf("%02x ", env->tr.base[i]);
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| 106 | 20054ef0 | Blue Swirl | if ((i & 7) == 7) {
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| 107 | 20054ef0 | Blue Swirl | printf("\n");
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| 108 | 20054ef0 | Blue Swirl | }
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| 109 | eaa728ee | bellard | }
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| 110 | eaa728ee | bellard | printf("\n");
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| 111 | eaa728ee | bellard | }
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| 112 | eaa728ee | bellard | #endif
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| 113 | eaa728ee | bellard | |
| 114 | 20054ef0 | Blue Swirl | if (!(env->tr.flags & DESC_P_MASK)) {
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| 115 | eaa728ee | bellard | cpu_abort(env, "invalid tss");
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| 116 | 20054ef0 | Blue Swirl | } |
| 117 | eaa728ee | bellard | type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
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| 118 | 20054ef0 | Blue Swirl | if ((type & 7) != 1) { |
| 119 | eaa728ee | bellard | cpu_abort(env, "invalid tss type");
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| 120 | 20054ef0 | Blue Swirl | } |
| 121 | eaa728ee | bellard | shift = type >> 3;
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| 122 | eaa728ee | bellard | index = (dpl * 4 + 2) << shift; |
| 123 | 20054ef0 | Blue Swirl | if (index + (4 << shift) - 1 > env->tr.limit) { |
| 124 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
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| 125 | 20054ef0 | Blue Swirl | } |
| 126 | eaa728ee | bellard | if (shift == 0) { |
| 127 | 329e607d | Blue Swirl | *esp_ptr = cpu_lduw_kernel(env, env->tr.base + index); |
| 128 | 329e607d | Blue Swirl | *ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 2);
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| 129 | eaa728ee | bellard | } else {
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| 130 | 329e607d | Blue Swirl | *esp_ptr = cpu_ldl_kernel(env, env->tr.base + index); |
| 131 | 329e607d | Blue Swirl | *ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 4);
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| 132 | eaa728ee | bellard | } |
| 133 | eaa728ee | bellard | } |
| 134 | eaa728ee | bellard | |
| 135 | eaa728ee | bellard | /* XXX: merge with load_seg() */
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| 136 | 2999a0b2 | Blue Swirl | static void tss_load_seg(CPUX86State *env, int seg_reg, int selector) |
| 137 | eaa728ee | bellard | {
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| 138 | eaa728ee | bellard | uint32_t e1, e2; |
| 139 | eaa728ee | bellard | int rpl, dpl, cpl;
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| 140 | eaa728ee | bellard | |
| 141 | eaa728ee | bellard | if ((selector & 0xfffc) != 0) { |
| 142 | 2999a0b2 | Blue Swirl | if (load_segment(env, &e1, &e2, selector) != 0) { |
| 143 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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| 144 | 20054ef0 | Blue Swirl | } |
| 145 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_S_MASK)) {
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| 146 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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| 147 | 20054ef0 | Blue Swirl | } |
| 148 | eaa728ee | bellard | rpl = selector & 3;
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| 149 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
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| 150 | eaa728ee | bellard | cpl = env->hflags & HF_CPL_MASK; |
| 151 | eaa728ee | bellard | if (seg_reg == R_CS) {
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| 152 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_CS_MASK)) {
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| 153 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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| 154 | 20054ef0 | Blue Swirl | } |
| 155 | 20054ef0 | Blue Swirl | /* XXX: is it correct? */
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| 156 | 20054ef0 | Blue Swirl | if (dpl != rpl) {
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| 157 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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| 158 | 20054ef0 | Blue Swirl | } |
| 159 | 20054ef0 | Blue Swirl | if ((e2 & DESC_C_MASK) && dpl > rpl) {
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| 160 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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| 161 | 20054ef0 | Blue Swirl | } |
| 162 | eaa728ee | bellard | } else if (seg_reg == R_SS) { |
| 163 | eaa728ee | bellard | /* SS must be writable data */
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| 164 | 20054ef0 | Blue Swirl | if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
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| 165 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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| 166 | 20054ef0 | Blue Swirl | } |
| 167 | 20054ef0 | Blue Swirl | if (dpl != cpl || dpl != rpl) {
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| 168 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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| 169 | 20054ef0 | Blue Swirl | } |
| 170 | eaa728ee | bellard | } else {
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| 171 | eaa728ee | bellard | /* not readable code */
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| 172 | 20054ef0 | Blue Swirl | if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK)) {
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| 173 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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| 174 | 20054ef0 | Blue Swirl | } |
| 175 | eaa728ee | bellard | /* if data or non conforming code, checks the rights */
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| 176 | eaa728ee | bellard | if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) { |
| 177 | 20054ef0 | Blue Swirl | if (dpl < cpl || dpl < rpl) {
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| 178 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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| 179 | 20054ef0 | Blue Swirl | } |
| 180 | eaa728ee | bellard | } |
| 181 | eaa728ee | bellard | } |
| 182 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
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| 183 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
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| 184 | 20054ef0 | Blue Swirl | } |
| 185 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, seg_reg, selector, |
| 186 | 20054ef0 | Blue Swirl | get_seg_base(e1, e2), |
| 187 | 20054ef0 | Blue Swirl | get_seg_limit(e1, e2), |
| 188 | 20054ef0 | Blue Swirl | e2); |
| 189 | eaa728ee | bellard | } else {
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| 190 | 20054ef0 | Blue Swirl | if (seg_reg == R_SS || seg_reg == R_CS) {
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| 191 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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| 192 | 20054ef0 | Blue Swirl | } |
| 193 | eaa728ee | bellard | } |
| 194 | eaa728ee | bellard | } |
| 195 | eaa728ee | bellard | |
| 196 | eaa728ee | bellard | #define SWITCH_TSS_JMP 0 |
| 197 | eaa728ee | bellard | #define SWITCH_TSS_IRET 1 |
| 198 | eaa728ee | bellard | #define SWITCH_TSS_CALL 2 |
| 199 | eaa728ee | bellard | |
| 200 | eaa728ee | bellard | /* XXX: restore CPU state in registers (PowerPC case) */
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| 201 | 2999a0b2 | Blue Swirl | static void switch_tss(CPUX86State *env, int tss_selector, |
| 202 | eaa728ee | bellard | uint32_t e1, uint32_t e2, int source,
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| 203 | eaa728ee | bellard | uint32_t next_eip) |
| 204 | eaa728ee | bellard | {
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| 205 | eaa728ee | bellard | int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
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| 206 | eaa728ee | bellard | target_ulong tss_base; |
| 207 | eaa728ee | bellard | uint32_t new_regs[8], new_segs[6]; |
| 208 | eaa728ee | bellard | uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap; |
| 209 | eaa728ee | bellard | uint32_t old_eflags, eflags_mask; |
| 210 | eaa728ee | bellard | SegmentCache *dt; |
| 211 | eaa728ee | bellard | int index;
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| 212 | eaa728ee | bellard | target_ulong ptr; |
| 213 | eaa728ee | bellard | |
| 214 | eaa728ee | bellard | type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
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| 215 | 20054ef0 | Blue Swirl | LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type,
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| 216 | 20054ef0 | Blue Swirl | source); |
| 217 | eaa728ee | bellard | |
| 218 | eaa728ee | bellard | /* if task gate, we read the TSS segment and we load it */
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| 219 | eaa728ee | bellard | if (type == 5) { |
| 220 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
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| 221 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
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| 222 | 20054ef0 | Blue Swirl | } |
| 223 | eaa728ee | bellard | tss_selector = e1 >> 16;
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| 224 | 20054ef0 | Blue Swirl | if (tss_selector & 4) { |
| 225 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
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| 226 | 20054ef0 | Blue Swirl | } |
| 227 | 2999a0b2 | Blue Swirl | if (load_segment(env, &e1, &e2, tss_selector) != 0) { |
| 228 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
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| 229 | 20054ef0 | Blue Swirl | } |
| 230 | 20054ef0 | Blue Swirl | if (e2 & DESC_S_MASK) {
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| 231 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
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| 232 | 20054ef0 | Blue Swirl | } |
| 233 | eaa728ee | bellard | type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
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| 234 | 20054ef0 | Blue Swirl | if ((type & 7) != 1) { |
| 235 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
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| 236 | 20054ef0 | Blue Swirl | } |
| 237 | eaa728ee | bellard | } |
| 238 | eaa728ee | bellard | |
| 239 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
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| 240 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
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| 241 | 20054ef0 | Blue Swirl | } |
| 242 | eaa728ee | bellard | |
| 243 | 20054ef0 | Blue Swirl | if (type & 8) { |
| 244 | eaa728ee | bellard | tss_limit_max = 103;
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| 245 | 20054ef0 | Blue Swirl | } else {
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| 246 | eaa728ee | bellard | tss_limit_max = 43;
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| 247 | 20054ef0 | Blue Swirl | } |
| 248 | eaa728ee | bellard | tss_limit = get_seg_limit(e1, e2); |
| 249 | eaa728ee | bellard | tss_base = get_seg_base(e1, e2); |
| 250 | eaa728ee | bellard | if ((tss_selector & 4) != 0 || |
| 251 | 20054ef0 | Blue Swirl | tss_limit < tss_limit_max) {
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| 252 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
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| 253 | 20054ef0 | Blue Swirl | } |
| 254 | eaa728ee | bellard | old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
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| 255 | 20054ef0 | Blue Swirl | if (old_type & 8) { |
| 256 | eaa728ee | bellard | old_tss_limit_max = 103;
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| 257 | 20054ef0 | Blue Swirl | } else {
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| 258 | eaa728ee | bellard | old_tss_limit_max = 43;
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| 259 | 20054ef0 | Blue Swirl | } |
| 260 | eaa728ee | bellard | |
| 261 | eaa728ee | bellard | /* read all the registers from the new TSS */
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| 262 | eaa728ee | bellard | if (type & 8) { |
| 263 | eaa728ee | bellard | /* 32 bit */
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| 264 | 329e607d | Blue Swirl | new_cr3 = cpu_ldl_kernel(env, tss_base + 0x1c);
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| 265 | 329e607d | Blue Swirl | new_eip = cpu_ldl_kernel(env, tss_base + 0x20);
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| 266 | 329e607d | Blue Swirl | new_eflags = cpu_ldl_kernel(env, tss_base + 0x24);
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| 267 | 20054ef0 | Blue Swirl | for (i = 0; i < 8; i++) { |
| 268 | 329e607d | Blue Swirl | new_regs[i] = cpu_ldl_kernel(env, tss_base + (0x28 + i * 4)); |
| 269 | 20054ef0 | Blue Swirl | } |
| 270 | 20054ef0 | Blue Swirl | for (i = 0; i < 6; i++) { |
| 271 | 329e607d | Blue Swirl | new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x48 + i * 4)); |
| 272 | 20054ef0 | Blue Swirl | } |
| 273 | 329e607d | Blue Swirl | new_ldt = cpu_lduw_kernel(env, tss_base + 0x60);
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| 274 | 329e607d | Blue Swirl | new_trap = cpu_ldl_kernel(env, tss_base + 0x64);
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| 275 | eaa728ee | bellard | } else {
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| 276 | eaa728ee | bellard | /* 16 bit */
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| 277 | eaa728ee | bellard | new_cr3 = 0;
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| 278 | 329e607d | Blue Swirl | new_eip = cpu_lduw_kernel(env, tss_base + 0x0e);
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| 279 | 329e607d | Blue Swirl | new_eflags = cpu_lduw_kernel(env, tss_base + 0x10);
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| 280 | 20054ef0 | Blue Swirl | for (i = 0; i < 8; i++) { |
| 281 | 329e607d | Blue Swirl | new_regs[i] = cpu_lduw_kernel(env, tss_base + (0x12 + i * 2)) | |
| 282 | 329e607d | Blue Swirl | 0xffff0000;
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| 283 | 20054ef0 | Blue Swirl | } |
| 284 | 20054ef0 | Blue Swirl | for (i = 0; i < 4; i++) { |
| 285 | 329e607d | Blue Swirl | new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x22 + i * 4)); |
| 286 | 20054ef0 | Blue Swirl | } |
| 287 | 329e607d | Blue Swirl | new_ldt = cpu_lduw_kernel(env, tss_base + 0x2a);
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| 288 | eaa728ee | bellard | new_segs[R_FS] = 0;
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| 289 | eaa728ee | bellard | new_segs[R_GS] = 0;
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| 290 | eaa728ee | bellard | new_trap = 0;
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| 291 | eaa728ee | bellard | } |
| 292 | 4581cbcd | Blue Swirl | /* XXX: avoid a compiler warning, see
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| 293 | 4581cbcd | Blue Swirl | http://support.amd.com/us/Processor_TechDocs/24593.pdf
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| 294 | 4581cbcd | Blue Swirl | chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */
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| 295 | 4581cbcd | Blue Swirl | (void)new_trap;
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| 296 | eaa728ee | bellard | |
| 297 | eaa728ee | bellard | /* NOTE: we must avoid memory exceptions during the task switch,
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| 298 | eaa728ee | bellard | so we make dummy accesses before */
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| 299 | eaa728ee | bellard | /* XXX: it can still fail in some cases, so a bigger hack is
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| 300 | eaa728ee | bellard | necessary to valid the TLB after having done the accesses */
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| 301 | eaa728ee | bellard | |
| 302 | 329e607d | Blue Swirl | v1 = cpu_ldub_kernel(env, env->tr.base); |
| 303 | 329e607d | Blue Swirl | v2 = cpu_ldub_kernel(env, env->tr.base + old_tss_limit_max); |
| 304 | 329e607d | Blue Swirl | cpu_stb_kernel(env, env->tr.base, v1); |
| 305 | 329e607d | Blue Swirl | cpu_stb_kernel(env, env->tr.base + old_tss_limit_max, v2); |
| 306 | eaa728ee | bellard | |
| 307 | eaa728ee | bellard | /* clear busy bit (it is restartable) */
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| 308 | eaa728ee | bellard | if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
|
| 309 | eaa728ee | bellard | target_ulong ptr; |
| 310 | eaa728ee | bellard | uint32_t e2; |
| 311 | 20054ef0 | Blue Swirl | |
| 312 | eaa728ee | bellard | ptr = env->gdt.base + (env->tr.selector & ~7);
|
| 313 | 329e607d | Blue Swirl | e2 = cpu_ldl_kernel(env, ptr + 4);
|
| 314 | eaa728ee | bellard | e2 &= ~DESC_TSS_BUSY_MASK; |
| 315 | 329e607d | Blue Swirl | cpu_stl_kernel(env, ptr + 4, e2);
|
| 316 | eaa728ee | bellard | } |
| 317 | 997ff0d9 | Blue Swirl | old_eflags = cpu_compute_eflags(env); |
| 318 | 20054ef0 | Blue Swirl | if (source == SWITCH_TSS_IRET) {
|
| 319 | eaa728ee | bellard | old_eflags &= ~NT_MASK; |
| 320 | 20054ef0 | Blue Swirl | } |
| 321 | eaa728ee | bellard | |
| 322 | eaa728ee | bellard | /* save the current state in the old TSS */
|
| 323 | eaa728ee | bellard | if (type & 8) { |
| 324 | eaa728ee | bellard | /* 32 bit */
|
| 325 | 329e607d | Blue Swirl | cpu_stl_kernel(env, env->tr.base + 0x20, next_eip);
|
| 326 | 329e607d | Blue Swirl | cpu_stl_kernel(env, env->tr.base + 0x24, old_eflags);
|
| 327 | 4b34e3ad | liguang | cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX]); |
| 328 | a4165610 | liguang | cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]); |
| 329 | 00f5e6f2 | liguang | cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX]); |
| 330 | 70b51365 | liguang | cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]); |
| 331 | 329e607d | Blue Swirl | cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), ESP); |
| 332 | 329e607d | Blue Swirl | cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), EBP); |
| 333 | 329e607d | Blue Swirl | cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), ESI); |
| 334 | 329e607d | Blue Swirl | cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), EDI); |
| 335 | 20054ef0 | Blue Swirl | for (i = 0; i < 6; i++) { |
| 336 | 329e607d | Blue Swirl | cpu_stw_kernel(env, env->tr.base + (0x48 + i * 4), |
| 337 | 329e607d | Blue Swirl | env->segs[i].selector); |
| 338 | 20054ef0 | Blue Swirl | } |
| 339 | eaa728ee | bellard | } else {
|
| 340 | eaa728ee | bellard | /* 16 bit */
|
| 341 | 329e607d | Blue Swirl | cpu_stw_kernel(env, env->tr.base + 0x0e, next_eip);
|
| 342 | 329e607d | Blue Swirl | cpu_stw_kernel(env, env->tr.base + 0x10, old_eflags);
|
| 343 | 4b34e3ad | liguang | cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX]); |
| 344 | a4165610 | liguang | cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]); |
| 345 | 00f5e6f2 | liguang | cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX]); |
| 346 | 70b51365 | liguang | cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]); |
| 347 | 329e607d | Blue Swirl | cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), ESP); |
| 348 | 329e607d | Blue Swirl | cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), EBP); |
| 349 | 329e607d | Blue Swirl | cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), ESI); |
| 350 | 329e607d | Blue Swirl | cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), EDI); |
| 351 | 20054ef0 | Blue Swirl | for (i = 0; i < 4; i++) { |
| 352 | 329e607d | Blue Swirl | cpu_stw_kernel(env, env->tr.base + (0x22 + i * 4), |
| 353 | 329e607d | Blue Swirl | env->segs[i].selector); |
| 354 | 20054ef0 | Blue Swirl | } |
| 355 | eaa728ee | bellard | } |
| 356 | eaa728ee | bellard | |
| 357 | eaa728ee | bellard | /* now if an exception occurs, it will occurs in the next task
|
| 358 | eaa728ee | bellard | context */
|
| 359 | eaa728ee | bellard | |
| 360 | eaa728ee | bellard | if (source == SWITCH_TSS_CALL) {
|
| 361 | 329e607d | Blue Swirl | cpu_stw_kernel(env, tss_base, env->tr.selector); |
| 362 | eaa728ee | bellard | new_eflags |= NT_MASK; |
| 363 | eaa728ee | bellard | } |
| 364 | eaa728ee | bellard | |
| 365 | eaa728ee | bellard | /* set busy bit */
|
| 366 | eaa728ee | bellard | if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
|
| 367 | eaa728ee | bellard | target_ulong ptr; |
| 368 | eaa728ee | bellard | uint32_t e2; |
| 369 | 20054ef0 | Blue Swirl | |
| 370 | eaa728ee | bellard | ptr = env->gdt.base + (tss_selector & ~7);
|
| 371 | 329e607d | Blue Swirl | e2 = cpu_ldl_kernel(env, ptr + 4);
|
| 372 | eaa728ee | bellard | e2 |= DESC_TSS_BUSY_MASK; |
| 373 | 329e607d | Blue Swirl | cpu_stl_kernel(env, ptr + 4, e2);
|
| 374 | eaa728ee | bellard | } |
| 375 | eaa728ee | bellard | |
| 376 | eaa728ee | bellard | /* set the new CPU state */
|
| 377 | eaa728ee | bellard | /* from this point, any exception which occurs can give problems */
|
| 378 | eaa728ee | bellard | env->cr[0] |= CR0_TS_MASK;
|
| 379 | eaa728ee | bellard | env->hflags |= HF_TS_MASK; |
| 380 | eaa728ee | bellard | env->tr.selector = tss_selector; |
| 381 | eaa728ee | bellard | env->tr.base = tss_base; |
| 382 | eaa728ee | bellard | env->tr.limit = tss_limit; |
| 383 | eaa728ee | bellard | env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK; |
| 384 | eaa728ee | bellard | |
| 385 | eaa728ee | bellard | if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) { |
| 386 | eaa728ee | bellard | cpu_x86_update_cr3(env, new_cr3); |
| 387 | eaa728ee | bellard | } |
| 388 | eaa728ee | bellard | |
| 389 | eaa728ee | bellard | /* load all registers without an exception, then reload them with
|
| 390 | eaa728ee | bellard | possible exception */
|
| 391 | eaa728ee | bellard | env->eip = new_eip; |
| 392 | eaa728ee | bellard | eflags_mask = TF_MASK | AC_MASK | ID_MASK | |
| 393 | eaa728ee | bellard | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK; |
| 394 | 20054ef0 | Blue Swirl | if (!(type & 8)) { |
| 395 | eaa728ee | bellard | eflags_mask &= 0xffff;
|
| 396 | 20054ef0 | Blue Swirl | } |
| 397 | 997ff0d9 | Blue Swirl | cpu_load_eflags(env, new_eflags, eflags_mask); |
| 398 | 20054ef0 | Blue Swirl | /* XXX: what to do in 16 bit case? */
|
| 399 | 4b34e3ad | liguang | env->regs[R_EAX] = new_regs[0];
|
| 400 | a4165610 | liguang | env->regs[R_ECX] = new_regs[1];
|
| 401 | 00f5e6f2 | liguang | env->regs[R_EDX] = new_regs[2];
|
| 402 | 70b51365 | liguang | env->regs[R_EBX] = new_regs[3];
|
| 403 | eaa728ee | bellard | ESP = new_regs[4];
|
| 404 | eaa728ee | bellard | EBP = new_regs[5];
|
| 405 | eaa728ee | bellard | ESI = new_regs[6];
|
| 406 | eaa728ee | bellard | EDI = new_regs[7];
|
| 407 | eaa728ee | bellard | if (new_eflags & VM_MASK) {
|
| 408 | 20054ef0 | Blue Swirl | for (i = 0; i < 6; i++) { |
| 409 | 2999a0b2 | Blue Swirl | load_seg_vm(env, i, new_segs[i]); |
| 410 | 20054ef0 | Blue Swirl | } |
| 411 | eaa728ee | bellard | /* in vm86, CPL is always 3 */
|
| 412 | eaa728ee | bellard | cpu_x86_set_cpl(env, 3);
|
| 413 | eaa728ee | bellard | } else {
|
| 414 | eaa728ee | bellard | /* CPL is set the RPL of CS */
|
| 415 | eaa728ee | bellard | cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
|
| 416 | eaa728ee | bellard | /* first just selectors as the rest may trigger exceptions */
|
| 417 | 20054ef0 | Blue Swirl | for (i = 0; i < 6; i++) { |
| 418 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0); |
| 419 | 20054ef0 | Blue Swirl | } |
| 420 | eaa728ee | bellard | } |
| 421 | eaa728ee | bellard | |
| 422 | eaa728ee | bellard | env->ldt.selector = new_ldt & ~4;
|
| 423 | eaa728ee | bellard | env->ldt.base = 0;
|
| 424 | eaa728ee | bellard | env->ldt.limit = 0;
|
| 425 | eaa728ee | bellard | env->ldt.flags = 0;
|
| 426 | eaa728ee | bellard | |
| 427 | eaa728ee | bellard | /* load the LDT */
|
| 428 | 20054ef0 | Blue Swirl | if (new_ldt & 4) { |
| 429 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
|
| 430 | 20054ef0 | Blue Swirl | } |
| 431 | eaa728ee | bellard | |
| 432 | eaa728ee | bellard | if ((new_ldt & 0xfffc) != 0) { |
| 433 | eaa728ee | bellard | dt = &env->gdt; |
| 434 | eaa728ee | bellard | index = new_ldt & ~7;
|
| 435 | 20054ef0 | Blue Swirl | if ((index + 7) > dt->limit) { |
| 436 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
|
| 437 | 20054ef0 | Blue Swirl | } |
| 438 | eaa728ee | bellard | ptr = dt->base + index; |
| 439 | 329e607d | Blue Swirl | e1 = cpu_ldl_kernel(env, ptr); |
| 440 | 329e607d | Blue Swirl | e2 = cpu_ldl_kernel(env, ptr + 4);
|
| 441 | 20054ef0 | Blue Swirl | if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) { |
| 442 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
|
| 443 | 20054ef0 | Blue Swirl | } |
| 444 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
|
| 445 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
|
| 446 | 20054ef0 | Blue Swirl | } |
| 447 | eaa728ee | bellard | load_seg_cache_raw_dt(&env->ldt, e1, e2); |
| 448 | eaa728ee | bellard | } |
| 449 | eaa728ee | bellard | |
| 450 | eaa728ee | bellard | /* load the segments */
|
| 451 | eaa728ee | bellard | if (!(new_eflags & VM_MASK)) {
|
| 452 | 2999a0b2 | Blue Swirl | tss_load_seg(env, R_CS, new_segs[R_CS]); |
| 453 | 2999a0b2 | Blue Swirl | tss_load_seg(env, R_SS, new_segs[R_SS]); |
| 454 | 2999a0b2 | Blue Swirl | tss_load_seg(env, R_ES, new_segs[R_ES]); |
| 455 | 2999a0b2 | Blue Swirl | tss_load_seg(env, R_DS, new_segs[R_DS]); |
| 456 | 2999a0b2 | Blue Swirl | tss_load_seg(env, R_FS, new_segs[R_FS]); |
| 457 | 2999a0b2 | Blue Swirl | tss_load_seg(env, R_GS, new_segs[R_GS]); |
| 458 | eaa728ee | bellard | } |
| 459 | eaa728ee | bellard | |
| 460 | eaa728ee | bellard | /* check that EIP is in the CS segment limits */
|
| 461 | eaa728ee | bellard | if (new_eip > env->segs[R_CS].limit) {
|
| 462 | 20054ef0 | Blue Swirl | /* XXX: different exception if CALL? */
|
| 463 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, 0);
|
| 464 | eaa728ee | bellard | } |
| 465 | 01df040b | aliguori | |
| 466 | 01df040b | aliguori | #ifndef CONFIG_USER_ONLY
|
| 467 | 01df040b | aliguori | /* reset local breakpoints */
|
| 468 | 428065ce | liguang | if (env->dr[7] & DR7_LOCAL_BP_MASK) { |
| 469 | 428065ce | liguang | for (i = 0; i < DR7_MAX_BP; i++) { |
| 470 | 5902564a | liguang | if (hw_local_breakpoint_enabled(env->dr[7], i) && |
| 471 | 5902564a | liguang | !hw_global_breakpoint_enabled(env->dr[7], i)) {
|
| 472 | 01df040b | aliguori | hw_breakpoint_remove(env, i); |
| 473 | 20054ef0 | Blue Swirl | } |
| 474 | 01df040b | aliguori | } |
| 475 | 428065ce | liguang | env->dr[7] &= ~DR7_LOCAL_BP_MASK;
|
| 476 | 01df040b | aliguori | } |
| 477 | 01df040b | aliguori | #endif
|
| 478 | eaa728ee | bellard | } |
| 479 | eaa728ee | bellard | |
| 480 | eaa728ee | bellard | static inline unsigned int get_sp_mask(unsigned int e2) |
| 481 | eaa728ee | bellard | {
|
| 482 | 20054ef0 | Blue Swirl | if (e2 & DESC_B_MASK) {
|
| 483 | eaa728ee | bellard | return 0xffffffff; |
| 484 | 20054ef0 | Blue Swirl | } else {
|
| 485 | eaa728ee | bellard | return 0xffff; |
| 486 | 20054ef0 | Blue Swirl | } |
| 487 | eaa728ee | bellard | } |
| 488 | eaa728ee | bellard | |
| 489 | 20054ef0 | Blue Swirl | static int exception_has_error_code(int intno) |
| 490 | 2ed51f5b | aliguori | {
|
| 491 | 20054ef0 | Blue Swirl | switch (intno) {
|
| 492 | 20054ef0 | Blue Swirl | case 8: |
| 493 | 20054ef0 | Blue Swirl | case 10: |
| 494 | 20054ef0 | Blue Swirl | case 11: |
| 495 | 20054ef0 | Blue Swirl | case 12: |
| 496 | 20054ef0 | Blue Swirl | case 13: |
| 497 | 20054ef0 | Blue Swirl | case 14: |
| 498 | 20054ef0 | Blue Swirl | case 17: |
| 499 | 20054ef0 | Blue Swirl | return 1; |
| 500 | 20054ef0 | Blue Swirl | } |
| 501 | 20054ef0 | Blue Swirl | return 0; |
| 502 | 2ed51f5b | aliguori | } |
| 503 | 2ed51f5b | aliguori | |
| 504 | eaa728ee | bellard | #ifdef TARGET_X86_64
|
| 505 | 20054ef0 | Blue Swirl | #define SET_ESP(val, sp_mask) \
|
| 506 | 20054ef0 | Blue Swirl | do { \
|
| 507 | 20054ef0 | Blue Swirl | if ((sp_mask) == 0xffff) { \ |
| 508 | 20054ef0 | Blue Swirl | ESP = (ESP & ~0xffff) | ((val) & 0xffff); \ |
| 509 | 20054ef0 | Blue Swirl | } else if ((sp_mask) == 0xffffffffLL) { \ |
| 510 | 20054ef0 | Blue Swirl | ESP = (uint32_t)(val); \ |
| 511 | 20054ef0 | Blue Swirl | } else { \
|
| 512 | 20054ef0 | Blue Swirl | ESP = (val); \ |
| 513 | 20054ef0 | Blue Swirl | } \ |
| 514 | 20054ef0 | Blue Swirl | } while (0) |
| 515 | eaa728ee | bellard | #else
|
| 516 | 20054ef0 | Blue Swirl | #define SET_ESP(val, sp_mask) \
|
| 517 | 20054ef0 | Blue Swirl | do { \
|
| 518 | 20054ef0 | Blue Swirl | ESP = (ESP & ~(sp_mask)) | ((val) & (sp_mask)); \ |
| 519 | 20054ef0 | Blue Swirl | } while (0) |
| 520 | eaa728ee | bellard | #endif
|
| 521 | eaa728ee | bellard | |
| 522 | c0a04f0e | aliguori | /* in 64-bit machines, this can overflow. So this segment addition macro
|
| 523 | c0a04f0e | aliguori | * can be used to trim the value to 32-bit whenever needed */
|
| 524 | c0a04f0e | aliguori | #define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask))))
|
| 525 | c0a04f0e | aliguori | |
| 526 | eaa728ee | bellard | /* XXX: add a is_user flag to have proper security support */
|
| 527 | 329e607d | Blue Swirl | #define PUSHW(ssp, sp, sp_mask, val) \
|
| 528 | 329e607d | Blue Swirl | { \
|
| 529 | 329e607d | Blue Swirl | sp -= 2; \
|
| 530 | 329e607d | Blue Swirl | cpu_stw_kernel(env, (ssp) + (sp & (sp_mask)), (val)); \ |
| 531 | 20054ef0 | Blue Swirl | } |
| 532 | eaa728ee | bellard | |
| 533 | 20054ef0 | Blue Swirl | #define PUSHL(ssp, sp, sp_mask, val) \
|
| 534 | 20054ef0 | Blue Swirl | { \
|
| 535 | 20054ef0 | Blue Swirl | sp -= 4; \
|
| 536 | 329e607d | Blue Swirl | cpu_stl_kernel(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val)); \ |
| 537 | 20054ef0 | Blue Swirl | } |
| 538 | eaa728ee | bellard | |
| 539 | 329e607d | Blue Swirl | #define POPW(ssp, sp, sp_mask, val) \
|
| 540 | 329e607d | Blue Swirl | { \
|
| 541 | 329e607d | Blue Swirl | val = cpu_lduw_kernel(env, (ssp) + (sp & (sp_mask))); \ |
| 542 | 329e607d | Blue Swirl | sp += 2; \
|
| 543 | 20054ef0 | Blue Swirl | } |
| 544 | eaa728ee | bellard | |
| 545 | 329e607d | Blue Swirl | #define POPL(ssp, sp, sp_mask, val) \
|
| 546 | 329e607d | Blue Swirl | { \
|
| 547 | 329e607d | Blue Swirl | val = (uint32_t)cpu_ldl_kernel(env, SEG_ADDL(ssp, sp, sp_mask)); \ |
| 548 | 329e607d | Blue Swirl | sp += 4; \
|
| 549 | 20054ef0 | Blue Swirl | } |
| 550 | eaa728ee | bellard | |
| 551 | eaa728ee | bellard | /* protected mode interrupt */
|
| 552 | 2999a0b2 | Blue Swirl | static void do_interrupt_protected(CPUX86State *env, int intno, int is_int, |
| 553 | 2999a0b2 | Blue Swirl | int error_code, unsigned int next_eip, |
| 554 | 2999a0b2 | Blue Swirl | int is_hw)
|
| 555 | eaa728ee | bellard | {
|
| 556 | eaa728ee | bellard | SegmentCache *dt; |
| 557 | eaa728ee | bellard | target_ulong ptr, ssp; |
| 558 | eaa728ee | bellard | int type, dpl, selector, ss_dpl, cpl;
|
| 559 | eaa728ee | bellard | int has_error_code, new_stack, shift;
|
| 560 | 1c918eba | blueswir1 | uint32_t e1, e2, offset, ss = 0, esp, ss_e1 = 0, ss_e2 = 0; |
| 561 | eaa728ee | bellard | uint32_t old_eip, sp_mask; |
| 562 | eaa728ee | bellard | |
| 563 | eaa728ee | bellard | has_error_code = 0;
|
| 564 | 20054ef0 | Blue Swirl | if (!is_int && !is_hw) {
|
| 565 | 20054ef0 | Blue Swirl | has_error_code = exception_has_error_code(intno); |
| 566 | 20054ef0 | Blue Swirl | } |
| 567 | 20054ef0 | Blue Swirl | if (is_int) {
|
| 568 | eaa728ee | bellard | old_eip = next_eip; |
| 569 | 20054ef0 | Blue Swirl | } else {
|
| 570 | eaa728ee | bellard | old_eip = env->eip; |
| 571 | 20054ef0 | Blue Swirl | } |
| 572 | eaa728ee | bellard | |
| 573 | eaa728ee | bellard | dt = &env->idt; |
| 574 | 20054ef0 | Blue Swirl | if (intno * 8 + 7 > dt->limit) { |
| 575 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
| 576 | 20054ef0 | Blue Swirl | } |
| 577 | eaa728ee | bellard | ptr = dt->base + intno * 8;
|
| 578 | 329e607d | Blue Swirl | e1 = cpu_ldl_kernel(env, ptr); |
| 579 | 329e607d | Blue Swirl | e2 = cpu_ldl_kernel(env, ptr + 4);
|
| 580 | eaa728ee | bellard | /* check gate type */
|
| 581 | eaa728ee | bellard | type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
|
| 582 | 20054ef0 | Blue Swirl | switch (type) {
|
| 583 | eaa728ee | bellard | case 5: /* task gate */ |
| 584 | eaa728ee | bellard | /* must do that check here to return the correct error code */
|
| 585 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
|
| 586 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2); |
| 587 | 20054ef0 | Blue Swirl | } |
| 588 | 2999a0b2 | Blue Swirl | switch_tss(env, intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
|
| 589 | eaa728ee | bellard | if (has_error_code) {
|
| 590 | eaa728ee | bellard | int type;
|
| 591 | eaa728ee | bellard | uint32_t mask; |
| 592 | 20054ef0 | Blue Swirl | |
| 593 | eaa728ee | bellard | /* push the error code */
|
| 594 | eaa728ee | bellard | type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
|
| 595 | eaa728ee | bellard | shift = type >> 3;
|
| 596 | 20054ef0 | Blue Swirl | if (env->segs[R_SS].flags & DESC_B_MASK) {
|
| 597 | eaa728ee | bellard | mask = 0xffffffff;
|
| 598 | 20054ef0 | Blue Swirl | } else {
|
| 599 | eaa728ee | bellard | mask = 0xffff;
|
| 600 | 20054ef0 | Blue Swirl | } |
| 601 | eaa728ee | bellard | esp = (ESP - (2 << shift)) & mask;
|
| 602 | eaa728ee | bellard | ssp = env->segs[R_SS].base + esp; |
| 603 | 20054ef0 | Blue Swirl | if (shift) {
|
| 604 | 329e607d | Blue Swirl | cpu_stl_kernel(env, ssp, error_code); |
| 605 | 20054ef0 | Blue Swirl | } else {
|
| 606 | 329e607d | Blue Swirl | cpu_stw_kernel(env, ssp, error_code); |
| 607 | 20054ef0 | Blue Swirl | } |
| 608 | eaa728ee | bellard | SET_ESP(esp, mask); |
| 609 | eaa728ee | bellard | } |
| 610 | eaa728ee | bellard | return;
|
| 611 | eaa728ee | bellard | case 6: /* 286 interrupt gate */ |
| 612 | eaa728ee | bellard | case 7: /* 286 trap gate */ |
| 613 | eaa728ee | bellard | case 14: /* 386 interrupt gate */ |
| 614 | eaa728ee | bellard | case 15: /* 386 trap gate */ |
| 615 | eaa728ee | bellard | break;
|
| 616 | eaa728ee | bellard | default:
|
| 617 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
| 618 | eaa728ee | bellard | break;
|
| 619 | eaa728ee | bellard | } |
| 620 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 621 | eaa728ee | bellard | cpl = env->hflags & HF_CPL_MASK; |
| 622 | 1235fc06 | ths | /* check privilege if software int */
|
| 623 | 20054ef0 | Blue Swirl | if (is_int && dpl < cpl) {
|
| 624 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
| 625 | 20054ef0 | Blue Swirl | } |
| 626 | eaa728ee | bellard | /* check valid bit */
|
| 627 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
|
| 628 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2); |
| 629 | 20054ef0 | Blue Swirl | } |
| 630 | eaa728ee | bellard | selector = e1 >> 16;
|
| 631 | eaa728ee | bellard | offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff); |
| 632 | 20054ef0 | Blue Swirl | if ((selector & 0xfffc) == 0) { |
| 633 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, 0);
|
| 634 | 20054ef0 | Blue Swirl | } |
| 635 | 2999a0b2 | Blue Swirl | if (load_segment(env, &e1, &e2, selector) != 0) { |
| 636 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 637 | 20054ef0 | Blue Swirl | } |
| 638 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
|
| 639 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 640 | 20054ef0 | Blue Swirl | } |
| 641 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 642 | 20054ef0 | Blue Swirl | if (dpl > cpl) {
|
| 643 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 644 | 20054ef0 | Blue Swirl | } |
| 645 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
|
| 646 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
| 647 | 20054ef0 | Blue Swirl | } |
| 648 | eaa728ee | bellard | if (!(e2 & DESC_C_MASK) && dpl < cpl) {
|
| 649 | eaa728ee | bellard | /* to inner privilege */
|
| 650 | 2999a0b2 | Blue Swirl | get_ss_esp_from_tss(env, &ss, &esp, dpl); |
| 651 | 20054ef0 | Blue Swirl | if ((ss & 0xfffc) == 0) { |
| 652 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
| 653 | 20054ef0 | Blue Swirl | } |
| 654 | 20054ef0 | Blue Swirl | if ((ss & 3) != dpl) { |
| 655 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
| 656 | 20054ef0 | Blue Swirl | } |
| 657 | 2999a0b2 | Blue Swirl | if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) { |
| 658 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
| 659 | 20054ef0 | Blue Swirl | } |
| 660 | eaa728ee | bellard | ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
|
| 661 | 20054ef0 | Blue Swirl | if (ss_dpl != dpl) {
|
| 662 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
| 663 | 20054ef0 | Blue Swirl | } |
| 664 | eaa728ee | bellard | if (!(ss_e2 & DESC_S_MASK) ||
|
| 665 | eaa728ee | bellard | (ss_e2 & DESC_CS_MASK) || |
| 666 | 20054ef0 | Blue Swirl | !(ss_e2 & DESC_W_MASK)) {
|
| 667 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
| 668 | 20054ef0 | Blue Swirl | } |
| 669 | 20054ef0 | Blue Swirl | if (!(ss_e2 & DESC_P_MASK)) {
|
| 670 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
| 671 | 20054ef0 | Blue Swirl | } |
| 672 | eaa728ee | bellard | new_stack = 1;
|
| 673 | eaa728ee | bellard | sp_mask = get_sp_mask(ss_e2); |
| 674 | eaa728ee | bellard | ssp = get_seg_base(ss_e1, ss_e2); |
| 675 | eaa728ee | bellard | } else if ((e2 & DESC_C_MASK) || dpl == cpl) { |
| 676 | eaa728ee | bellard | /* to same privilege */
|
| 677 | 20054ef0 | Blue Swirl | if (env->eflags & VM_MASK) {
|
| 678 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 679 | 20054ef0 | Blue Swirl | } |
| 680 | eaa728ee | bellard | new_stack = 0;
|
| 681 | eaa728ee | bellard | sp_mask = get_sp_mask(env->segs[R_SS].flags); |
| 682 | eaa728ee | bellard | ssp = env->segs[R_SS].base; |
| 683 | eaa728ee | bellard | esp = ESP; |
| 684 | eaa728ee | bellard | dpl = cpl; |
| 685 | eaa728ee | bellard | } else {
|
| 686 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 687 | eaa728ee | bellard | new_stack = 0; /* avoid warning */ |
| 688 | eaa728ee | bellard | sp_mask = 0; /* avoid warning */ |
| 689 | eaa728ee | bellard | ssp = 0; /* avoid warning */ |
| 690 | eaa728ee | bellard | esp = 0; /* avoid warning */ |
| 691 | eaa728ee | bellard | } |
| 692 | eaa728ee | bellard | |
| 693 | eaa728ee | bellard | shift = type >> 3;
|
| 694 | eaa728ee | bellard | |
| 695 | eaa728ee | bellard | #if 0
|
| 696 | eaa728ee | bellard | /* XXX: check that enough room is available */
|
| 697 | eaa728ee | bellard | push_size = 6 + (new_stack << 2) + (has_error_code << 1);
|
| 698 | 20054ef0 | Blue Swirl | if (env->eflags & VM_MASK) {
|
| 699 | eaa728ee | bellard | push_size += 8;
|
| 700 | 20054ef0 | Blue Swirl | }
|
| 701 | eaa728ee | bellard | push_size <<= shift;
|
| 702 | eaa728ee | bellard | #endif
|
| 703 | eaa728ee | bellard | if (shift == 1) { |
| 704 | eaa728ee | bellard | if (new_stack) {
|
| 705 | eaa728ee | bellard | if (env->eflags & VM_MASK) {
|
| 706 | eaa728ee | bellard | PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector); |
| 707 | eaa728ee | bellard | PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector); |
| 708 | eaa728ee | bellard | PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector); |
| 709 | eaa728ee | bellard | PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector); |
| 710 | eaa728ee | bellard | } |
| 711 | eaa728ee | bellard | PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector); |
| 712 | eaa728ee | bellard | PUSHL(ssp, esp, sp_mask, ESP); |
| 713 | eaa728ee | bellard | } |
| 714 | 997ff0d9 | Blue Swirl | PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env)); |
| 715 | eaa728ee | bellard | PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector); |
| 716 | eaa728ee | bellard | PUSHL(ssp, esp, sp_mask, old_eip); |
| 717 | eaa728ee | bellard | if (has_error_code) {
|
| 718 | eaa728ee | bellard | PUSHL(ssp, esp, sp_mask, error_code); |
| 719 | eaa728ee | bellard | } |
| 720 | eaa728ee | bellard | } else {
|
| 721 | eaa728ee | bellard | if (new_stack) {
|
| 722 | eaa728ee | bellard | if (env->eflags & VM_MASK) {
|
| 723 | eaa728ee | bellard | PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector); |
| 724 | eaa728ee | bellard | PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector); |
| 725 | eaa728ee | bellard | PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector); |
| 726 | eaa728ee | bellard | PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector); |
| 727 | eaa728ee | bellard | } |
| 728 | eaa728ee | bellard | PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector); |
| 729 | eaa728ee | bellard | PUSHW(ssp, esp, sp_mask, ESP); |
| 730 | eaa728ee | bellard | } |
| 731 | 997ff0d9 | Blue Swirl | PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env)); |
| 732 | eaa728ee | bellard | PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector); |
| 733 | eaa728ee | bellard | PUSHW(ssp, esp, sp_mask, old_eip); |
| 734 | eaa728ee | bellard | if (has_error_code) {
|
| 735 | eaa728ee | bellard | PUSHW(ssp, esp, sp_mask, error_code); |
| 736 | eaa728ee | bellard | } |
| 737 | eaa728ee | bellard | } |
| 738 | eaa728ee | bellard | |
| 739 | eaa728ee | bellard | if (new_stack) {
|
| 740 | eaa728ee | bellard | if (env->eflags & VM_MASK) {
|
| 741 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0); |
| 742 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0); |
| 743 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0); |
| 744 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0); |
| 745 | eaa728ee | bellard | } |
| 746 | eaa728ee | bellard | ss = (ss & ~3) | dpl;
|
| 747 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_SS, ss, |
| 748 | eaa728ee | bellard | ssp, get_seg_limit(ss_e1, ss_e2), ss_e2); |
| 749 | eaa728ee | bellard | } |
| 750 | eaa728ee | bellard | SET_ESP(esp, sp_mask); |
| 751 | eaa728ee | bellard | |
| 752 | eaa728ee | bellard | selector = (selector & ~3) | dpl;
|
| 753 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_CS, selector, |
| 754 | eaa728ee | bellard | get_seg_base(e1, e2), |
| 755 | eaa728ee | bellard | get_seg_limit(e1, e2), |
| 756 | eaa728ee | bellard | e2); |
| 757 | eaa728ee | bellard | cpu_x86_set_cpl(env, dpl); |
| 758 | eaa728ee | bellard | env->eip = offset; |
| 759 | eaa728ee | bellard | |
| 760 | eaa728ee | bellard | /* interrupt gate clear IF mask */
|
| 761 | eaa728ee | bellard | if ((type & 1) == 0) { |
| 762 | eaa728ee | bellard | env->eflags &= ~IF_MASK; |
| 763 | eaa728ee | bellard | } |
| 764 | eaa728ee | bellard | env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK); |
| 765 | eaa728ee | bellard | } |
| 766 | eaa728ee | bellard | |
| 767 | eaa728ee | bellard | #ifdef TARGET_X86_64
|
| 768 | eaa728ee | bellard | |
| 769 | 20054ef0 | Blue Swirl | #define PUSHQ(sp, val) \
|
| 770 | 20054ef0 | Blue Swirl | { \
|
| 771 | 20054ef0 | Blue Swirl | sp -= 8; \
|
| 772 | 329e607d | Blue Swirl | cpu_stq_kernel(env, sp, (val)); \ |
| 773 | 20054ef0 | Blue Swirl | } |
| 774 | eaa728ee | bellard | |
| 775 | 20054ef0 | Blue Swirl | #define POPQ(sp, val) \
|
| 776 | 20054ef0 | Blue Swirl | { \
|
| 777 | 329e607d | Blue Swirl | val = cpu_ldq_kernel(env, sp); \ |
| 778 | 20054ef0 | Blue Swirl | sp += 8; \
|
| 779 | 20054ef0 | Blue Swirl | } |
| 780 | eaa728ee | bellard | |
| 781 | 2999a0b2 | Blue Swirl | static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level) |
| 782 | eaa728ee | bellard | {
|
| 783 | eaa728ee | bellard | int index;
|
| 784 | eaa728ee | bellard | |
| 785 | eaa728ee | bellard | #if 0
|
| 786 | eaa728ee | bellard | printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
|
| 787 | eaa728ee | bellard | env->tr.base, env->tr.limit);
|
| 788 | eaa728ee | bellard | #endif
|
| 789 | eaa728ee | bellard | |
| 790 | 20054ef0 | Blue Swirl | if (!(env->tr.flags & DESC_P_MASK)) {
|
| 791 | eaa728ee | bellard | cpu_abort(env, "invalid tss");
|
| 792 | 20054ef0 | Blue Swirl | } |
| 793 | eaa728ee | bellard | index = 8 * level + 4; |
| 794 | 20054ef0 | Blue Swirl | if ((index + 7) > env->tr.limit) { |
| 795 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
|
| 796 | 20054ef0 | Blue Swirl | } |
| 797 | 329e607d | Blue Swirl | return cpu_ldq_kernel(env, env->tr.base + index);
|
| 798 | eaa728ee | bellard | } |
| 799 | eaa728ee | bellard | |
| 800 | eaa728ee | bellard | /* 64 bit interrupt */
|
| 801 | 2999a0b2 | Blue Swirl | static void do_interrupt64(CPUX86State *env, int intno, int is_int, |
| 802 | 2999a0b2 | Blue Swirl | int error_code, target_ulong next_eip, int is_hw) |
| 803 | eaa728ee | bellard | {
|
| 804 | eaa728ee | bellard | SegmentCache *dt; |
| 805 | eaa728ee | bellard | target_ulong ptr; |
| 806 | eaa728ee | bellard | int type, dpl, selector, cpl, ist;
|
| 807 | eaa728ee | bellard | int has_error_code, new_stack;
|
| 808 | eaa728ee | bellard | uint32_t e1, e2, e3, ss; |
| 809 | eaa728ee | bellard | target_ulong old_eip, esp, offset; |
| 810 | eaa728ee | bellard | |
| 811 | eaa728ee | bellard | has_error_code = 0;
|
| 812 | 20054ef0 | Blue Swirl | if (!is_int && !is_hw) {
|
| 813 | 20054ef0 | Blue Swirl | has_error_code = exception_has_error_code(intno); |
| 814 | 20054ef0 | Blue Swirl | } |
| 815 | 20054ef0 | Blue Swirl | if (is_int) {
|
| 816 | eaa728ee | bellard | old_eip = next_eip; |
| 817 | 20054ef0 | Blue Swirl | } else {
|
| 818 | eaa728ee | bellard | old_eip = env->eip; |
| 819 | 20054ef0 | Blue Swirl | } |
| 820 | eaa728ee | bellard | |
| 821 | eaa728ee | bellard | dt = &env->idt; |
| 822 | 20054ef0 | Blue Swirl | if (intno * 16 + 15 > dt->limit) { |
| 823 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2); |
| 824 | 20054ef0 | Blue Swirl | } |
| 825 | eaa728ee | bellard | ptr = dt->base + intno * 16;
|
| 826 | 329e607d | Blue Swirl | e1 = cpu_ldl_kernel(env, ptr); |
| 827 | 329e607d | Blue Swirl | e2 = cpu_ldl_kernel(env, ptr + 4);
|
| 828 | 329e607d | Blue Swirl | e3 = cpu_ldl_kernel(env, ptr + 8);
|
| 829 | eaa728ee | bellard | /* check gate type */
|
| 830 | eaa728ee | bellard | type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
|
| 831 | 20054ef0 | Blue Swirl | switch (type) {
|
| 832 | eaa728ee | bellard | case 14: /* 386 interrupt gate */ |
| 833 | eaa728ee | bellard | case 15: /* 386 trap gate */ |
| 834 | eaa728ee | bellard | break;
|
| 835 | eaa728ee | bellard | default:
|
| 836 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2); |
| 837 | eaa728ee | bellard | break;
|
| 838 | eaa728ee | bellard | } |
| 839 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 840 | eaa728ee | bellard | cpl = env->hflags & HF_CPL_MASK; |
| 841 | 1235fc06 | ths | /* check privilege if software int */
|
| 842 | 20054ef0 | Blue Swirl | if (is_int && dpl < cpl) {
|
| 843 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2); |
| 844 | 20054ef0 | Blue Swirl | } |
| 845 | eaa728ee | bellard | /* check valid bit */
|
| 846 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
|
| 847 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, intno * 16 + 2); |
| 848 | 20054ef0 | Blue Swirl | } |
| 849 | eaa728ee | bellard | selector = e1 >> 16;
|
| 850 | eaa728ee | bellard | offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff); |
| 851 | eaa728ee | bellard | ist = e2 & 7;
|
| 852 | 20054ef0 | Blue Swirl | if ((selector & 0xfffc) == 0) { |
| 853 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, 0);
|
| 854 | 20054ef0 | Blue Swirl | } |
| 855 | eaa728ee | bellard | |
| 856 | 2999a0b2 | Blue Swirl | if (load_segment(env, &e1, &e2, selector) != 0) { |
| 857 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 858 | 20054ef0 | Blue Swirl | } |
| 859 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
|
| 860 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 861 | 20054ef0 | Blue Swirl | } |
| 862 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 863 | 20054ef0 | Blue Swirl | if (dpl > cpl) {
|
| 864 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 865 | 20054ef0 | Blue Swirl | } |
| 866 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
|
| 867 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
| 868 | 20054ef0 | Blue Swirl | } |
| 869 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK)) {
|
| 870 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 871 | 20054ef0 | Blue Swirl | } |
| 872 | eaa728ee | bellard | if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) { |
| 873 | eaa728ee | bellard | /* to inner privilege */
|
| 874 | 20054ef0 | Blue Swirl | if (ist != 0) { |
| 875 | 2999a0b2 | Blue Swirl | esp = get_rsp_from_tss(env, ist + 3);
|
| 876 | 20054ef0 | Blue Swirl | } else {
|
| 877 | 2999a0b2 | Blue Swirl | esp = get_rsp_from_tss(env, dpl); |
| 878 | 20054ef0 | Blue Swirl | } |
| 879 | eaa728ee | bellard | esp &= ~0xfLL; /* align stack */ |
| 880 | eaa728ee | bellard | ss = 0;
|
| 881 | eaa728ee | bellard | new_stack = 1;
|
| 882 | eaa728ee | bellard | } else if ((e2 & DESC_C_MASK) || dpl == cpl) { |
| 883 | eaa728ee | bellard | /* to same privilege */
|
| 884 | 20054ef0 | Blue Swirl | if (env->eflags & VM_MASK) {
|
| 885 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 886 | 20054ef0 | Blue Swirl | } |
| 887 | eaa728ee | bellard | new_stack = 0;
|
| 888 | 20054ef0 | Blue Swirl | if (ist != 0) { |
| 889 | 2999a0b2 | Blue Swirl | esp = get_rsp_from_tss(env, ist + 3);
|
| 890 | 20054ef0 | Blue Swirl | } else {
|
| 891 | eaa728ee | bellard | esp = ESP; |
| 892 | 20054ef0 | Blue Swirl | } |
| 893 | eaa728ee | bellard | esp &= ~0xfLL; /* align stack */ |
| 894 | eaa728ee | bellard | dpl = cpl; |
| 895 | eaa728ee | bellard | } else {
|
| 896 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 897 | eaa728ee | bellard | new_stack = 0; /* avoid warning */ |
| 898 | eaa728ee | bellard | esp = 0; /* avoid warning */ |
| 899 | eaa728ee | bellard | } |
| 900 | eaa728ee | bellard | |
| 901 | eaa728ee | bellard | PUSHQ(esp, env->segs[R_SS].selector); |
| 902 | eaa728ee | bellard | PUSHQ(esp, ESP); |
| 903 | 997ff0d9 | Blue Swirl | PUSHQ(esp, cpu_compute_eflags(env)); |
| 904 | eaa728ee | bellard | PUSHQ(esp, env->segs[R_CS].selector); |
| 905 | eaa728ee | bellard | PUSHQ(esp, old_eip); |
| 906 | eaa728ee | bellard | if (has_error_code) {
|
| 907 | eaa728ee | bellard | PUSHQ(esp, error_code); |
| 908 | eaa728ee | bellard | } |
| 909 | eaa728ee | bellard | |
| 910 | eaa728ee | bellard | if (new_stack) {
|
| 911 | eaa728ee | bellard | ss = 0 | dpl;
|
| 912 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0); |
| 913 | eaa728ee | bellard | } |
| 914 | eaa728ee | bellard | ESP = esp; |
| 915 | eaa728ee | bellard | |
| 916 | eaa728ee | bellard | selector = (selector & ~3) | dpl;
|
| 917 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_CS, selector, |
| 918 | eaa728ee | bellard | get_seg_base(e1, e2), |
| 919 | eaa728ee | bellard | get_seg_limit(e1, e2), |
| 920 | eaa728ee | bellard | e2); |
| 921 | eaa728ee | bellard | cpu_x86_set_cpl(env, dpl); |
| 922 | eaa728ee | bellard | env->eip = offset; |
| 923 | eaa728ee | bellard | |
| 924 | eaa728ee | bellard | /* interrupt gate clear IF mask */
|
| 925 | eaa728ee | bellard | if ((type & 1) == 0) { |
| 926 | eaa728ee | bellard | env->eflags &= ~IF_MASK; |
| 927 | eaa728ee | bellard | } |
| 928 | eaa728ee | bellard | env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK); |
| 929 | eaa728ee | bellard | } |
| 930 | eaa728ee | bellard | #endif
|
| 931 | eaa728ee | bellard | |
| 932 | d9957a8b | blueswir1 | #ifdef TARGET_X86_64
|
| 933 | eaa728ee | bellard | #if defined(CONFIG_USER_ONLY)
|
| 934 | 2999a0b2 | Blue Swirl | void helper_syscall(CPUX86State *env, int next_eip_addend) |
| 935 | eaa728ee | bellard | {
|
| 936 | eaa728ee | bellard | env->exception_index = EXCP_SYSCALL; |
| 937 | eaa728ee | bellard | env->exception_next_eip = env->eip + next_eip_addend; |
| 938 | 1162c041 | Blue Swirl | cpu_loop_exit(env); |
| 939 | eaa728ee | bellard | } |
| 940 | eaa728ee | bellard | #else
|
| 941 | 2999a0b2 | Blue Swirl | void helper_syscall(CPUX86State *env, int next_eip_addend) |
| 942 | eaa728ee | bellard | {
|
| 943 | eaa728ee | bellard | int selector;
|
| 944 | eaa728ee | bellard | |
| 945 | eaa728ee | bellard | if (!(env->efer & MSR_EFER_SCE)) {
|
| 946 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP06_ILLOP, 0);
|
| 947 | eaa728ee | bellard | } |
| 948 | eaa728ee | bellard | selector = (env->star >> 32) & 0xffff; |
| 949 | eaa728ee | bellard | if (env->hflags & HF_LMA_MASK) {
|
| 950 | eaa728ee | bellard | int code64;
|
| 951 | eaa728ee | bellard | |
| 952 | a4165610 | liguang | env->regs[R_ECX] = env->eip + next_eip_addend; |
| 953 | 997ff0d9 | Blue Swirl | env->regs[11] = cpu_compute_eflags(env);
|
| 954 | eaa728ee | bellard | |
| 955 | eaa728ee | bellard | code64 = env->hflags & HF_CS64_MASK; |
| 956 | eaa728ee | bellard | |
| 957 | eaa728ee | bellard | cpu_x86_set_cpl(env, 0);
|
| 958 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
|
| 959 | eaa728ee | bellard | 0, 0xffffffff, |
| 960 | eaa728ee | bellard | DESC_G_MASK | DESC_P_MASK | |
| 961 | eaa728ee | bellard | DESC_S_MASK | |
| 962 | 20054ef0 | Blue Swirl | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
| 963 | 20054ef0 | Blue Swirl | DESC_L_MASK); |
| 964 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, |
| 965 | eaa728ee | bellard | 0, 0xffffffff, |
| 966 | eaa728ee | bellard | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 967 | eaa728ee | bellard | DESC_S_MASK | |
| 968 | eaa728ee | bellard | DESC_W_MASK | DESC_A_MASK); |
| 969 | eaa728ee | bellard | env->eflags &= ~env->fmask; |
| 970 | 997ff0d9 | Blue Swirl | cpu_load_eflags(env, env->eflags, 0);
|
| 971 | 20054ef0 | Blue Swirl | if (code64) {
|
| 972 | eaa728ee | bellard | env->eip = env->lstar; |
| 973 | 20054ef0 | Blue Swirl | } else {
|
| 974 | eaa728ee | bellard | env->eip = env->cstar; |
| 975 | 20054ef0 | Blue Swirl | } |
| 976 | d9957a8b | blueswir1 | } else {
|
| 977 | a4165610 | liguang | env->regs[R_ECX] = (uint32_t)(env->eip + next_eip_addend); |
| 978 | eaa728ee | bellard | |
| 979 | eaa728ee | bellard | cpu_x86_set_cpl(env, 0);
|
| 980 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
|
| 981 | eaa728ee | bellard | 0, 0xffffffff, |
| 982 | eaa728ee | bellard | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 983 | eaa728ee | bellard | DESC_S_MASK | |
| 984 | eaa728ee | bellard | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
| 985 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, |
| 986 | eaa728ee | bellard | 0, 0xffffffff, |
| 987 | eaa728ee | bellard | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 988 | eaa728ee | bellard | DESC_S_MASK | |
| 989 | eaa728ee | bellard | DESC_W_MASK | DESC_A_MASK); |
| 990 | eaa728ee | bellard | env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK); |
| 991 | eaa728ee | bellard | env->eip = (uint32_t)env->star; |
| 992 | eaa728ee | bellard | } |
| 993 | eaa728ee | bellard | } |
| 994 | eaa728ee | bellard | #endif
|
| 995 | d9957a8b | blueswir1 | #endif
|
| 996 | eaa728ee | bellard | |
| 997 | d9957a8b | blueswir1 | #ifdef TARGET_X86_64
|
| 998 | 2999a0b2 | Blue Swirl | void helper_sysret(CPUX86State *env, int dflag) |
| 999 | eaa728ee | bellard | {
|
| 1000 | eaa728ee | bellard | int cpl, selector;
|
| 1001 | eaa728ee | bellard | |
| 1002 | eaa728ee | bellard | if (!(env->efer & MSR_EFER_SCE)) {
|
| 1003 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP06_ILLOP, 0);
|
| 1004 | eaa728ee | bellard | } |
| 1005 | eaa728ee | bellard | cpl = env->hflags & HF_CPL_MASK; |
| 1006 | eaa728ee | bellard | if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) { |
| 1007 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, 0);
|
| 1008 | eaa728ee | bellard | } |
| 1009 | eaa728ee | bellard | selector = (env->star >> 48) & 0xffff; |
| 1010 | eaa728ee | bellard | if (env->hflags & HF_LMA_MASK) {
|
| 1011 | eaa728ee | bellard | if (dflag == 2) { |
| 1012 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3, |
| 1013 | eaa728ee | bellard | 0, 0xffffffff, |
| 1014 | eaa728ee | bellard | DESC_G_MASK | DESC_P_MASK | |
| 1015 | eaa728ee | bellard | DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
| 1016 | eaa728ee | bellard | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
| 1017 | eaa728ee | bellard | DESC_L_MASK); |
| 1018 | a4165610 | liguang | env->eip = env->regs[R_ECX]; |
| 1019 | eaa728ee | bellard | } else {
|
| 1020 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_CS, selector | 3,
|
| 1021 | eaa728ee | bellard | 0, 0xffffffff, |
| 1022 | eaa728ee | bellard | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 1023 | eaa728ee | bellard | DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
| 1024 | eaa728ee | bellard | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
| 1025 | a4165610 | liguang | env->eip = (uint32_t)env->regs[R_ECX]; |
| 1026 | eaa728ee | bellard | } |
| 1027 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_SS, selector + 8,
|
| 1028 | eaa728ee | bellard | 0, 0xffffffff, |
| 1029 | eaa728ee | bellard | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 1030 | eaa728ee | bellard | DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
| 1031 | eaa728ee | bellard | DESC_W_MASK | DESC_A_MASK); |
| 1032 | 997ff0d9 | Blue Swirl | cpu_load_eflags(env, (uint32_t)(env->regs[11]), TF_MASK | AC_MASK
|
| 1033 | 997ff0d9 | Blue Swirl | | ID_MASK | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | |
| 1034 | 997ff0d9 | Blue Swirl | NT_MASK); |
| 1035 | eaa728ee | bellard | cpu_x86_set_cpl(env, 3);
|
| 1036 | d9957a8b | blueswir1 | } else {
|
| 1037 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_CS, selector | 3,
|
| 1038 | eaa728ee | bellard | 0, 0xffffffff, |
| 1039 | eaa728ee | bellard | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 1040 | eaa728ee | bellard | DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
| 1041 | eaa728ee | bellard | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
| 1042 | a4165610 | liguang | env->eip = (uint32_t)env->regs[R_ECX]; |
| 1043 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_SS, selector + 8,
|
| 1044 | eaa728ee | bellard | 0, 0xffffffff, |
| 1045 | eaa728ee | bellard | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 1046 | eaa728ee | bellard | DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
| 1047 | eaa728ee | bellard | DESC_W_MASK | DESC_A_MASK); |
| 1048 | eaa728ee | bellard | env->eflags |= IF_MASK; |
| 1049 | eaa728ee | bellard | cpu_x86_set_cpl(env, 3);
|
| 1050 | eaa728ee | bellard | } |
| 1051 | eaa728ee | bellard | } |
| 1052 | d9957a8b | blueswir1 | #endif
|
| 1053 | eaa728ee | bellard | |
| 1054 | eaa728ee | bellard | /* real mode interrupt */
|
| 1055 | 2999a0b2 | Blue Swirl | static void do_interrupt_real(CPUX86State *env, int intno, int is_int, |
| 1056 | 2999a0b2 | Blue Swirl | int error_code, unsigned int next_eip) |
| 1057 | eaa728ee | bellard | {
|
| 1058 | eaa728ee | bellard | SegmentCache *dt; |
| 1059 | eaa728ee | bellard | target_ulong ptr, ssp; |
| 1060 | eaa728ee | bellard | int selector;
|
| 1061 | eaa728ee | bellard | uint32_t offset, esp; |
| 1062 | eaa728ee | bellard | uint32_t old_cs, old_eip; |
| 1063 | eaa728ee | bellard | |
| 1064 | 20054ef0 | Blue Swirl | /* real mode (simpler!) */
|
| 1065 | eaa728ee | bellard | dt = &env->idt; |
| 1066 | 20054ef0 | Blue Swirl | if (intno * 4 + 3 > dt->limit) { |
| 1067 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
| 1068 | 20054ef0 | Blue Swirl | } |
| 1069 | eaa728ee | bellard | ptr = dt->base + intno * 4;
|
| 1070 | 329e607d | Blue Swirl | offset = cpu_lduw_kernel(env, ptr); |
| 1071 | 329e607d | Blue Swirl | selector = cpu_lduw_kernel(env, ptr + 2);
|
| 1072 | eaa728ee | bellard | esp = ESP; |
| 1073 | eaa728ee | bellard | ssp = env->segs[R_SS].base; |
| 1074 | 20054ef0 | Blue Swirl | if (is_int) {
|
| 1075 | eaa728ee | bellard | old_eip = next_eip; |
| 1076 | 20054ef0 | Blue Swirl | } else {
|
| 1077 | eaa728ee | bellard | old_eip = env->eip; |
| 1078 | 20054ef0 | Blue Swirl | } |
| 1079 | eaa728ee | bellard | old_cs = env->segs[R_CS].selector; |
| 1080 | 20054ef0 | Blue Swirl | /* XXX: use SS segment size? */
|
| 1081 | 997ff0d9 | Blue Swirl | PUSHW(ssp, esp, 0xffff, cpu_compute_eflags(env));
|
| 1082 | eaa728ee | bellard | PUSHW(ssp, esp, 0xffff, old_cs);
|
| 1083 | eaa728ee | bellard | PUSHW(ssp, esp, 0xffff, old_eip);
|
| 1084 | eaa728ee | bellard | |
| 1085 | eaa728ee | bellard | /* update processor state */
|
| 1086 | eaa728ee | bellard | ESP = (ESP & ~0xffff) | (esp & 0xffff); |
| 1087 | eaa728ee | bellard | env->eip = offset; |
| 1088 | eaa728ee | bellard | env->segs[R_CS].selector = selector; |
| 1089 | eaa728ee | bellard | env->segs[R_CS].base = (selector << 4);
|
| 1090 | eaa728ee | bellard | env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK); |
| 1091 | eaa728ee | bellard | } |
| 1092 | eaa728ee | bellard | |
| 1093 | e694d4e2 | Blue Swirl | #if defined(CONFIG_USER_ONLY)
|
| 1094 | eaa728ee | bellard | /* fake user mode interrupt */
|
| 1095 | 2999a0b2 | Blue Swirl | static void do_interrupt_user(CPUX86State *env, int intno, int is_int, |
| 1096 | 2999a0b2 | Blue Swirl | int error_code, target_ulong next_eip)
|
| 1097 | eaa728ee | bellard | {
|
| 1098 | eaa728ee | bellard | SegmentCache *dt; |
| 1099 | eaa728ee | bellard | target_ulong ptr; |
| 1100 | eaa728ee | bellard | int dpl, cpl, shift;
|
| 1101 | eaa728ee | bellard | uint32_t e2; |
| 1102 | eaa728ee | bellard | |
| 1103 | eaa728ee | bellard | dt = &env->idt; |
| 1104 | eaa728ee | bellard | if (env->hflags & HF_LMA_MASK) {
|
| 1105 | eaa728ee | bellard | shift = 4;
|
| 1106 | eaa728ee | bellard | } else {
|
| 1107 | eaa728ee | bellard | shift = 3;
|
| 1108 | eaa728ee | bellard | } |
| 1109 | eaa728ee | bellard | ptr = dt->base + (intno << shift); |
| 1110 | 329e607d | Blue Swirl | e2 = cpu_ldl_kernel(env, ptr + 4);
|
| 1111 | eaa728ee | bellard | |
| 1112 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 1113 | eaa728ee | bellard | cpl = env->hflags & HF_CPL_MASK; |
| 1114 | 1235fc06 | ths | /* check privilege if software int */
|
| 1115 | 20054ef0 | Blue Swirl | if (is_int && dpl < cpl) {
|
| 1116 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, (intno << shift) + 2);
|
| 1117 | 20054ef0 | Blue Swirl | } |
| 1118 | eaa728ee | bellard | |
| 1119 | eaa728ee | bellard | /* Since we emulate only user space, we cannot do more than
|
| 1120 | eaa728ee | bellard | exiting the emulation with the suitable exception and error
|
| 1121 | eaa728ee | bellard | code */
|
| 1122 | 20054ef0 | Blue Swirl | if (is_int) {
|
| 1123 | eaa728ee | bellard | EIP = next_eip; |
| 1124 | 20054ef0 | Blue Swirl | } |
| 1125 | eaa728ee | bellard | } |
| 1126 | eaa728ee | bellard | |
| 1127 | e694d4e2 | Blue Swirl | #else
|
| 1128 | e694d4e2 | Blue Swirl | |
| 1129 | 2999a0b2 | Blue Swirl | static void handle_even_inj(CPUX86State *env, int intno, int is_int, |
| 1130 | 2999a0b2 | Blue Swirl | int error_code, int is_hw, int rm) |
| 1131 | 2ed51f5b | aliguori | {
|
| 1132 | 20054ef0 | Blue Swirl | uint32_t event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
|
| 1133 | 20054ef0 | Blue Swirl | control.event_inj)); |
| 1134 | 20054ef0 | Blue Swirl | |
| 1135 | 2ed51f5b | aliguori | if (!(event_inj & SVM_EVTINJ_VALID)) {
|
| 1136 | 20054ef0 | Blue Swirl | int type;
|
| 1137 | 20054ef0 | Blue Swirl | |
| 1138 | 20054ef0 | Blue Swirl | if (is_int) {
|
| 1139 | 20054ef0 | Blue Swirl | type = SVM_EVTINJ_TYPE_SOFT; |
| 1140 | 20054ef0 | Blue Swirl | } else {
|
| 1141 | 20054ef0 | Blue Swirl | type = SVM_EVTINJ_TYPE_EXEPT; |
| 1142 | 20054ef0 | Blue Swirl | } |
| 1143 | 20054ef0 | Blue Swirl | event_inj = intno | type | SVM_EVTINJ_VALID; |
| 1144 | 20054ef0 | Blue Swirl | if (!rm && exception_has_error_code(intno)) {
|
| 1145 | 20054ef0 | Blue Swirl | event_inj |= SVM_EVTINJ_VALID_ERR; |
| 1146 | 20054ef0 | Blue Swirl | stl_phys(env->vm_vmcb + offsetof(struct vmcb,
|
| 1147 | 20054ef0 | Blue Swirl | control.event_inj_err), |
| 1148 | 20054ef0 | Blue Swirl | error_code); |
| 1149 | 20054ef0 | Blue Swirl | } |
| 1150 | 20054ef0 | Blue Swirl | stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
|
| 1151 | 20054ef0 | Blue Swirl | event_inj); |
| 1152 | 2ed51f5b | aliguori | } |
| 1153 | 2ed51f5b | aliguori | } |
| 1154 | 00ea18d1 | aliguori | #endif
|
| 1155 | 2ed51f5b | aliguori | |
| 1156 | eaa728ee | bellard | /*
|
| 1157 | eaa728ee | bellard | * Begin execution of an interruption. is_int is TRUE if coming from
|
| 1158 | eaa728ee | bellard | * the int instruction. next_eip is the EIP value AFTER the interrupt
|
| 1159 | eaa728ee | bellard | * instruction. It is only relevant if is_int is TRUE.
|
| 1160 | eaa728ee | bellard | */
|
| 1161 | 2999a0b2 | Blue Swirl | static void do_interrupt_all(CPUX86State *env, int intno, int is_int, |
| 1162 | 2999a0b2 | Blue Swirl | int error_code, target_ulong next_eip, int is_hw) |
| 1163 | eaa728ee | bellard | {
|
| 1164 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
| 1165 | eaa728ee | bellard | if ((env->cr[0] & CR0_PE_MASK)) { |
| 1166 | eaa728ee | bellard | static int count; |
| 1167 | 20054ef0 | Blue Swirl | |
| 1168 | 20054ef0 | Blue Swirl | qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx
|
| 1169 | 20054ef0 | Blue Swirl | " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx, |
| 1170 | 20054ef0 | Blue Swirl | count, intno, error_code, is_int, |
| 1171 | 20054ef0 | Blue Swirl | env->hflags & HF_CPL_MASK, |
| 1172 | 20054ef0 | Blue Swirl | env->segs[R_CS].selector, EIP, |
| 1173 | 20054ef0 | Blue Swirl | (int)env->segs[R_CS].base + EIP,
|
| 1174 | 20054ef0 | Blue Swirl | env->segs[R_SS].selector, ESP); |
| 1175 | eaa728ee | bellard | if (intno == 0x0e) { |
| 1176 | 93fcfe39 | aliguori | qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]); |
| 1177 | eaa728ee | bellard | } else {
|
| 1178 | 4b34e3ad | liguang | qemu_log(" env->regs[R_EAX]=" TARGET_FMT_lx, env->regs[R_EAX]);
|
| 1179 | eaa728ee | bellard | } |
| 1180 | 93fcfe39 | aliguori | qemu_log("\n");
|
| 1181 | 6fd2a026 | Peter Maydell | log_cpu_state(env, CPU_DUMP_CCOP); |
| 1182 | eaa728ee | bellard | #if 0
|
| 1183 | eaa728ee | bellard | {
|
| 1184 | eaa728ee | bellard | int i;
|
| 1185 | 9bd5494e | Adam Lackorzynski | target_ulong ptr;
|
| 1186 | 20054ef0 | Blue Swirl | |
| 1187 | 93fcfe39 | aliguori | qemu_log(" code=");
|
| 1188 | eaa728ee | bellard | ptr = env->segs[R_CS].base + env->eip;
|
| 1189 | 20054ef0 | Blue Swirl | for (i = 0; i < 16; i++) {
|
| 1190 | 93fcfe39 | aliguori | qemu_log(" %02x", ldub(ptr + i));
|
| 1191 | eaa728ee | bellard | }
|
| 1192 | 93fcfe39 | aliguori | qemu_log("\n");
|
| 1193 | eaa728ee | bellard | }
|
| 1194 | eaa728ee | bellard | #endif
|
| 1195 | eaa728ee | bellard | count++; |
| 1196 | eaa728ee | bellard | } |
| 1197 | eaa728ee | bellard | } |
| 1198 | eaa728ee | bellard | if (env->cr[0] & CR0_PE_MASK) { |
| 1199 | 00ea18d1 | aliguori | #if !defined(CONFIG_USER_ONLY)
|
| 1200 | 20054ef0 | Blue Swirl | if (env->hflags & HF_SVMI_MASK) {
|
| 1201 | 2999a0b2 | Blue Swirl | handle_even_inj(env, intno, is_int, error_code, is_hw, 0);
|
| 1202 | 20054ef0 | Blue Swirl | } |
| 1203 | 00ea18d1 | aliguori | #endif
|
| 1204 | eb38c52c | blueswir1 | #ifdef TARGET_X86_64
|
| 1205 | eaa728ee | bellard | if (env->hflags & HF_LMA_MASK) {
|
| 1206 | 2999a0b2 | Blue Swirl | do_interrupt64(env, intno, is_int, error_code, next_eip, is_hw); |
| 1207 | eaa728ee | bellard | } else
|
| 1208 | eaa728ee | bellard | #endif
|
| 1209 | eaa728ee | bellard | {
|
| 1210 | 2999a0b2 | Blue Swirl | do_interrupt_protected(env, intno, is_int, error_code, next_eip, |
| 1211 | 2999a0b2 | Blue Swirl | is_hw); |
| 1212 | eaa728ee | bellard | } |
| 1213 | eaa728ee | bellard | } else {
|
| 1214 | 00ea18d1 | aliguori | #if !defined(CONFIG_USER_ONLY)
|
| 1215 | 20054ef0 | Blue Swirl | if (env->hflags & HF_SVMI_MASK) {
|
| 1216 | 2999a0b2 | Blue Swirl | handle_even_inj(env, intno, is_int, error_code, is_hw, 1);
|
| 1217 | 20054ef0 | Blue Swirl | } |
| 1218 | 00ea18d1 | aliguori | #endif
|
| 1219 | 2999a0b2 | Blue Swirl | do_interrupt_real(env, intno, is_int, error_code, next_eip); |
| 1220 | eaa728ee | bellard | } |
| 1221 | 2ed51f5b | aliguori | |
| 1222 | 00ea18d1 | aliguori | #if !defined(CONFIG_USER_ONLY)
|
| 1223 | 2ed51f5b | aliguori | if (env->hflags & HF_SVMI_MASK) {
|
| 1224 | 20054ef0 | Blue Swirl | uint32_t event_inj = ldl_phys(env->vm_vmcb + |
| 1225 | 20054ef0 | Blue Swirl | offsetof(struct vmcb,
|
| 1226 | 20054ef0 | Blue Swirl | control.event_inj)); |
| 1227 | 20054ef0 | Blue Swirl | |
| 1228 | 20054ef0 | Blue Swirl | stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
|
| 1229 | 20054ef0 | Blue Swirl | event_inj & ~SVM_EVTINJ_VALID); |
| 1230 | 2ed51f5b | aliguori | } |
| 1231 | 00ea18d1 | aliguori | #endif
|
| 1232 | eaa728ee | bellard | } |
| 1233 | eaa728ee | bellard | |
| 1234 | 97a8ea5a | Andreas Fรคrber | void x86_cpu_do_interrupt(CPUState *cs)
|
| 1235 | e694d4e2 | Blue Swirl | {
|
| 1236 | 97a8ea5a | Andreas Fรคrber | X86CPU *cpu = X86_CPU(cs); |
| 1237 | 97a8ea5a | Andreas Fรคrber | CPUX86State *env = &cpu->env; |
| 1238 | 97a8ea5a | Andreas Fรคrber | |
| 1239 | e694d4e2 | Blue Swirl | #if defined(CONFIG_USER_ONLY)
|
| 1240 | e694d4e2 | Blue Swirl | /* if user mode only, we simulate a fake exception
|
| 1241 | e694d4e2 | Blue Swirl | which will be handled outside the cpu execution
|
| 1242 | e694d4e2 | Blue Swirl | loop */
|
| 1243 | 2999a0b2 | Blue Swirl | do_interrupt_user(env, env->exception_index, |
| 1244 | e694d4e2 | Blue Swirl | env->exception_is_int, |
| 1245 | e694d4e2 | Blue Swirl | env->error_code, |
| 1246 | e694d4e2 | Blue Swirl | env->exception_next_eip); |
| 1247 | e694d4e2 | Blue Swirl | /* successfully delivered */
|
| 1248 | e694d4e2 | Blue Swirl | env->old_exception = -1;
|
| 1249 | e694d4e2 | Blue Swirl | #else
|
| 1250 | e694d4e2 | Blue Swirl | /* simulate a real cpu exception. On i386, it can
|
| 1251 | e694d4e2 | Blue Swirl | trigger new exceptions, but we do not handle
|
| 1252 | e694d4e2 | Blue Swirl | double or triple faults yet. */
|
| 1253 | 2999a0b2 | Blue Swirl | do_interrupt_all(env, env->exception_index, |
| 1254 | e694d4e2 | Blue Swirl | env->exception_is_int, |
| 1255 | e694d4e2 | Blue Swirl | env->error_code, |
| 1256 | e694d4e2 | Blue Swirl | env->exception_next_eip, 0);
|
| 1257 | e694d4e2 | Blue Swirl | /* successfully delivered */
|
| 1258 | e694d4e2 | Blue Swirl | env->old_exception = -1;
|
| 1259 | e694d4e2 | Blue Swirl | #endif
|
| 1260 | e694d4e2 | Blue Swirl | } |
| 1261 | e694d4e2 | Blue Swirl | |
| 1262 | 2999a0b2 | Blue Swirl | void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw) |
| 1263 | e694d4e2 | Blue Swirl | {
|
| 1264 | 2999a0b2 | Blue Swirl | do_interrupt_all(env, intno, 0, 0, 0, is_hw); |
| 1265 | e694d4e2 | Blue Swirl | } |
| 1266 | e694d4e2 | Blue Swirl | |
| 1267 | 2999a0b2 | Blue Swirl | void helper_enter_level(CPUX86State *env, int level, int data32, |
| 1268 | 2999a0b2 | Blue Swirl | target_ulong t1) |
| 1269 | eaa728ee | bellard | {
|
| 1270 | eaa728ee | bellard | target_ulong ssp; |
| 1271 | eaa728ee | bellard | uint32_t esp_mask, esp, ebp; |
| 1272 | eaa728ee | bellard | |
| 1273 | eaa728ee | bellard | esp_mask = get_sp_mask(env->segs[R_SS].flags); |
| 1274 | eaa728ee | bellard | ssp = env->segs[R_SS].base; |
| 1275 | eaa728ee | bellard | ebp = EBP; |
| 1276 | eaa728ee | bellard | esp = ESP; |
| 1277 | eaa728ee | bellard | if (data32) {
|
| 1278 | eaa728ee | bellard | /* 32 bit */
|
| 1279 | eaa728ee | bellard | esp -= 4;
|
| 1280 | eaa728ee | bellard | while (--level) {
|
| 1281 | eaa728ee | bellard | esp -= 4;
|
| 1282 | eaa728ee | bellard | ebp -= 4;
|
| 1283 | 329e607d | Blue Swirl | cpu_stl_data(env, ssp + (esp & esp_mask), |
| 1284 | 329e607d | Blue Swirl | cpu_ldl_data(env, ssp + (ebp & esp_mask))); |
| 1285 | eaa728ee | bellard | } |
| 1286 | eaa728ee | bellard | esp -= 4;
|
| 1287 | 329e607d | Blue Swirl | cpu_stl_data(env, ssp + (esp & esp_mask), t1); |
| 1288 | eaa728ee | bellard | } else {
|
| 1289 | eaa728ee | bellard | /* 16 bit */
|
| 1290 | eaa728ee | bellard | esp -= 2;
|
| 1291 | eaa728ee | bellard | while (--level) {
|
| 1292 | eaa728ee | bellard | esp -= 2;
|
| 1293 | eaa728ee | bellard | ebp -= 2;
|
| 1294 | 329e607d | Blue Swirl | cpu_stw_data(env, ssp + (esp & esp_mask), |
| 1295 | 329e607d | Blue Swirl | cpu_lduw_data(env, ssp + (ebp & esp_mask))); |
| 1296 | eaa728ee | bellard | } |
| 1297 | eaa728ee | bellard | esp -= 2;
|
| 1298 | 329e607d | Blue Swirl | cpu_stw_data(env, ssp + (esp & esp_mask), t1); |
| 1299 | eaa728ee | bellard | } |
| 1300 | eaa728ee | bellard | } |
| 1301 | eaa728ee | bellard | |
| 1302 | eaa728ee | bellard | #ifdef TARGET_X86_64
|
| 1303 | 2999a0b2 | Blue Swirl | void helper_enter64_level(CPUX86State *env, int level, int data64, |
| 1304 | 2999a0b2 | Blue Swirl | target_ulong t1) |
| 1305 | eaa728ee | bellard | {
|
| 1306 | eaa728ee | bellard | target_ulong esp, ebp; |
| 1307 | 20054ef0 | Blue Swirl | |
| 1308 | eaa728ee | bellard | ebp = EBP; |
| 1309 | eaa728ee | bellard | esp = ESP; |
| 1310 | eaa728ee | bellard | |
| 1311 | eaa728ee | bellard | if (data64) {
|
| 1312 | eaa728ee | bellard | /* 64 bit */
|
| 1313 | eaa728ee | bellard | esp -= 8;
|
| 1314 | eaa728ee | bellard | while (--level) {
|
| 1315 | eaa728ee | bellard | esp -= 8;
|
| 1316 | eaa728ee | bellard | ebp -= 8;
|
| 1317 | 329e607d | Blue Swirl | cpu_stq_data(env, esp, cpu_ldq_data(env, ebp)); |
| 1318 | eaa728ee | bellard | } |
| 1319 | eaa728ee | bellard | esp -= 8;
|
| 1320 | 329e607d | Blue Swirl | cpu_stq_data(env, esp, t1); |
| 1321 | eaa728ee | bellard | } else {
|
| 1322 | eaa728ee | bellard | /* 16 bit */
|
| 1323 | eaa728ee | bellard | esp -= 2;
|
| 1324 | eaa728ee | bellard | while (--level) {
|
| 1325 | eaa728ee | bellard | esp -= 2;
|
| 1326 | eaa728ee | bellard | ebp -= 2;
|
| 1327 | 329e607d | Blue Swirl | cpu_stw_data(env, esp, cpu_lduw_data(env, ebp)); |
| 1328 | eaa728ee | bellard | } |
| 1329 | eaa728ee | bellard | esp -= 2;
|
| 1330 | 329e607d | Blue Swirl | cpu_stw_data(env, esp, t1); |
| 1331 | eaa728ee | bellard | } |
| 1332 | eaa728ee | bellard | } |
| 1333 | eaa728ee | bellard | #endif
|
| 1334 | eaa728ee | bellard | |
| 1335 | 2999a0b2 | Blue Swirl | void helper_lldt(CPUX86State *env, int selector) |
| 1336 | eaa728ee | bellard | {
|
| 1337 | eaa728ee | bellard | SegmentCache *dt; |
| 1338 | eaa728ee | bellard | uint32_t e1, e2; |
| 1339 | eaa728ee | bellard | int index, entry_limit;
|
| 1340 | eaa728ee | bellard | target_ulong ptr; |
| 1341 | eaa728ee | bellard | |
| 1342 | eaa728ee | bellard | selector &= 0xffff;
|
| 1343 | eaa728ee | bellard | if ((selector & 0xfffc) == 0) { |
| 1344 | eaa728ee | bellard | /* XXX: NULL selector case: invalid LDT */
|
| 1345 | eaa728ee | bellard | env->ldt.base = 0;
|
| 1346 | eaa728ee | bellard | env->ldt.limit = 0;
|
| 1347 | eaa728ee | bellard | } else {
|
| 1348 | 20054ef0 | Blue Swirl | if (selector & 0x4) { |
| 1349 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1350 | 20054ef0 | Blue Swirl | } |
| 1351 | eaa728ee | bellard | dt = &env->gdt; |
| 1352 | eaa728ee | bellard | index = selector & ~7;
|
| 1353 | eaa728ee | bellard | #ifdef TARGET_X86_64
|
| 1354 | 20054ef0 | Blue Swirl | if (env->hflags & HF_LMA_MASK) {
|
| 1355 | eaa728ee | bellard | entry_limit = 15;
|
| 1356 | 20054ef0 | Blue Swirl | } else
|
| 1357 | eaa728ee | bellard | #endif
|
| 1358 | 20054ef0 | Blue Swirl | {
|
| 1359 | eaa728ee | bellard | entry_limit = 7;
|
| 1360 | 20054ef0 | Blue Swirl | } |
| 1361 | 20054ef0 | Blue Swirl | if ((index + entry_limit) > dt->limit) {
|
| 1362 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1363 | 20054ef0 | Blue Swirl | } |
| 1364 | eaa728ee | bellard | ptr = dt->base + index; |
| 1365 | 329e607d | Blue Swirl | e1 = cpu_ldl_kernel(env, ptr); |
| 1366 | 329e607d | Blue Swirl | e2 = cpu_ldl_kernel(env, ptr + 4);
|
| 1367 | 20054ef0 | Blue Swirl | if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) { |
| 1368 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1369 | 20054ef0 | Blue Swirl | } |
| 1370 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
|
| 1371 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
| 1372 | 20054ef0 | Blue Swirl | } |
| 1373 | eaa728ee | bellard | #ifdef TARGET_X86_64
|
| 1374 | eaa728ee | bellard | if (env->hflags & HF_LMA_MASK) {
|
| 1375 | eaa728ee | bellard | uint32_t e3; |
| 1376 | 20054ef0 | Blue Swirl | |
| 1377 | 329e607d | Blue Swirl | e3 = cpu_ldl_kernel(env, ptr + 8);
|
| 1378 | eaa728ee | bellard | load_seg_cache_raw_dt(&env->ldt, e1, e2); |
| 1379 | eaa728ee | bellard | env->ldt.base |= (target_ulong)e3 << 32;
|
| 1380 | eaa728ee | bellard | } else
|
| 1381 | eaa728ee | bellard | #endif
|
| 1382 | eaa728ee | bellard | {
|
| 1383 | eaa728ee | bellard | load_seg_cache_raw_dt(&env->ldt, e1, e2); |
| 1384 | eaa728ee | bellard | } |
| 1385 | eaa728ee | bellard | } |
| 1386 | eaa728ee | bellard | env->ldt.selector = selector; |
| 1387 | eaa728ee | bellard | } |
| 1388 | eaa728ee | bellard | |
| 1389 | 2999a0b2 | Blue Swirl | void helper_ltr(CPUX86State *env, int selector) |
| 1390 | eaa728ee | bellard | {
|
| 1391 | eaa728ee | bellard | SegmentCache *dt; |
| 1392 | eaa728ee | bellard | uint32_t e1, e2; |
| 1393 | eaa728ee | bellard | int index, type, entry_limit;
|
| 1394 | eaa728ee | bellard | target_ulong ptr; |
| 1395 | eaa728ee | bellard | |
| 1396 | eaa728ee | bellard | selector &= 0xffff;
|
| 1397 | eaa728ee | bellard | if ((selector & 0xfffc) == 0) { |
| 1398 | eaa728ee | bellard | /* NULL selector case: invalid TR */
|
| 1399 | eaa728ee | bellard | env->tr.base = 0;
|
| 1400 | eaa728ee | bellard | env->tr.limit = 0;
|
| 1401 | eaa728ee | bellard | env->tr.flags = 0;
|
| 1402 | eaa728ee | bellard | } else {
|
| 1403 | 20054ef0 | Blue Swirl | if (selector & 0x4) { |
| 1404 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1405 | 20054ef0 | Blue Swirl | } |
| 1406 | eaa728ee | bellard | dt = &env->gdt; |
| 1407 | eaa728ee | bellard | index = selector & ~7;
|
| 1408 | eaa728ee | bellard | #ifdef TARGET_X86_64
|
| 1409 | 20054ef0 | Blue Swirl | if (env->hflags & HF_LMA_MASK) {
|
| 1410 | eaa728ee | bellard | entry_limit = 15;
|
| 1411 | 20054ef0 | Blue Swirl | } else
|
| 1412 | eaa728ee | bellard | #endif
|
| 1413 | 20054ef0 | Blue Swirl | {
|
| 1414 | eaa728ee | bellard | entry_limit = 7;
|
| 1415 | 20054ef0 | Blue Swirl | } |
| 1416 | 20054ef0 | Blue Swirl | if ((index + entry_limit) > dt->limit) {
|
| 1417 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1418 | 20054ef0 | Blue Swirl | } |
| 1419 | eaa728ee | bellard | ptr = dt->base + index; |
| 1420 | 329e607d | Blue Swirl | e1 = cpu_ldl_kernel(env, ptr); |
| 1421 | 329e607d | Blue Swirl | e2 = cpu_ldl_kernel(env, ptr + 4);
|
| 1422 | eaa728ee | bellard | type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
|
| 1423 | eaa728ee | bellard | if ((e2 & DESC_S_MASK) ||
|
| 1424 | 20054ef0 | Blue Swirl | (type != 1 && type != 9)) { |
| 1425 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1426 | 20054ef0 | Blue Swirl | } |
| 1427 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
|
| 1428 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
| 1429 | 20054ef0 | Blue Swirl | } |
| 1430 | eaa728ee | bellard | #ifdef TARGET_X86_64
|
| 1431 | eaa728ee | bellard | if (env->hflags & HF_LMA_MASK) {
|
| 1432 | eaa728ee | bellard | uint32_t e3, e4; |
| 1433 | 20054ef0 | Blue Swirl | |
| 1434 | 329e607d | Blue Swirl | e3 = cpu_ldl_kernel(env, ptr + 8);
|
| 1435 | 329e607d | Blue Swirl | e4 = cpu_ldl_kernel(env, ptr + 12);
|
| 1436 | 20054ef0 | Blue Swirl | if ((e4 >> DESC_TYPE_SHIFT) & 0xf) { |
| 1437 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1438 | 20054ef0 | Blue Swirl | } |
| 1439 | eaa728ee | bellard | load_seg_cache_raw_dt(&env->tr, e1, e2); |
| 1440 | eaa728ee | bellard | env->tr.base |= (target_ulong)e3 << 32;
|
| 1441 | eaa728ee | bellard | } else
|
| 1442 | eaa728ee | bellard | #endif
|
| 1443 | eaa728ee | bellard | {
|
| 1444 | eaa728ee | bellard | load_seg_cache_raw_dt(&env->tr, e1, e2); |
| 1445 | eaa728ee | bellard | } |
| 1446 | eaa728ee | bellard | e2 |= DESC_TSS_BUSY_MASK; |
| 1447 | 329e607d | Blue Swirl | cpu_stl_kernel(env, ptr + 4, e2);
|
| 1448 | eaa728ee | bellard | } |
| 1449 | eaa728ee | bellard | env->tr.selector = selector; |
| 1450 | eaa728ee | bellard | } |
| 1451 | eaa728ee | bellard | |
| 1452 | eaa728ee | bellard | /* only works if protected mode and not VM86. seg_reg must be != R_CS */
|
| 1453 | 2999a0b2 | Blue Swirl | void helper_load_seg(CPUX86State *env, int seg_reg, int selector) |
| 1454 | eaa728ee | bellard | {
|
| 1455 | eaa728ee | bellard | uint32_t e1, e2; |
| 1456 | eaa728ee | bellard | int cpl, dpl, rpl;
|
| 1457 | eaa728ee | bellard | SegmentCache *dt; |
| 1458 | eaa728ee | bellard | int index;
|
| 1459 | eaa728ee | bellard | target_ulong ptr; |
| 1460 | eaa728ee | bellard | |
| 1461 | eaa728ee | bellard | selector &= 0xffff;
|
| 1462 | eaa728ee | bellard | cpl = env->hflags & HF_CPL_MASK; |
| 1463 | eaa728ee | bellard | if ((selector & 0xfffc) == 0) { |
| 1464 | eaa728ee | bellard | /* null selector case */
|
| 1465 | eaa728ee | bellard | if (seg_reg == R_SS
|
| 1466 | eaa728ee | bellard | #ifdef TARGET_X86_64
|
| 1467 | eaa728ee | bellard | && (!(env->hflags & HF_CS64_MASK) || cpl == 3)
|
| 1468 | eaa728ee | bellard | #endif
|
| 1469 | 20054ef0 | Blue Swirl | ) {
|
| 1470 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, 0);
|
| 1471 | 20054ef0 | Blue Swirl | } |
| 1472 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0); |
| 1473 | eaa728ee | bellard | } else {
|
| 1474 | eaa728ee | bellard | |
| 1475 | 20054ef0 | Blue Swirl | if (selector & 0x4) { |
| 1476 | eaa728ee | bellard | dt = &env->ldt; |
| 1477 | 20054ef0 | Blue Swirl | } else {
|
| 1478 | eaa728ee | bellard | dt = &env->gdt; |
| 1479 | 20054ef0 | Blue Swirl | } |
| 1480 | eaa728ee | bellard | index = selector & ~7;
|
| 1481 | 20054ef0 | Blue Swirl | if ((index + 7) > dt->limit) { |
| 1482 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1483 | 20054ef0 | Blue Swirl | } |
| 1484 | eaa728ee | bellard | ptr = dt->base + index; |
| 1485 | 329e607d | Blue Swirl | e1 = cpu_ldl_kernel(env, ptr); |
| 1486 | 329e607d | Blue Swirl | e2 = cpu_ldl_kernel(env, ptr + 4);
|
| 1487 | eaa728ee | bellard | |
| 1488 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_S_MASK)) {
|
| 1489 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1490 | 20054ef0 | Blue Swirl | } |
| 1491 | eaa728ee | bellard | rpl = selector & 3;
|
| 1492 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 1493 | eaa728ee | bellard | if (seg_reg == R_SS) {
|
| 1494 | eaa728ee | bellard | /* must be writable segment */
|
| 1495 | 20054ef0 | Blue Swirl | if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
|
| 1496 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1497 | 20054ef0 | Blue Swirl | } |
| 1498 | 20054ef0 | Blue Swirl | if (rpl != cpl || dpl != cpl) {
|
| 1499 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1500 | 20054ef0 | Blue Swirl | } |
| 1501 | eaa728ee | bellard | } else {
|
| 1502 | eaa728ee | bellard | /* must be readable segment */
|
| 1503 | 20054ef0 | Blue Swirl | if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK) {
|
| 1504 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1505 | 20054ef0 | Blue Swirl | } |
| 1506 | eaa728ee | bellard | |
| 1507 | eaa728ee | bellard | if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
|
| 1508 | eaa728ee | bellard | /* if not conforming code, test rights */
|
| 1509 | 20054ef0 | Blue Swirl | if (dpl < cpl || dpl < rpl) {
|
| 1510 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1511 | 20054ef0 | Blue Swirl | } |
| 1512 | eaa728ee | bellard | } |
| 1513 | eaa728ee | bellard | } |
| 1514 | eaa728ee | bellard | |
| 1515 | eaa728ee | bellard | if (!(e2 & DESC_P_MASK)) {
|
| 1516 | 20054ef0 | Blue Swirl | if (seg_reg == R_SS) {
|
| 1517 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0C_STACK, selector & 0xfffc);
|
| 1518 | 20054ef0 | Blue Swirl | } else {
|
| 1519 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
| 1520 | 20054ef0 | Blue Swirl | } |
| 1521 | eaa728ee | bellard | } |
| 1522 | eaa728ee | bellard | |
| 1523 | eaa728ee | bellard | /* set the access bit if not already set */
|
| 1524 | eaa728ee | bellard | if (!(e2 & DESC_A_MASK)) {
|
| 1525 | eaa728ee | bellard | e2 |= DESC_A_MASK; |
| 1526 | 329e607d | Blue Swirl | cpu_stl_kernel(env, ptr + 4, e2);
|
| 1527 | eaa728ee | bellard | } |
| 1528 | eaa728ee | bellard | |
| 1529 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, seg_reg, selector, |
| 1530 | eaa728ee | bellard | get_seg_base(e1, e2), |
| 1531 | eaa728ee | bellard | get_seg_limit(e1, e2), |
| 1532 | eaa728ee | bellard | e2); |
| 1533 | eaa728ee | bellard | #if 0
|
| 1534 | 93fcfe39 | aliguori | qemu_log("load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
|
| 1535 | eaa728ee | bellard | selector, (unsigned long)sc->base, sc->limit, sc->flags);
|
| 1536 | eaa728ee | bellard | #endif
|
| 1537 | eaa728ee | bellard | } |
| 1538 | eaa728ee | bellard | } |
| 1539 | eaa728ee | bellard | |
| 1540 | eaa728ee | bellard | /* protected mode jump */
|
| 1541 | 2999a0b2 | Blue Swirl | void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip, |
| 1542 | eaa728ee | bellard | int next_eip_addend)
|
| 1543 | eaa728ee | bellard | {
|
| 1544 | eaa728ee | bellard | int gate_cs, type;
|
| 1545 | eaa728ee | bellard | uint32_t e1, e2, cpl, dpl, rpl, limit; |
| 1546 | eaa728ee | bellard | target_ulong next_eip; |
| 1547 | eaa728ee | bellard | |
| 1548 | 20054ef0 | Blue Swirl | if ((new_cs & 0xfffc) == 0) { |
| 1549 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, 0);
|
| 1550 | 20054ef0 | Blue Swirl | } |
| 1551 | 2999a0b2 | Blue Swirl | if (load_segment(env, &e1, &e2, new_cs) != 0) { |
| 1552 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1553 | 20054ef0 | Blue Swirl | } |
| 1554 | eaa728ee | bellard | cpl = env->hflags & HF_CPL_MASK; |
| 1555 | eaa728ee | bellard | if (e2 & DESC_S_MASK) {
|
| 1556 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_CS_MASK)) {
|
| 1557 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1558 | 20054ef0 | Blue Swirl | } |
| 1559 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 1560 | eaa728ee | bellard | if (e2 & DESC_C_MASK) {
|
| 1561 | eaa728ee | bellard | /* conforming code segment */
|
| 1562 | 20054ef0 | Blue Swirl | if (dpl > cpl) {
|
| 1563 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1564 | 20054ef0 | Blue Swirl | } |
| 1565 | eaa728ee | bellard | } else {
|
| 1566 | eaa728ee | bellard | /* non conforming code segment */
|
| 1567 | eaa728ee | bellard | rpl = new_cs & 3;
|
| 1568 | 20054ef0 | Blue Swirl | if (rpl > cpl) {
|
| 1569 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1570 | 20054ef0 | Blue Swirl | } |
| 1571 | 20054ef0 | Blue Swirl | if (dpl != cpl) {
|
| 1572 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1573 | 20054ef0 | Blue Swirl | } |
| 1574 | eaa728ee | bellard | } |
| 1575 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
|
| 1576 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
|
| 1577 | 20054ef0 | Blue Swirl | } |
| 1578 | eaa728ee | bellard | limit = get_seg_limit(e1, e2); |
| 1579 | eaa728ee | bellard | if (new_eip > limit &&
|
| 1580 | 20054ef0 | Blue Swirl | !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK)) {
|
| 1581 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1582 | 20054ef0 | Blue Swirl | } |
| 1583 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
|
| 1584 | eaa728ee | bellard | get_seg_base(e1, e2), limit, e2); |
| 1585 | eaa728ee | bellard | EIP = new_eip; |
| 1586 | eaa728ee | bellard | } else {
|
| 1587 | eaa728ee | bellard | /* jump to call or task gate */
|
| 1588 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 1589 | eaa728ee | bellard | rpl = new_cs & 3;
|
| 1590 | eaa728ee | bellard | cpl = env->hflags & HF_CPL_MASK; |
| 1591 | eaa728ee | bellard | type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
|
| 1592 | 20054ef0 | Blue Swirl | switch (type) {
|
| 1593 | eaa728ee | bellard | case 1: /* 286 TSS */ |
| 1594 | eaa728ee | bellard | case 9: /* 386 TSS */ |
| 1595 | eaa728ee | bellard | case 5: /* task gate */ |
| 1596 | 20054ef0 | Blue Swirl | if (dpl < cpl || dpl < rpl) {
|
| 1597 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1598 | 20054ef0 | Blue Swirl | } |
| 1599 | eaa728ee | bellard | next_eip = env->eip + next_eip_addend; |
| 1600 | 2999a0b2 | Blue Swirl | switch_tss(env, new_cs, e1, e2, SWITCH_TSS_JMP, next_eip); |
| 1601 | eaa728ee | bellard | CC_OP = CC_OP_EFLAGS; |
| 1602 | eaa728ee | bellard | break;
|
| 1603 | eaa728ee | bellard | case 4: /* 286 call gate */ |
| 1604 | eaa728ee | bellard | case 12: /* 386 call gate */ |
| 1605 | 20054ef0 | Blue Swirl | if ((dpl < cpl) || (dpl < rpl)) {
|
| 1606 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1607 | 20054ef0 | Blue Swirl | } |
| 1608 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
|
| 1609 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
|
| 1610 | 20054ef0 | Blue Swirl | } |
| 1611 | eaa728ee | bellard | gate_cs = e1 >> 16;
|
| 1612 | eaa728ee | bellard | new_eip = (e1 & 0xffff);
|
| 1613 | 20054ef0 | Blue Swirl | if (type == 12) { |
| 1614 | eaa728ee | bellard | new_eip |= (e2 & 0xffff0000);
|
| 1615 | 20054ef0 | Blue Swirl | } |
| 1616 | 2999a0b2 | Blue Swirl | if (load_segment(env, &e1, &e2, gate_cs) != 0) { |
| 1617 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
|
| 1618 | 20054ef0 | Blue Swirl | } |
| 1619 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 1620 | eaa728ee | bellard | /* must be code segment */
|
| 1621 | eaa728ee | bellard | if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
|
| 1622 | 20054ef0 | Blue Swirl | (DESC_S_MASK | DESC_CS_MASK))) {
|
| 1623 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
|
| 1624 | 20054ef0 | Blue Swirl | } |
| 1625 | eaa728ee | bellard | if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
|
| 1626 | 20054ef0 | Blue Swirl | (!(e2 & DESC_C_MASK) && (dpl != cpl))) {
|
| 1627 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
|
| 1628 | 20054ef0 | Blue Swirl | } |
| 1629 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
|
| 1630 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
|
| 1631 | 20054ef0 | Blue Swirl | } |
| 1632 | eaa728ee | bellard | limit = get_seg_limit(e1, e2); |
| 1633 | 20054ef0 | Blue Swirl | if (new_eip > limit) {
|
| 1634 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, 0);
|
| 1635 | 20054ef0 | Blue Swirl | } |
| 1636 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
|
| 1637 | eaa728ee | bellard | get_seg_base(e1, e2), limit, e2); |
| 1638 | eaa728ee | bellard | EIP = new_eip; |
| 1639 | eaa728ee | bellard | break;
|
| 1640 | eaa728ee | bellard | default:
|
| 1641 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1642 | eaa728ee | bellard | break;
|
| 1643 | eaa728ee | bellard | } |
| 1644 | eaa728ee | bellard | } |
| 1645 | eaa728ee | bellard | } |
| 1646 | eaa728ee | bellard | |
| 1647 | eaa728ee | bellard | /* real mode call */
|
| 1648 | 2999a0b2 | Blue Swirl | void helper_lcall_real(CPUX86State *env, int new_cs, target_ulong new_eip1, |
| 1649 | eaa728ee | bellard | int shift, int next_eip) |
| 1650 | eaa728ee | bellard | {
|
| 1651 | eaa728ee | bellard | int new_eip;
|
| 1652 | eaa728ee | bellard | uint32_t esp, esp_mask; |
| 1653 | eaa728ee | bellard | target_ulong ssp; |
| 1654 | eaa728ee | bellard | |
| 1655 | eaa728ee | bellard | new_eip = new_eip1; |
| 1656 | eaa728ee | bellard | esp = ESP; |
| 1657 | eaa728ee | bellard | esp_mask = get_sp_mask(env->segs[R_SS].flags); |
| 1658 | eaa728ee | bellard | ssp = env->segs[R_SS].base; |
| 1659 | eaa728ee | bellard | if (shift) {
|
| 1660 | eaa728ee | bellard | PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector); |
| 1661 | eaa728ee | bellard | PUSHL(ssp, esp, esp_mask, next_eip); |
| 1662 | eaa728ee | bellard | } else {
|
| 1663 | eaa728ee | bellard | PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector); |
| 1664 | eaa728ee | bellard | PUSHW(ssp, esp, esp_mask, next_eip); |
| 1665 | eaa728ee | bellard | } |
| 1666 | eaa728ee | bellard | |
| 1667 | eaa728ee | bellard | SET_ESP(esp, esp_mask); |
| 1668 | eaa728ee | bellard | env->eip = new_eip; |
| 1669 | eaa728ee | bellard | env->segs[R_CS].selector = new_cs; |
| 1670 | eaa728ee | bellard | env->segs[R_CS].base = (new_cs << 4);
|
| 1671 | eaa728ee | bellard | } |
| 1672 | eaa728ee | bellard | |
| 1673 | eaa728ee | bellard | /* protected mode call */
|
| 1674 | 2999a0b2 | Blue Swirl | void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip, |
| 1675 | eaa728ee | bellard | int shift, int next_eip_addend) |
| 1676 | eaa728ee | bellard | {
|
| 1677 | eaa728ee | bellard | int new_stack, i;
|
| 1678 | eaa728ee | bellard | uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count; |
| 1679 | 1c918eba | blueswir1 | uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, sp, type, ss_dpl, sp_mask; |
| 1680 | eaa728ee | bellard | uint32_t val, limit, old_sp_mask; |
| 1681 | eaa728ee | bellard | target_ulong ssp, old_ssp, next_eip; |
| 1682 | eaa728ee | bellard | |
| 1683 | eaa728ee | bellard | next_eip = env->eip + next_eip_addend; |
| 1684 | d12d51d5 | aliguori | LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift);
|
| 1685 | d12d51d5 | aliguori | LOG_PCALL_STATE(env); |
| 1686 | 20054ef0 | Blue Swirl | if ((new_cs & 0xfffc) == 0) { |
| 1687 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, 0);
|
| 1688 | 20054ef0 | Blue Swirl | } |
| 1689 | 2999a0b2 | Blue Swirl | if (load_segment(env, &e1, &e2, new_cs) != 0) { |
| 1690 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1691 | 20054ef0 | Blue Swirl | } |
| 1692 | eaa728ee | bellard | cpl = env->hflags & HF_CPL_MASK; |
| 1693 | d12d51d5 | aliguori | LOG_PCALL("desc=%08x:%08x\n", e1, e2);
|
| 1694 | eaa728ee | bellard | if (e2 & DESC_S_MASK) {
|
| 1695 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_CS_MASK)) {
|
| 1696 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1697 | 20054ef0 | Blue Swirl | } |
| 1698 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 1699 | eaa728ee | bellard | if (e2 & DESC_C_MASK) {
|
| 1700 | eaa728ee | bellard | /* conforming code segment */
|
| 1701 | 20054ef0 | Blue Swirl | if (dpl > cpl) {
|
| 1702 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1703 | 20054ef0 | Blue Swirl | } |
| 1704 | eaa728ee | bellard | } else {
|
| 1705 | eaa728ee | bellard | /* non conforming code segment */
|
| 1706 | eaa728ee | bellard | rpl = new_cs & 3;
|
| 1707 | 20054ef0 | Blue Swirl | if (rpl > cpl) {
|
| 1708 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1709 | 20054ef0 | Blue Swirl | } |
| 1710 | 20054ef0 | Blue Swirl | if (dpl != cpl) {
|
| 1711 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1712 | 20054ef0 | Blue Swirl | } |
| 1713 | eaa728ee | bellard | } |
| 1714 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
|
| 1715 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
|
| 1716 | 20054ef0 | Blue Swirl | } |
| 1717 | eaa728ee | bellard | |
| 1718 | eaa728ee | bellard | #ifdef TARGET_X86_64
|
| 1719 | eaa728ee | bellard | /* XXX: check 16/32 bit cases in long mode */
|
| 1720 | eaa728ee | bellard | if (shift == 2) { |
| 1721 | eaa728ee | bellard | target_ulong rsp; |
| 1722 | 20054ef0 | Blue Swirl | |
| 1723 | eaa728ee | bellard | /* 64 bit case */
|
| 1724 | eaa728ee | bellard | rsp = ESP; |
| 1725 | eaa728ee | bellard | PUSHQ(rsp, env->segs[R_CS].selector); |
| 1726 | eaa728ee | bellard | PUSHQ(rsp, next_eip); |
| 1727 | eaa728ee | bellard | /* from this point, not restartable */
|
| 1728 | eaa728ee | bellard | ESP = rsp; |
| 1729 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
|
| 1730 | eaa728ee | bellard | get_seg_base(e1, e2), |
| 1731 | eaa728ee | bellard | get_seg_limit(e1, e2), e2); |
| 1732 | eaa728ee | bellard | EIP = new_eip; |
| 1733 | eaa728ee | bellard | } else
|
| 1734 | eaa728ee | bellard | #endif
|
| 1735 | eaa728ee | bellard | {
|
| 1736 | eaa728ee | bellard | sp = ESP; |
| 1737 | eaa728ee | bellard | sp_mask = get_sp_mask(env->segs[R_SS].flags); |
| 1738 | eaa728ee | bellard | ssp = env->segs[R_SS].base; |
| 1739 | eaa728ee | bellard | if (shift) {
|
| 1740 | eaa728ee | bellard | PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector); |
| 1741 | eaa728ee | bellard | PUSHL(ssp, sp, sp_mask, next_eip); |
| 1742 | eaa728ee | bellard | } else {
|
| 1743 | eaa728ee | bellard | PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector); |
| 1744 | eaa728ee | bellard | PUSHW(ssp, sp, sp_mask, next_eip); |
| 1745 | eaa728ee | bellard | } |
| 1746 | eaa728ee | bellard | |
| 1747 | eaa728ee | bellard | limit = get_seg_limit(e1, e2); |
| 1748 | 20054ef0 | Blue Swirl | if (new_eip > limit) {
|
| 1749 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1750 | 20054ef0 | Blue Swirl | } |
| 1751 | eaa728ee | bellard | /* from this point, not restartable */
|
| 1752 | eaa728ee | bellard | SET_ESP(sp, sp_mask); |
| 1753 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
|
| 1754 | eaa728ee | bellard | get_seg_base(e1, e2), limit, e2); |
| 1755 | eaa728ee | bellard | EIP = new_eip; |
| 1756 | eaa728ee | bellard | } |
| 1757 | eaa728ee | bellard | } else {
|
| 1758 | eaa728ee | bellard | /* check gate type */
|
| 1759 | eaa728ee | bellard | type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
|
| 1760 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 1761 | eaa728ee | bellard | rpl = new_cs & 3;
|
| 1762 | 20054ef0 | Blue Swirl | switch (type) {
|
| 1763 | eaa728ee | bellard | case 1: /* available 286 TSS */ |
| 1764 | eaa728ee | bellard | case 9: /* available 386 TSS */ |
| 1765 | eaa728ee | bellard | case 5: /* task gate */ |
| 1766 | 20054ef0 | Blue Swirl | if (dpl < cpl || dpl < rpl) {
|
| 1767 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1768 | 20054ef0 | Blue Swirl | } |
| 1769 | 2999a0b2 | Blue Swirl | switch_tss(env, new_cs, e1, e2, SWITCH_TSS_CALL, next_eip); |
| 1770 | eaa728ee | bellard | CC_OP = CC_OP_EFLAGS; |
| 1771 | eaa728ee | bellard | return;
|
| 1772 | eaa728ee | bellard | case 4: /* 286 call gate */ |
| 1773 | eaa728ee | bellard | case 12: /* 386 call gate */ |
| 1774 | eaa728ee | bellard | break;
|
| 1775 | eaa728ee | bellard | default:
|
| 1776 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1777 | eaa728ee | bellard | break;
|
| 1778 | eaa728ee | bellard | } |
| 1779 | eaa728ee | bellard | shift = type >> 3;
|
| 1780 | eaa728ee | bellard | |
| 1781 | 20054ef0 | Blue Swirl | if (dpl < cpl || dpl < rpl) {
|
| 1782 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 1783 | 20054ef0 | Blue Swirl | } |
| 1784 | eaa728ee | bellard | /* check valid bit */
|
| 1785 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
|
| 1786 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
|
| 1787 | 20054ef0 | Blue Swirl | } |
| 1788 | eaa728ee | bellard | selector = e1 >> 16;
|
| 1789 | eaa728ee | bellard | offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff); |
| 1790 | eaa728ee | bellard | param_count = e2 & 0x1f;
|
| 1791 | 20054ef0 | Blue Swirl | if ((selector & 0xfffc) == 0) { |
| 1792 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, 0);
|
| 1793 | 20054ef0 | Blue Swirl | } |
| 1794 | eaa728ee | bellard | |
| 1795 | 2999a0b2 | Blue Swirl | if (load_segment(env, &e1, &e2, selector) != 0) { |
| 1796 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1797 | 20054ef0 | Blue Swirl | } |
| 1798 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
|
| 1799 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1800 | 20054ef0 | Blue Swirl | } |
| 1801 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 1802 | 20054ef0 | Blue Swirl | if (dpl > cpl) {
|
| 1803 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
| 1804 | 20054ef0 | Blue Swirl | } |
| 1805 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
|
| 1806 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
| 1807 | 20054ef0 | Blue Swirl | } |
| 1808 | eaa728ee | bellard | |
| 1809 | eaa728ee | bellard | if (!(e2 & DESC_C_MASK) && dpl < cpl) {
|
| 1810 | eaa728ee | bellard | /* to inner privilege */
|
| 1811 | 2999a0b2 | Blue Swirl | get_ss_esp_from_tss(env, &ss, &sp, dpl); |
| 1812 | 20054ef0 | Blue Swirl | LOG_PCALL("new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx
|
| 1813 | 20054ef0 | Blue Swirl | "\n",
|
| 1814 | 20054ef0 | Blue Swirl | ss, sp, param_count, ESP); |
| 1815 | 20054ef0 | Blue Swirl | if ((ss & 0xfffc) == 0) { |
| 1816 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
| 1817 | 20054ef0 | Blue Swirl | } |
| 1818 | 20054ef0 | Blue Swirl | if ((ss & 3) != dpl) { |
| 1819 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
| 1820 | 20054ef0 | Blue Swirl | } |
| 1821 | 2999a0b2 | Blue Swirl | if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) { |
| 1822 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
| 1823 | 20054ef0 | Blue Swirl | } |
| 1824 | eaa728ee | bellard | ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
|
| 1825 | 20054ef0 | Blue Swirl | if (ss_dpl != dpl) {
|
| 1826 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
| 1827 | 20054ef0 | Blue Swirl | } |
| 1828 | eaa728ee | bellard | if (!(ss_e2 & DESC_S_MASK) ||
|
| 1829 | eaa728ee | bellard | (ss_e2 & DESC_CS_MASK) || |
| 1830 | 20054ef0 | Blue Swirl | !(ss_e2 & DESC_W_MASK)) {
|
| 1831 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
| 1832 | 20054ef0 | Blue Swirl | } |
| 1833 | 20054ef0 | Blue Swirl | if (!(ss_e2 & DESC_P_MASK)) {
|
| 1834 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
| 1835 | 20054ef0 | Blue Swirl | } |
| 1836 | eaa728ee | bellard | |
| 1837 | 20054ef0 | Blue Swirl | /* push_size = ((param_count * 2) + 8) << shift; */
|
| 1838 | eaa728ee | bellard | |
| 1839 | eaa728ee | bellard | old_sp_mask = get_sp_mask(env->segs[R_SS].flags); |
| 1840 | eaa728ee | bellard | old_ssp = env->segs[R_SS].base; |
| 1841 | eaa728ee | bellard | |
| 1842 | eaa728ee | bellard | sp_mask = get_sp_mask(ss_e2); |
| 1843 | eaa728ee | bellard | ssp = get_seg_base(ss_e1, ss_e2); |
| 1844 | eaa728ee | bellard | if (shift) {
|
| 1845 | eaa728ee | bellard | PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector); |
| 1846 | eaa728ee | bellard | PUSHL(ssp, sp, sp_mask, ESP); |
| 1847 | 20054ef0 | Blue Swirl | for (i = param_count - 1; i >= 0; i--) { |
| 1848 | 329e607d | Blue Swirl | val = cpu_ldl_kernel(env, old_ssp + ((ESP + i * 4) &
|
| 1849 | 329e607d | Blue Swirl | old_sp_mask)); |
| 1850 | eaa728ee | bellard | PUSHL(ssp, sp, sp_mask, val); |
| 1851 | eaa728ee | bellard | } |
| 1852 | eaa728ee | bellard | } else {
|
| 1853 | eaa728ee | bellard | PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector); |
| 1854 | eaa728ee | bellard | PUSHW(ssp, sp, sp_mask, ESP); |
| 1855 | 20054ef0 | Blue Swirl | for (i = param_count - 1; i >= 0; i--) { |
| 1856 | 329e607d | Blue Swirl | val = cpu_lduw_kernel(env, old_ssp + ((ESP + i * 2) &
|
| 1857 | 329e607d | Blue Swirl | old_sp_mask)); |
| 1858 | eaa728ee | bellard | PUSHW(ssp, sp, sp_mask, val); |
| 1859 | eaa728ee | bellard | } |
| 1860 | eaa728ee | bellard | } |
| 1861 | eaa728ee | bellard | new_stack = 1;
|
| 1862 | eaa728ee | bellard | } else {
|
| 1863 | eaa728ee | bellard | /* to same privilege */
|
| 1864 | eaa728ee | bellard | sp = ESP; |
| 1865 | eaa728ee | bellard | sp_mask = get_sp_mask(env->segs[R_SS].flags); |
| 1866 | eaa728ee | bellard | ssp = env->segs[R_SS].base; |
| 1867 | 20054ef0 | Blue Swirl | /* push_size = (4 << shift); */
|
| 1868 | eaa728ee | bellard | new_stack = 0;
|
| 1869 | eaa728ee | bellard | } |
| 1870 | eaa728ee | bellard | |
| 1871 | eaa728ee | bellard | if (shift) {
|
| 1872 | eaa728ee | bellard | PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector); |
| 1873 | eaa728ee | bellard | PUSHL(ssp, sp, sp_mask, next_eip); |
| 1874 | eaa728ee | bellard | } else {
|
| 1875 | eaa728ee | bellard | PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector); |
| 1876 | eaa728ee | bellard | PUSHW(ssp, sp, sp_mask, next_eip); |
| 1877 | eaa728ee | bellard | } |
| 1878 | eaa728ee | bellard | |
| 1879 | eaa728ee | bellard | /* from this point, not restartable */
|
| 1880 | eaa728ee | bellard | |
| 1881 | eaa728ee | bellard | if (new_stack) {
|
| 1882 | eaa728ee | bellard | ss = (ss & ~3) | dpl;
|
| 1883 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_SS, ss, |
| 1884 | eaa728ee | bellard | ssp, |
| 1885 | eaa728ee | bellard | get_seg_limit(ss_e1, ss_e2), |
| 1886 | eaa728ee | bellard | ss_e2); |
| 1887 | eaa728ee | bellard | } |
| 1888 | eaa728ee | bellard | |
| 1889 | eaa728ee | bellard | selector = (selector & ~3) | dpl;
|
| 1890 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_CS, selector, |
| 1891 | eaa728ee | bellard | get_seg_base(e1, e2), |
| 1892 | eaa728ee | bellard | get_seg_limit(e1, e2), |
| 1893 | eaa728ee | bellard | e2); |
| 1894 | eaa728ee | bellard | cpu_x86_set_cpl(env, dpl); |
| 1895 | eaa728ee | bellard | SET_ESP(sp, sp_mask); |
| 1896 | eaa728ee | bellard | EIP = offset; |
| 1897 | eaa728ee | bellard | } |
| 1898 | eaa728ee | bellard | } |
| 1899 | eaa728ee | bellard | |
| 1900 | eaa728ee | bellard | /* real and vm86 mode iret */
|
| 1901 | 2999a0b2 | Blue Swirl | void helper_iret_real(CPUX86State *env, int shift) |
| 1902 | eaa728ee | bellard | {
|
| 1903 | eaa728ee | bellard | uint32_t sp, new_cs, new_eip, new_eflags, sp_mask; |
| 1904 | eaa728ee | bellard | target_ulong ssp; |
| 1905 | eaa728ee | bellard | int eflags_mask;
|
| 1906 | eaa728ee | bellard | |
| 1907 | 20054ef0 | Blue Swirl | sp_mask = 0xffff; /* XXXX: use SS segment size? */ |
| 1908 | eaa728ee | bellard | sp = ESP; |
| 1909 | eaa728ee | bellard | ssp = env->segs[R_SS].base; |
| 1910 | eaa728ee | bellard | if (shift == 1) { |
| 1911 | eaa728ee | bellard | /* 32 bits */
|
| 1912 | eaa728ee | bellard | POPL(ssp, sp, sp_mask, new_eip); |
| 1913 | eaa728ee | bellard | POPL(ssp, sp, sp_mask, new_cs); |
| 1914 | eaa728ee | bellard | new_cs &= 0xffff;
|
| 1915 | eaa728ee | bellard | POPL(ssp, sp, sp_mask, new_eflags); |
| 1916 | eaa728ee | bellard | } else {
|
| 1917 | eaa728ee | bellard | /* 16 bits */
|
| 1918 | eaa728ee | bellard | POPW(ssp, sp, sp_mask, new_eip); |
| 1919 | eaa728ee | bellard | POPW(ssp, sp, sp_mask, new_cs); |
| 1920 | eaa728ee | bellard | POPW(ssp, sp, sp_mask, new_eflags); |
| 1921 | eaa728ee | bellard | } |
| 1922 | eaa728ee | bellard | ESP = (ESP & ~sp_mask) | (sp & sp_mask); |
| 1923 | bdadc0b5 | malc | env->segs[R_CS].selector = new_cs; |
| 1924 | bdadc0b5 | malc | env->segs[R_CS].base = (new_cs << 4);
|
| 1925 | eaa728ee | bellard | env->eip = new_eip; |
| 1926 | 20054ef0 | Blue Swirl | if (env->eflags & VM_MASK) {
|
| 1927 | 20054ef0 | Blue Swirl | eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK | |
| 1928 | 20054ef0 | Blue Swirl | NT_MASK; |
| 1929 | 20054ef0 | Blue Swirl | } else {
|
| 1930 | 20054ef0 | Blue Swirl | eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK | |
| 1931 | 20054ef0 | Blue Swirl | RF_MASK | NT_MASK; |
| 1932 | 20054ef0 | Blue Swirl | } |
| 1933 | 20054ef0 | Blue Swirl | if (shift == 0) { |
| 1934 | eaa728ee | bellard | eflags_mask &= 0xffff;
|
| 1935 | 20054ef0 | Blue Swirl | } |
| 1936 | 997ff0d9 | Blue Swirl | cpu_load_eflags(env, new_eflags, eflags_mask); |
| 1937 | db620f46 | bellard | env->hflags2 &= ~HF2_NMI_MASK; |
| 1938 | eaa728ee | bellard | } |
| 1939 | eaa728ee | bellard | |
| 1940 | 2999a0b2 | Blue Swirl | static inline void validate_seg(CPUX86State *env, int seg_reg, int cpl) |
| 1941 | eaa728ee | bellard | {
|
| 1942 | eaa728ee | bellard | int dpl;
|
| 1943 | eaa728ee | bellard | uint32_t e2; |
| 1944 | eaa728ee | bellard | |
| 1945 | eaa728ee | bellard | /* XXX: on x86_64, we do not want to nullify FS and GS because
|
| 1946 | eaa728ee | bellard | they may still contain a valid base. I would be interested to
|
| 1947 | eaa728ee | bellard | know how a real x86_64 CPU behaves */
|
| 1948 | eaa728ee | bellard | if ((seg_reg == R_FS || seg_reg == R_GS) &&
|
| 1949 | 20054ef0 | Blue Swirl | (env->segs[seg_reg].selector & 0xfffc) == 0) { |
| 1950 | eaa728ee | bellard | return;
|
| 1951 | 20054ef0 | Blue Swirl | } |
| 1952 | eaa728ee | bellard | |
| 1953 | eaa728ee | bellard | e2 = env->segs[seg_reg].flags; |
| 1954 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 1955 | eaa728ee | bellard | if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
|
| 1956 | eaa728ee | bellard | /* data or non conforming code segment */
|
| 1957 | eaa728ee | bellard | if (dpl < cpl) {
|
| 1958 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0); |
| 1959 | eaa728ee | bellard | } |
| 1960 | eaa728ee | bellard | } |
| 1961 | eaa728ee | bellard | } |
| 1962 | eaa728ee | bellard | |
| 1963 | eaa728ee | bellard | /* protected mode iret */
|
| 1964 | 2999a0b2 | Blue Swirl | static inline void helper_ret_protected(CPUX86State *env, int shift, |
| 1965 | 2999a0b2 | Blue Swirl | int is_iret, int addend) |
| 1966 | eaa728ee | bellard | {
|
| 1967 | eaa728ee | bellard | uint32_t new_cs, new_eflags, new_ss; |
| 1968 | eaa728ee | bellard | uint32_t new_es, new_ds, new_fs, new_gs; |
| 1969 | eaa728ee | bellard | uint32_t e1, e2, ss_e1, ss_e2; |
| 1970 | eaa728ee | bellard | int cpl, dpl, rpl, eflags_mask, iopl;
|
| 1971 | eaa728ee | bellard | target_ulong ssp, sp, new_eip, new_esp, sp_mask; |
| 1972 | eaa728ee | bellard | |
| 1973 | eaa728ee | bellard | #ifdef TARGET_X86_64
|
| 1974 | 20054ef0 | Blue Swirl | if (shift == 2) { |
| 1975 | eaa728ee | bellard | sp_mask = -1;
|
| 1976 | 20054ef0 | Blue Swirl | } else
|
| 1977 | eaa728ee | bellard | #endif
|
| 1978 | 20054ef0 | Blue Swirl | {
|
| 1979 | eaa728ee | bellard | sp_mask = get_sp_mask(env->segs[R_SS].flags); |
| 1980 | 20054ef0 | Blue Swirl | } |
| 1981 | eaa728ee | bellard | sp = ESP; |
| 1982 | eaa728ee | bellard | ssp = env->segs[R_SS].base; |
| 1983 | eaa728ee | bellard | new_eflags = 0; /* avoid warning */ |
| 1984 | eaa728ee | bellard | #ifdef TARGET_X86_64
|
| 1985 | eaa728ee | bellard | if (shift == 2) { |
| 1986 | eaa728ee | bellard | POPQ(sp, new_eip); |
| 1987 | eaa728ee | bellard | POPQ(sp, new_cs); |
| 1988 | eaa728ee | bellard | new_cs &= 0xffff;
|
| 1989 | eaa728ee | bellard | if (is_iret) {
|
| 1990 | eaa728ee | bellard | POPQ(sp, new_eflags); |
| 1991 | eaa728ee | bellard | } |
| 1992 | eaa728ee | bellard | } else
|
| 1993 | eaa728ee | bellard | #endif
|
| 1994 | 20054ef0 | Blue Swirl | {
|
| 1995 | 20054ef0 | Blue Swirl | if (shift == 1) { |
| 1996 | 20054ef0 | Blue Swirl | /* 32 bits */
|
| 1997 | 20054ef0 | Blue Swirl | POPL(ssp, sp, sp_mask, new_eip); |
| 1998 | 20054ef0 | Blue Swirl | POPL(ssp, sp, sp_mask, new_cs); |
| 1999 | 20054ef0 | Blue Swirl | new_cs &= 0xffff;
|
| 2000 | 20054ef0 | Blue Swirl | if (is_iret) {
|
| 2001 | 20054ef0 | Blue Swirl | POPL(ssp, sp, sp_mask, new_eflags); |
| 2002 | 20054ef0 | Blue Swirl | if (new_eflags & VM_MASK) {
|
| 2003 | 20054ef0 | Blue Swirl | goto return_to_vm86;
|
| 2004 | 20054ef0 | Blue Swirl | } |
| 2005 | 20054ef0 | Blue Swirl | } |
| 2006 | 20054ef0 | Blue Swirl | } else {
|
| 2007 | 20054ef0 | Blue Swirl | /* 16 bits */
|
| 2008 | 20054ef0 | Blue Swirl | POPW(ssp, sp, sp_mask, new_eip); |
| 2009 | 20054ef0 | Blue Swirl | POPW(ssp, sp, sp_mask, new_cs); |
| 2010 | 20054ef0 | Blue Swirl | if (is_iret) {
|
| 2011 | 20054ef0 | Blue Swirl | POPW(ssp, sp, sp_mask, new_eflags); |
| 2012 | 20054ef0 | Blue Swirl | } |
| 2013 | eaa728ee | bellard | } |
| 2014 | eaa728ee | bellard | } |
| 2015 | d12d51d5 | aliguori | LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n", |
| 2016 | d12d51d5 | aliguori | new_cs, new_eip, shift, addend); |
| 2017 | d12d51d5 | aliguori | LOG_PCALL_STATE(env); |
| 2018 | 20054ef0 | Blue Swirl | if ((new_cs & 0xfffc) == 0) { |
| 2019 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 2020 | 20054ef0 | Blue Swirl | } |
| 2021 | 2999a0b2 | Blue Swirl | if (load_segment(env, &e1, &e2, new_cs) != 0) { |
| 2022 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 2023 | 20054ef0 | Blue Swirl | } |
| 2024 | eaa728ee | bellard | if (!(e2 & DESC_S_MASK) ||
|
| 2025 | 20054ef0 | Blue Swirl | !(e2 & DESC_CS_MASK)) {
|
| 2026 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 2027 | 20054ef0 | Blue Swirl | } |
| 2028 | eaa728ee | bellard | cpl = env->hflags & HF_CPL_MASK; |
| 2029 | eaa728ee | bellard | rpl = new_cs & 3;
|
| 2030 | 20054ef0 | Blue Swirl | if (rpl < cpl) {
|
| 2031 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 2032 | 20054ef0 | Blue Swirl | } |
| 2033 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 2034 | eaa728ee | bellard | if (e2 & DESC_C_MASK) {
|
| 2035 | 20054ef0 | Blue Swirl | if (dpl > rpl) {
|
| 2036 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 2037 | 20054ef0 | Blue Swirl | } |
| 2038 | eaa728ee | bellard | } else {
|
| 2039 | 20054ef0 | Blue Swirl | if (dpl != rpl) {
|
| 2040 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
| 2041 | 20054ef0 | Blue Swirl | } |
| 2042 | eaa728ee | bellard | } |
| 2043 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_P_MASK)) {
|
| 2044 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
|
| 2045 | 20054ef0 | Blue Swirl | } |
| 2046 | eaa728ee | bellard | |
| 2047 | eaa728ee | bellard | sp += addend; |
| 2048 | eaa728ee | bellard | if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
|
| 2049 | eaa728ee | bellard | ((env->hflags & HF_CS64_MASK) && !is_iret))) {
|
| 2050 | 1235fc06 | ths | /* return to same privilege level */
|
| 2051 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_CS, new_cs, |
| 2052 | eaa728ee | bellard | get_seg_base(e1, e2), |
| 2053 | eaa728ee | bellard | get_seg_limit(e1, e2), |
| 2054 | eaa728ee | bellard | e2); |
| 2055 | eaa728ee | bellard | } else {
|
| 2056 | eaa728ee | bellard | /* return to different privilege level */
|
| 2057 | eaa728ee | bellard | #ifdef TARGET_X86_64
|
| 2058 | eaa728ee | bellard | if (shift == 2) { |
| 2059 | eaa728ee | bellard | POPQ(sp, new_esp); |
| 2060 | eaa728ee | bellard | POPQ(sp, new_ss); |
| 2061 | eaa728ee | bellard | new_ss &= 0xffff;
|
| 2062 | eaa728ee | bellard | } else
|
| 2063 | eaa728ee | bellard | #endif
|
| 2064 | 20054ef0 | Blue Swirl | {
|
| 2065 | 20054ef0 | Blue Swirl | if (shift == 1) { |
| 2066 | 20054ef0 | Blue Swirl | /* 32 bits */
|
| 2067 | 20054ef0 | Blue Swirl | POPL(ssp, sp, sp_mask, new_esp); |
| 2068 | 20054ef0 | Blue Swirl | POPL(ssp, sp, sp_mask, new_ss); |
| 2069 | 20054ef0 | Blue Swirl | new_ss &= 0xffff;
|
| 2070 | 20054ef0 | Blue Swirl | } else {
|
| 2071 | 20054ef0 | Blue Swirl | /* 16 bits */
|
| 2072 | 20054ef0 | Blue Swirl | POPW(ssp, sp, sp_mask, new_esp); |
| 2073 | 20054ef0 | Blue Swirl | POPW(ssp, sp, sp_mask, new_ss); |
| 2074 | 20054ef0 | Blue Swirl | } |
| 2075 | eaa728ee | bellard | } |
| 2076 | d12d51d5 | aliguori | LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n", |
| 2077 | 20054ef0 | Blue Swirl | new_ss, new_esp); |
| 2078 | eaa728ee | bellard | if ((new_ss & 0xfffc) == 0) { |
| 2079 | eaa728ee | bellard | #ifdef TARGET_X86_64
|
| 2080 | 20054ef0 | Blue Swirl | /* NULL ss is allowed in long mode if cpl != 3 */
|
| 2081 | 20054ef0 | Blue Swirl | /* XXX: test CS64? */
|
| 2082 | eaa728ee | bellard | if ((env->hflags & HF_LMA_MASK) && rpl != 3) { |
| 2083 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_SS, new_ss, |
| 2084 | eaa728ee | bellard | 0, 0xffffffff, |
| 2085 | eaa728ee | bellard | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 2086 | eaa728ee | bellard | DESC_S_MASK | (rpl << DESC_DPL_SHIFT) | |
| 2087 | eaa728ee | bellard | DESC_W_MASK | DESC_A_MASK); |
| 2088 | 20054ef0 | Blue Swirl | ss_e2 = DESC_B_MASK; /* XXX: should not be needed? */
|
| 2089 | eaa728ee | bellard | } else
|
| 2090 | eaa728ee | bellard | #endif
|
| 2091 | eaa728ee | bellard | {
|
| 2092 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, 0);
|
| 2093 | eaa728ee | bellard | } |
| 2094 | eaa728ee | bellard | } else {
|
| 2095 | 20054ef0 | Blue Swirl | if ((new_ss & 3) != rpl) { |
| 2096 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
|
| 2097 | 20054ef0 | Blue Swirl | } |
| 2098 | 2999a0b2 | Blue Swirl | if (load_segment(env, &ss_e1, &ss_e2, new_ss) != 0) { |
| 2099 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
|
| 2100 | 20054ef0 | Blue Swirl | } |
| 2101 | eaa728ee | bellard | if (!(ss_e2 & DESC_S_MASK) ||
|
| 2102 | eaa728ee | bellard | (ss_e2 & DESC_CS_MASK) || |
| 2103 | 20054ef0 | Blue Swirl | !(ss_e2 & DESC_W_MASK)) {
|
| 2104 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
|
| 2105 | 20054ef0 | Blue Swirl | } |
| 2106 | eaa728ee | bellard | dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
|
| 2107 | 20054ef0 | Blue Swirl | if (dpl != rpl) {
|
| 2108 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
|
| 2109 | 20054ef0 | Blue Swirl | } |
| 2110 | 20054ef0 | Blue Swirl | if (!(ss_e2 & DESC_P_MASK)) {
|
| 2111 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0B_NOSEG, new_ss & 0xfffc);
|
| 2112 | 20054ef0 | Blue Swirl | } |
| 2113 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_SS, new_ss, |
| 2114 | eaa728ee | bellard | get_seg_base(ss_e1, ss_e2), |
| 2115 | eaa728ee | bellard | get_seg_limit(ss_e1, ss_e2), |
| 2116 | eaa728ee | bellard | ss_e2); |
| 2117 | eaa728ee | bellard | } |
| 2118 | eaa728ee | bellard | |
| 2119 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_CS, new_cs, |
| 2120 | eaa728ee | bellard | get_seg_base(e1, e2), |
| 2121 | eaa728ee | bellard | get_seg_limit(e1, e2), |
| 2122 | eaa728ee | bellard | e2); |
| 2123 | eaa728ee | bellard | cpu_x86_set_cpl(env, rpl); |
| 2124 | eaa728ee | bellard | sp = new_esp; |
| 2125 | eaa728ee | bellard | #ifdef TARGET_X86_64
|
| 2126 | 20054ef0 | Blue Swirl | if (env->hflags & HF_CS64_MASK) {
|
| 2127 | eaa728ee | bellard | sp_mask = -1;
|
| 2128 | 20054ef0 | Blue Swirl | } else
|
| 2129 | eaa728ee | bellard | #endif
|
| 2130 | 20054ef0 | Blue Swirl | {
|
| 2131 | eaa728ee | bellard | sp_mask = get_sp_mask(ss_e2); |
| 2132 | 20054ef0 | Blue Swirl | } |
| 2133 | eaa728ee | bellard | |
| 2134 | eaa728ee | bellard | /* validate data segments */
|
| 2135 | 2999a0b2 | Blue Swirl | validate_seg(env, R_ES, rpl); |
| 2136 | 2999a0b2 | Blue Swirl | validate_seg(env, R_DS, rpl); |
| 2137 | 2999a0b2 | Blue Swirl | validate_seg(env, R_FS, rpl); |
| 2138 | 2999a0b2 | Blue Swirl | validate_seg(env, R_GS, rpl); |
| 2139 | eaa728ee | bellard | |
| 2140 | eaa728ee | bellard | sp += addend; |
| 2141 | eaa728ee | bellard | } |
| 2142 | eaa728ee | bellard | SET_ESP(sp, sp_mask); |
| 2143 | eaa728ee | bellard | env->eip = new_eip; |
| 2144 | eaa728ee | bellard | if (is_iret) {
|
| 2145 | eaa728ee | bellard | /* NOTE: 'cpl' is the _old_ CPL */
|
| 2146 | eaa728ee | bellard | eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK; |
| 2147 | 20054ef0 | Blue Swirl | if (cpl == 0) { |
| 2148 | eaa728ee | bellard | eflags_mask |= IOPL_MASK; |
| 2149 | 20054ef0 | Blue Swirl | } |
| 2150 | eaa728ee | bellard | iopl = (env->eflags >> IOPL_SHIFT) & 3;
|
| 2151 | 20054ef0 | Blue Swirl | if (cpl <= iopl) {
|
| 2152 | eaa728ee | bellard | eflags_mask |= IF_MASK; |
| 2153 | 20054ef0 | Blue Swirl | } |
| 2154 | 20054ef0 | Blue Swirl | if (shift == 0) { |
| 2155 | eaa728ee | bellard | eflags_mask &= 0xffff;
|
| 2156 | 20054ef0 | Blue Swirl | } |
| 2157 | 997ff0d9 | Blue Swirl | cpu_load_eflags(env, new_eflags, eflags_mask); |
| 2158 | eaa728ee | bellard | } |
| 2159 | eaa728ee | bellard | return;
|
| 2160 | eaa728ee | bellard | |
| 2161 | eaa728ee | bellard | return_to_vm86:
|
| 2162 | eaa728ee | bellard | POPL(ssp, sp, sp_mask, new_esp); |
| 2163 | eaa728ee | bellard | POPL(ssp, sp, sp_mask, new_ss); |
| 2164 | eaa728ee | bellard | POPL(ssp, sp, sp_mask, new_es); |
| 2165 | eaa728ee | bellard | POPL(ssp, sp, sp_mask, new_ds); |
| 2166 | eaa728ee | bellard | POPL(ssp, sp, sp_mask, new_fs); |
| 2167 | eaa728ee | bellard | POPL(ssp, sp, sp_mask, new_gs); |
| 2168 | eaa728ee | bellard | |
| 2169 | eaa728ee | bellard | /* modify processor state */
|
| 2170 | 997ff0d9 | Blue Swirl | cpu_load_eflags(env, new_eflags, TF_MASK | AC_MASK | ID_MASK | |
| 2171 | 997ff0d9 | Blue Swirl | IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | |
| 2172 | 997ff0d9 | Blue Swirl | VIP_MASK); |
| 2173 | 2999a0b2 | Blue Swirl | load_seg_vm(env, R_CS, new_cs & 0xffff);
|
| 2174 | eaa728ee | bellard | cpu_x86_set_cpl(env, 3);
|
| 2175 | 2999a0b2 | Blue Swirl | load_seg_vm(env, R_SS, new_ss & 0xffff);
|
| 2176 | 2999a0b2 | Blue Swirl | load_seg_vm(env, R_ES, new_es & 0xffff);
|
| 2177 | 2999a0b2 | Blue Swirl | load_seg_vm(env, R_DS, new_ds & 0xffff);
|
| 2178 | 2999a0b2 | Blue Swirl | load_seg_vm(env, R_FS, new_fs & 0xffff);
|
| 2179 | 2999a0b2 | Blue Swirl | load_seg_vm(env, R_GS, new_gs & 0xffff);
|
| 2180 | eaa728ee | bellard | |
| 2181 | eaa728ee | bellard | env->eip = new_eip & 0xffff;
|
| 2182 | eaa728ee | bellard | ESP = new_esp; |
| 2183 | eaa728ee | bellard | } |
| 2184 | eaa728ee | bellard | |
| 2185 | 2999a0b2 | Blue Swirl | void helper_iret_protected(CPUX86State *env, int shift, int next_eip) |
| 2186 | eaa728ee | bellard | {
|
| 2187 | eaa728ee | bellard | int tss_selector, type;
|
| 2188 | eaa728ee | bellard | uint32_t e1, e2; |
| 2189 | eaa728ee | bellard | |
| 2190 | eaa728ee | bellard | /* specific case for TSS */
|
| 2191 | eaa728ee | bellard | if (env->eflags & NT_MASK) {
|
| 2192 | eaa728ee | bellard | #ifdef TARGET_X86_64
|
| 2193 | 20054ef0 | Blue Swirl | if (env->hflags & HF_LMA_MASK) {
|
| 2194 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, 0);
|
| 2195 | 20054ef0 | Blue Swirl | } |
| 2196 | eaa728ee | bellard | #endif
|
| 2197 | 329e607d | Blue Swirl | tss_selector = cpu_lduw_kernel(env, env->tr.base + 0);
|
| 2198 | 20054ef0 | Blue Swirl | if (tss_selector & 4) { |
| 2199 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
|
| 2200 | 20054ef0 | Blue Swirl | } |
| 2201 | 2999a0b2 | Blue Swirl | if (load_segment(env, &e1, &e2, tss_selector) != 0) { |
| 2202 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
|
| 2203 | 20054ef0 | Blue Swirl | } |
| 2204 | eaa728ee | bellard | type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
|
| 2205 | eaa728ee | bellard | /* NOTE: we check both segment and busy TSS */
|
| 2206 | 20054ef0 | Blue Swirl | if (type != 3) { |
| 2207 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
|
| 2208 | 20054ef0 | Blue Swirl | } |
| 2209 | 2999a0b2 | Blue Swirl | switch_tss(env, tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip); |
| 2210 | eaa728ee | bellard | } else {
|
| 2211 | 2999a0b2 | Blue Swirl | helper_ret_protected(env, shift, 1, 0); |
| 2212 | eaa728ee | bellard | } |
| 2213 | db620f46 | bellard | env->hflags2 &= ~HF2_NMI_MASK; |
| 2214 | eaa728ee | bellard | } |
| 2215 | eaa728ee | bellard | |
| 2216 | 2999a0b2 | Blue Swirl | void helper_lret_protected(CPUX86State *env, int shift, int addend) |
| 2217 | eaa728ee | bellard | {
|
| 2218 | 2999a0b2 | Blue Swirl | helper_ret_protected(env, shift, 0, addend);
|
| 2219 | eaa728ee | bellard | } |
| 2220 | eaa728ee | bellard | |
| 2221 | 2999a0b2 | Blue Swirl | void helper_sysenter(CPUX86State *env)
|
| 2222 | eaa728ee | bellard | {
|
| 2223 | eaa728ee | bellard | if (env->sysenter_cs == 0) { |
| 2224 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, 0);
|
| 2225 | eaa728ee | bellard | } |
| 2226 | eaa728ee | bellard | env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK); |
| 2227 | eaa728ee | bellard | cpu_x86_set_cpl(env, 0);
|
| 2228 | 2436b61a | balrog | |
| 2229 | 2436b61a | balrog | #ifdef TARGET_X86_64
|
| 2230 | 2436b61a | balrog | if (env->hflags & HF_LMA_MASK) {
|
| 2231 | 2436b61a | balrog | cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
|
| 2232 | 2436b61a | balrog | 0, 0xffffffff, |
| 2233 | 2436b61a | balrog | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 2234 | 2436b61a | balrog | DESC_S_MASK | |
| 2235 | 20054ef0 | Blue Swirl | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
| 2236 | 20054ef0 | Blue Swirl | DESC_L_MASK); |
| 2237 | 2436b61a | balrog | } else
|
| 2238 | 2436b61a | balrog | #endif
|
| 2239 | 2436b61a | balrog | {
|
| 2240 | 2436b61a | balrog | cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
|
| 2241 | 2436b61a | balrog | 0, 0xffffffff, |
| 2242 | 2436b61a | balrog | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 2243 | 2436b61a | balrog | DESC_S_MASK | |
| 2244 | 2436b61a | balrog | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
| 2245 | 2436b61a | balrog | } |
| 2246 | eaa728ee | bellard | cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc, |
| 2247 | eaa728ee | bellard | 0, 0xffffffff, |
| 2248 | eaa728ee | bellard | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 2249 | eaa728ee | bellard | DESC_S_MASK | |
| 2250 | eaa728ee | bellard | DESC_W_MASK | DESC_A_MASK); |
| 2251 | eaa728ee | bellard | ESP = env->sysenter_esp; |
| 2252 | eaa728ee | bellard | EIP = env->sysenter_eip; |
| 2253 | eaa728ee | bellard | } |
| 2254 | eaa728ee | bellard | |
| 2255 | 2999a0b2 | Blue Swirl | void helper_sysexit(CPUX86State *env, int dflag) |
| 2256 | eaa728ee | bellard | {
|
| 2257 | eaa728ee | bellard | int cpl;
|
| 2258 | eaa728ee | bellard | |
| 2259 | eaa728ee | bellard | cpl = env->hflags & HF_CPL_MASK; |
| 2260 | eaa728ee | bellard | if (env->sysenter_cs == 0 || cpl != 0) { |
| 2261 | 77b2bc2c | Blue Swirl | raise_exception_err(env, EXCP0D_GPF, 0);
|
| 2262 | eaa728ee | bellard | } |
| 2263 | eaa728ee | bellard | cpu_x86_set_cpl(env, 3);
|
| 2264 | 2436b61a | balrog | #ifdef TARGET_X86_64
|
| 2265 | 2436b61a | balrog | if (dflag == 2) { |
| 2266 | 20054ef0 | Blue Swirl | cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 32) & 0xfffc) | |
| 2267 | 20054ef0 | Blue Swirl | 3, 0, 0xffffffff, |
| 2268 | 2436b61a | balrog | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 2269 | 2436b61a | balrog | DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
| 2270 | 20054ef0 | Blue Swirl | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
| 2271 | 20054ef0 | Blue Swirl | DESC_L_MASK); |
| 2272 | 20054ef0 | Blue Swirl | cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 40) & 0xfffc) | |
| 2273 | 20054ef0 | Blue Swirl | 3, 0, 0xffffffff, |
| 2274 | 2436b61a | balrog | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 2275 | 2436b61a | balrog | DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
| 2276 | 2436b61a | balrog | DESC_W_MASK | DESC_A_MASK); |
| 2277 | 2436b61a | balrog | } else
|
| 2278 | 2436b61a | balrog | #endif
|
| 2279 | 2436b61a | balrog | {
|
| 2280 | 20054ef0 | Blue Swirl | cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | |
| 2281 | 20054ef0 | Blue Swirl | 3, 0, 0xffffffff, |
| 2282 | 2436b61a | balrog | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 2283 | 2436b61a | balrog | DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
| 2284 | 2436b61a | balrog | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
| 2285 | 20054ef0 | Blue Swirl | cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) | |
| 2286 | 20054ef0 | Blue Swirl | 3, 0, 0xffffffff, |
| 2287 | 2436b61a | balrog | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 2288 | 2436b61a | balrog | DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
| 2289 | 2436b61a | balrog | DESC_W_MASK | DESC_A_MASK); |
| 2290 | 2436b61a | balrog | } |
| 2291 | a4165610 | liguang | ESP = env->regs[R_ECX]; |
| 2292 | 00f5e6f2 | liguang | EIP = env->regs[R_EDX]; |
| 2293 | eaa728ee | bellard | } |
| 2294 | eaa728ee | bellard | |
| 2295 | 2999a0b2 | Blue Swirl | target_ulong helper_lsl(CPUX86State *env, target_ulong selector1) |
| 2296 | eaa728ee | bellard | {
|
| 2297 | eaa728ee | bellard | unsigned int limit; |
| 2298 | eaa728ee | bellard | uint32_t e1, e2, eflags, selector; |
| 2299 | eaa728ee | bellard | int rpl, dpl, cpl, type;
|
| 2300 | eaa728ee | bellard | |
| 2301 | eaa728ee | bellard | selector = selector1 & 0xffff;
|
| 2302 | f0967a1a | Blue Swirl | eflags = cpu_cc_compute_all(env, CC_OP); |
| 2303 | 20054ef0 | Blue Swirl | if ((selector & 0xfffc) == 0) { |
| 2304 | dc1ded53 | aliguori | goto fail;
|
| 2305 | 20054ef0 | Blue Swirl | } |
| 2306 | 2999a0b2 | Blue Swirl | if (load_segment(env, &e1, &e2, selector) != 0) { |
| 2307 | eaa728ee | bellard | goto fail;
|
| 2308 | 20054ef0 | Blue Swirl | } |
| 2309 | eaa728ee | bellard | rpl = selector & 3;
|
| 2310 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 2311 | eaa728ee | bellard | cpl = env->hflags & HF_CPL_MASK; |
| 2312 | eaa728ee | bellard | if (e2 & DESC_S_MASK) {
|
| 2313 | eaa728ee | bellard | if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
|
| 2314 | eaa728ee | bellard | /* conforming */
|
| 2315 | eaa728ee | bellard | } else {
|
| 2316 | 20054ef0 | Blue Swirl | if (dpl < cpl || dpl < rpl) {
|
| 2317 | eaa728ee | bellard | goto fail;
|
| 2318 | 20054ef0 | Blue Swirl | } |
| 2319 | eaa728ee | bellard | } |
| 2320 | eaa728ee | bellard | } else {
|
| 2321 | eaa728ee | bellard | type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
|
| 2322 | 20054ef0 | Blue Swirl | switch (type) {
|
| 2323 | eaa728ee | bellard | case 1: |
| 2324 | eaa728ee | bellard | case 2: |
| 2325 | eaa728ee | bellard | case 3: |
| 2326 | eaa728ee | bellard | case 9: |
| 2327 | eaa728ee | bellard | case 11: |
| 2328 | eaa728ee | bellard | break;
|
| 2329 | eaa728ee | bellard | default:
|
| 2330 | eaa728ee | bellard | goto fail;
|
| 2331 | eaa728ee | bellard | } |
| 2332 | eaa728ee | bellard | if (dpl < cpl || dpl < rpl) {
|
| 2333 | eaa728ee | bellard | fail:
|
| 2334 | eaa728ee | bellard | CC_SRC = eflags & ~CC_Z; |
| 2335 | eaa728ee | bellard | return 0; |
| 2336 | eaa728ee | bellard | } |
| 2337 | eaa728ee | bellard | } |
| 2338 | eaa728ee | bellard | limit = get_seg_limit(e1, e2); |
| 2339 | eaa728ee | bellard | CC_SRC = eflags | CC_Z; |
| 2340 | eaa728ee | bellard | return limit;
|
| 2341 | eaa728ee | bellard | } |
| 2342 | eaa728ee | bellard | |
| 2343 | 2999a0b2 | Blue Swirl | target_ulong helper_lar(CPUX86State *env, target_ulong selector1) |
| 2344 | eaa728ee | bellard | {
|
| 2345 | eaa728ee | bellard | uint32_t e1, e2, eflags, selector; |
| 2346 | eaa728ee | bellard | int rpl, dpl, cpl, type;
|
| 2347 | eaa728ee | bellard | |
| 2348 | eaa728ee | bellard | selector = selector1 & 0xffff;
|
| 2349 | f0967a1a | Blue Swirl | eflags = cpu_cc_compute_all(env, CC_OP); |
| 2350 | 20054ef0 | Blue Swirl | if ((selector & 0xfffc) == 0) { |
| 2351 | eaa728ee | bellard | goto fail;
|
| 2352 | 20054ef0 | Blue Swirl | } |
| 2353 | 2999a0b2 | Blue Swirl | if (load_segment(env, &e1, &e2, selector) != 0) { |
| 2354 | eaa728ee | bellard | goto fail;
|
| 2355 | 20054ef0 | Blue Swirl | } |
| 2356 | eaa728ee | bellard | rpl = selector & 3;
|
| 2357 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 2358 | eaa728ee | bellard | cpl = env->hflags & HF_CPL_MASK; |
| 2359 | eaa728ee | bellard | if (e2 & DESC_S_MASK) {
|
| 2360 | eaa728ee | bellard | if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
|
| 2361 | eaa728ee | bellard | /* conforming */
|
| 2362 | eaa728ee | bellard | } else {
|
| 2363 | 20054ef0 | Blue Swirl | if (dpl < cpl || dpl < rpl) {
|
| 2364 | eaa728ee | bellard | goto fail;
|
| 2365 | 20054ef0 | Blue Swirl | } |
| 2366 | eaa728ee | bellard | } |
| 2367 | eaa728ee | bellard | } else {
|
| 2368 | eaa728ee | bellard | type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
|
| 2369 | 20054ef0 | Blue Swirl | switch (type) {
|
| 2370 | eaa728ee | bellard | case 1: |
| 2371 | eaa728ee | bellard | case 2: |
| 2372 | eaa728ee | bellard | case 3: |
| 2373 | eaa728ee | bellard | case 4: |
| 2374 | eaa728ee | bellard | case 5: |
| 2375 | eaa728ee | bellard | case 9: |
| 2376 | eaa728ee | bellard | case 11: |
| 2377 | eaa728ee | bellard | case 12: |
| 2378 | eaa728ee | bellard | break;
|
| 2379 | eaa728ee | bellard | default:
|
| 2380 | eaa728ee | bellard | goto fail;
|
| 2381 | eaa728ee | bellard | } |
| 2382 | eaa728ee | bellard | if (dpl < cpl || dpl < rpl) {
|
| 2383 | eaa728ee | bellard | fail:
|
| 2384 | eaa728ee | bellard | CC_SRC = eflags & ~CC_Z; |
| 2385 | eaa728ee | bellard | return 0; |
| 2386 | eaa728ee | bellard | } |
| 2387 | eaa728ee | bellard | } |
| 2388 | eaa728ee | bellard | CC_SRC = eflags | CC_Z; |
| 2389 | eaa728ee | bellard | return e2 & 0x00f0ff00; |
| 2390 | eaa728ee | bellard | } |
| 2391 | eaa728ee | bellard | |
| 2392 | 2999a0b2 | Blue Swirl | void helper_verr(CPUX86State *env, target_ulong selector1)
|
| 2393 | eaa728ee | bellard | {
|
| 2394 | eaa728ee | bellard | uint32_t e1, e2, eflags, selector; |
| 2395 | eaa728ee | bellard | int rpl, dpl, cpl;
|
| 2396 | eaa728ee | bellard | |
| 2397 | eaa728ee | bellard | selector = selector1 & 0xffff;
|
| 2398 | f0967a1a | Blue Swirl | eflags = cpu_cc_compute_all(env, CC_OP); |
| 2399 | 20054ef0 | Blue Swirl | if ((selector & 0xfffc) == 0) { |
| 2400 | eaa728ee | bellard | goto fail;
|
| 2401 | 20054ef0 | Blue Swirl | } |
| 2402 | 2999a0b2 | Blue Swirl | if (load_segment(env, &e1, &e2, selector) != 0) { |
| 2403 | eaa728ee | bellard | goto fail;
|
| 2404 | 20054ef0 | Blue Swirl | } |
| 2405 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_S_MASK)) {
|
| 2406 | eaa728ee | bellard | goto fail;
|
| 2407 | 20054ef0 | Blue Swirl | } |
| 2408 | eaa728ee | bellard | rpl = selector & 3;
|
| 2409 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 2410 | eaa728ee | bellard | cpl = env->hflags & HF_CPL_MASK; |
| 2411 | eaa728ee | bellard | if (e2 & DESC_CS_MASK) {
|
| 2412 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_R_MASK)) {
|
| 2413 | eaa728ee | bellard | goto fail;
|
| 2414 | 20054ef0 | Blue Swirl | } |
| 2415 | eaa728ee | bellard | if (!(e2 & DESC_C_MASK)) {
|
| 2416 | 20054ef0 | Blue Swirl | if (dpl < cpl || dpl < rpl) {
|
| 2417 | eaa728ee | bellard | goto fail;
|
| 2418 | 20054ef0 | Blue Swirl | } |
| 2419 | eaa728ee | bellard | } |
| 2420 | eaa728ee | bellard | } else {
|
| 2421 | eaa728ee | bellard | if (dpl < cpl || dpl < rpl) {
|
| 2422 | eaa728ee | bellard | fail:
|
| 2423 | eaa728ee | bellard | CC_SRC = eflags & ~CC_Z; |
| 2424 | eaa728ee | bellard | return;
|
| 2425 | eaa728ee | bellard | } |
| 2426 | eaa728ee | bellard | } |
| 2427 | eaa728ee | bellard | CC_SRC = eflags | CC_Z; |
| 2428 | eaa728ee | bellard | } |
| 2429 | eaa728ee | bellard | |
| 2430 | 2999a0b2 | Blue Swirl | void helper_verw(CPUX86State *env, target_ulong selector1)
|
| 2431 | eaa728ee | bellard | {
|
| 2432 | eaa728ee | bellard | uint32_t e1, e2, eflags, selector; |
| 2433 | eaa728ee | bellard | int rpl, dpl, cpl;
|
| 2434 | eaa728ee | bellard | |
| 2435 | eaa728ee | bellard | selector = selector1 & 0xffff;
|
| 2436 | f0967a1a | Blue Swirl | eflags = cpu_cc_compute_all(env, CC_OP); |
| 2437 | 20054ef0 | Blue Swirl | if ((selector & 0xfffc) == 0) { |
| 2438 | eaa728ee | bellard | goto fail;
|
| 2439 | 20054ef0 | Blue Swirl | } |
| 2440 | 2999a0b2 | Blue Swirl | if (load_segment(env, &e1, &e2, selector) != 0) { |
| 2441 | eaa728ee | bellard | goto fail;
|
| 2442 | 20054ef0 | Blue Swirl | } |
| 2443 | 20054ef0 | Blue Swirl | if (!(e2 & DESC_S_MASK)) {
|
| 2444 | eaa728ee | bellard | goto fail;
|
| 2445 | 20054ef0 | Blue Swirl | } |
| 2446 | eaa728ee | bellard | rpl = selector & 3;
|
| 2447 | eaa728ee | bellard | dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
| 2448 | eaa728ee | bellard | cpl = env->hflags & HF_CPL_MASK; |
| 2449 | eaa728ee | bellard | if (e2 & DESC_CS_MASK) {
|
| 2450 | eaa728ee | bellard | goto fail;
|
| 2451 | eaa728ee | bellard | } else {
|
| 2452 | 20054ef0 | Blue Swirl | if (dpl < cpl || dpl < rpl) {
|
| 2453 | eaa728ee | bellard | goto fail;
|
| 2454 | 20054ef0 | Blue Swirl | } |
| 2455 | eaa728ee | bellard | if (!(e2 & DESC_W_MASK)) {
|
| 2456 | eaa728ee | bellard | fail:
|
| 2457 | eaa728ee | bellard | CC_SRC = eflags & ~CC_Z; |
| 2458 | eaa728ee | bellard | return;
|
| 2459 | eaa728ee | bellard | } |
| 2460 | eaa728ee | bellard | } |
| 2461 | eaa728ee | bellard | CC_SRC = eflags | CC_Z; |
| 2462 | eaa728ee | bellard | } |
| 2463 | eaa728ee | bellard | |
| 2464 | f299f437 | Blue Swirl | #if defined(CONFIG_USER_ONLY)
|
| 2465 | 2999a0b2 | Blue Swirl | void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector) |
| 2466 | eaa728ee | bellard | {
|
| 2467 | f299f437 | Blue Swirl | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
| 2468 | f299f437 | Blue Swirl | selector &= 0xffff;
|
| 2469 | f299f437 | Blue Swirl | cpu_x86_load_seg_cache(env, seg_reg, selector, |
| 2470 | f299f437 | Blue Swirl | (selector << 4), 0xffff, 0); |
| 2471 | f299f437 | Blue Swirl | } else {
|
| 2472 | 2999a0b2 | Blue Swirl | helper_load_seg(env, seg_reg, selector); |
| 2473 | 13822781 | Aurelien Jarno | } |
| 2474 | eaa728ee | bellard | } |
| 2475 | eaa728ee | bellard | #endif |