root / hw / usb / hcd-uhci.c @ 0132b4b6
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/*
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* USB UHCI controller emulation
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Copyright (c) 2008 Max Krasnyansky
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* Magor rewrite of the UHCI data structures parser and frame processor
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* Support for fully async operation and multiple outstanding transactions
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h" |
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#include "hw/usb.h" |
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#include "hw/pci.h" |
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#include "qemu-timer.h" |
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#include "iov.h" |
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#include "dma.h" |
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#include "trace.h" |
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|
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//#define DEBUG
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//#define DEBUG_DUMP_DATA
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#define UHCI_CMD_FGR (1 << 4) |
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#define UHCI_CMD_EGSM (1 << 3) |
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#define UHCI_CMD_GRESET (1 << 2) |
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#define UHCI_CMD_HCRESET (1 << 1) |
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#define UHCI_CMD_RS (1 << 0) |
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|
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#define UHCI_STS_HCHALTED (1 << 5) |
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#define UHCI_STS_HCPERR (1 << 4) |
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#define UHCI_STS_HSERR (1 << 3) |
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#define UHCI_STS_RD (1 << 2) |
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#define UHCI_STS_USBERR (1 << 1) |
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#define UHCI_STS_USBINT (1 << 0) |
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|
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#define TD_CTRL_SPD (1 << 29) |
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#define TD_CTRL_ERROR_SHIFT 27 |
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#define TD_CTRL_IOS (1 << 25) |
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#define TD_CTRL_IOC (1 << 24) |
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#define TD_CTRL_ACTIVE (1 << 23) |
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#define TD_CTRL_STALL (1 << 22) |
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#define TD_CTRL_BABBLE (1 << 20) |
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#define TD_CTRL_NAK (1 << 19) |
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#define TD_CTRL_TIMEOUT (1 << 18) |
61 |
|
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#define UHCI_PORT_SUSPEND (1 << 12) |
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#define UHCI_PORT_RESET (1 << 9) |
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#define UHCI_PORT_LSDA (1 << 8) |
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#define UHCI_PORT_RD (1 << 6) |
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#define UHCI_PORT_ENC (1 << 3) |
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#define UHCI_PORT_EN (1 << 2) |
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#define UHCI_PORT_CSC (1 << 1) |
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#define UHCI_PORT_CCS (1 << 0) |
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|
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#define UHCI_PORT_READ_ONLY (0x1bb) |
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#define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC)
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#define FRAME_TIMER_FREQ 1000 |
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#define FRAME_MAX_LOOPS 256 |
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#define NB_PORTS 2 |
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enum {
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TD_RESULT_STOP_FRAME = 10,
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TD_RESULT_COMPLETE, |
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TD_RESULT_NEXT_QH, |
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TD_RESULT_ASYNC_START, |
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TD_RESULT_ASYNC_CONT, |
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}; |
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typedef struct UHCIState UHCIState; |
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typedef struct UHCIAsync UHCIAsync; |
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typedef struct UHCIQueue UHCIQueue; |
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/*
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* Pending async transaction.
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* 'packet' must be the first field because completion
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* handler does "(UHCIAsync *) pkt" cast.
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*/
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struct UHCIAsync {
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USBPacket packet; |
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QEMUSGList sgl; |
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UHCIQueue *queue; |
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QTAILQ_ENTRY(UHCIAsync) next; |
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uint32_t td; |
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uint8_t isoc; |
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uint8_t done; |
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}; |
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struct UHCIQueue {
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uint32_t token; |
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UHCIState *uhci; |
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QTAILQ_ENTRY(UHCIQueue) next; |
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QTAILQ_HEAD(, UHCIAsync) asyncs; |
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int8_t valid; |
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}; |
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typedef struct UHCIPort { |
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USBPort port; |
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uint16_t ctrl; |
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} UHCIPort; |
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struct UHCIState {
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PCIDevice dev; |
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MemoryRegion io_bar; |
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USBBus bus; /* Note unused when we're a companion controller */
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uint16_t cmd; /* cmd register */
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uint16_t status; |
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uint16_t intr; /* interrupt enable register */
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uint16_t frnum; /* frame number */
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uint32_t fl_base_addr; /* frame list base address */
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uint8_t sof_timing; |
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uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
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int64_t expire_time; |
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QEMUTimer *frame_timer; |
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QEMUBH *bh; |
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uint32_t frame_bytes; |
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uint32_t frame_bandwidth; |
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UHCIPort ports[NB_PORTS]; |
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/* Interrupts that should be raised at the end of the current frame. */
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uint32_t pending_int_mask; |
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int irq_pin;
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/* Active packets */
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QTAILQ_HEAD(, UHCIQueue) queues; |
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uint8_t num_ports_vmstate; |
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/* Properties */
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char *masterbus;
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uint32_t firstport; |
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}; |
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typedef struct UHCI_TD { |
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uint32_t link; |
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uint32_t ctrl; /* see TD_CTRL_xxx */
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uint32_t token; |
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uint32_t buffer; |
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} UHCI_TD; |
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typedef struct UHCI_QH { |
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uint32_t link; |
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uint32_t el_link; |
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} UHCI_QH; |
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static inline int32_t uhci_queue_token(UHCI_TD *td) |
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{ |
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/* covers ep, dev, pid -> identifies the endpoint */
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return td->token & 0x7ffff; |
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} |
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static UHCIQueue *uhci_queue_get(UHCIState *s, UHCI_TD *td)
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{ |
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uint32_t token = uhci_queue_token(td); |
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UHCIQueue *queue; |
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QTAILQ_FOREACH(queue, &s->queues, next) { |
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if (queue->token == token) {
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return queue;
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} |
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} |
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queue = g_new0(UHCIQueue, 1);
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queue->uhci = s; |
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queue->token = token; |
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QTAILQ_INIT(&queue->asyncs); |
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QTAILQ_INSERT_HEAD(&s->queues, queue, next); |
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trace_usb_uhci_queue_add(queue->token); |
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return queue;
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} |
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static void uhci_queue_free(UHCIQueue *queue) |
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{ |
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UHCIState *s = queue->uhci; |
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trace_usb_uhci_queue_del(queue->token); |
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QTAILQ_REMOVE(&s->queues, queue, next); |
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g_free(queue); |
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} |
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static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t addr)
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{ |
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UHCIAsync *async = g_new0(UHCIAsync, 1);
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async->queue = queue; |
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async->td = addr; |
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usb_packet_init(&async->packet); |
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pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1);
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trace_usb_uhci_packet_add(async->queue->token, async->td); |
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return async;
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} |
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static void uhci_async_free(UHCIAsync *async) |
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{ |
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trace_usb_uhci_packet_del(async->queue->token, async->td); |
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usb_packet_cleanup(&async->packet); |
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qemu_sglist_destroy(&async->sgl); |
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g_free(async); |
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} |
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static void uhci_async_link(UHCIAsync *async) |
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{ |
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UHCIQueue *queue = async->queue; |
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QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); |
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trace_usb_uhci_packet_link_async(async->queue->token, async->td); |
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} |
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static void uhci_async_unlink(UHCIAsync *async) |
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{ |
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UHCIQueue *queue = async->queue; |
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QTAILQ_REMOVE(&queue->asyncs, async, next); |
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trace_usb_uhci_packet_unlink_async(async->queue->token, async->td); |
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} |
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static void uhci_async_cancel(UHCIAsync *async) |
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{ |
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trace_usb_uhci_packet_cancel(async->queue->token, async->td, async->done); |
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if (!async->done)
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usb_cancel_packet(&async->packet); |
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uhci_async_free(async); |
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} |
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/*
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* Mark all outstanding async packets as invalid.
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* This is used for canceling them when TDs are removed by the HCD.
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*/
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static void uhci_async_validate_begin(UHCIState *s) |
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{ |
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UHCIQueue *queue; |
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QTAILQ_FOREACH(queue, &s->queues, next) { |
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queue->valid--; |
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} |
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} |
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/*
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* Cancel async packets that are no longer valid
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*/
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static void uhci_async_validate_end(UHCIState *s) |
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{ |
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UHCIQueue *queue, *n; |
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UHCIAsync *async; |
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QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { |
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if (queue->valid > 0) { |
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continue;
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} |
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while (!QTAILQ_EMPTY(&queue->asyncs)) {
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async = QTAILQ_FIRST(&queue->asyncs); |
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uhci_async_unlink(async); |
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uhci_async_cancel(async); |
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} |
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uhci_queue_free(queue); |
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} |
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} |
275 |
|
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static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) |
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{ |
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UHCIQueue *queue; |
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UHCIAsync *curr, *n; |
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|
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QTAILQ_FOREACH(queue, &s->queues, next) { |
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QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { |
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if (!usb_packet_is_inflight(&curr->packet) ||
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curr->packet.ep->dev != dev) { |
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continue;
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} |
287 |
uhci_async_unlink(curr); |
288 |
uhci_async_cancel(curr); |
289 |
} |
290 |
} |
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} |
292 |
|
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static void uhci_async_cancel_all(UHCIState *s) |
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{ |
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UHCIQueue *queue, *nq; |
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UHCIAsync *curr, *n; |
297 |
|
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QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { |
299 |
QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { |
300 |
uhci_async_unlink(curr); |
301 |
uhci_async_cancel(curr); |
302 |
} |
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uhci_queue_free(queue); |
304 |
} |
305 |
} |
306 |
|
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static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, UHCI_TD *td)
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{ |
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uint32_t token = uhci_queue_token(td); |
310 |
UHCIQueue *queue; |
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UHCIAsync *async; |
312 |
|
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QTAILQ_FOREACH(queue, &s->queues, next) { |
314 |
if (queue->token == token) {
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break;
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} |
317 |
} |
318 |
if (queue == NULL) { |
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return NULL; |
320 |
} |
321 |
|
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QTAILQ_FOREACH(async, &queue->asyncs, next) { |
323 |
if (async->td == addr) {
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return async;
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} |
326 |
} |
327 |
|
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return NULL; |
329 |
} |
330 |
|
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static void uhci_update_irq(UHCIState *s) |
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{ |
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int level;
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if (((s->status2 & 1) && (s->intr & (1 << 2))) || |
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((s->status2 & 2) && (s->intr & (1 << 3))) || |
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((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || |
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((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || |
338 |
(s->status & UHCI_STS_HSERR) || |
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(s->status & UHCI_STS_HCPERR)) { |
340 |
level = 1;
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} else {
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level = 0;
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} |
344 |
qemu_set_irq(s->dev.irq[s->irq_pin], level); |
345 |
} |
346 |
|
347 |
static void uhci_reset(void *opaque) |
348 |
{ |
349 |
UHCIState *s = opaque; |
350 |
uint8_t *pci_conf; |
351 |
int i;
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UHCIPort *port; |
353 |
|
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trace_usb_uhci_reset(); |
355 |
|
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pci_conf = s->dev.config; |
357 |
|
358 |
pci_conf[0x6a] = 0x01; /* usb clock */ |
359 |
pci_conf[0x6b] = 0x00; |
360 |
s->cmd = 0;
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361 |
s->status = 0;
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362 |
s->status2 = 0;
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363 |
s->intr = 0;
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364 |
s->fl_base_addr = 0;
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365 |
s->sof_timing = 64;
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366 |
|
367 |
for(i = 0; i < NB_PORTS; i++) { |
368 |
port = &s->ports[i]; |
369 |
port->ctrl = 0x0080;
|
370 |
if (port->port.dev && port->port.dev->attached) {
|
371 |
usb_port_reset(&port->port); |
372 |
} |
373 |
} |
374 |
|
375 |
uhci_async_cancel_all(s); |
376 |
qemu_bh_cancel(s->bh); |
377 |
uhci_update_irq(s); |
378 |
} |
379 |
|
380 |
static const VMStateDescription vmstate_uhci_port = { |
381 |
.name = "uhci port",
|
382 |
.version_id = 1,
|
383 |
.minimum_version_id = 1,
|
384 |
.minimum_version_id_old = 1,
|
385 |
.fields = (VMStateField []) { |
386 |
VMSTATE_UINT16(ctrl, UHCIPort), |
387 |
VMSTATE_END_OF_LIST() |
388 |
} |
389 |
}; |
390 |
|
391 |
static int uhci_post_load(void *opaque, int version_id) |
392 |
{ |
393 |
UHCIState *s = opaque; |
394 |
|
395 |
if (version_id < 2) { |
396 |
s->expire_time = qemu_get_clock_ns(vm_clock) + |
397 |
(get_ticks_per_sec() / FRAME_TIMER_FREQ); |
398 |
} |
399 |
return 0; |
400 |
} |
401 |
|
402 |
static const VMStateDescription vmstate_uhci = { |
403 |
.name = "uhci",
|
404 |
.version_id = 2,
|
405 |
.minimum_version_id = 1,
|
406 |
.minimum_version_id_old = 1,
|
407 |
.post_load = uhci_post_load, |
408 |
.fields = (VMStateField []) { |
409 |
VMSTATE_PCI_DEVICE(dev, UHCIState), |
410 |
VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), |
411 |
VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
|
412 |
vmstate_uhci_port, UHCIPort), |
413 |
VMSTATE_UINT16(cmd, UHCIState), |
414 |
VMSTATE_UINT16(status, UHCIState), |
415 |
VMSTATE_UINT16(intr, UHCIState), |
416 |
VMSTATE_UINT16(frnum, UHCIState), |
417 |
VMSTATE_UINT32(fl_base_addr, UHCIState), |
418 |
VMSTATE_UINT8(sof_timing, UHCIState), |
419 |
VMSTATE_UINT8(status2, UHCIState), |
420 |
VMSTATE_TIMER(frame_timer, UHCIState), |
421 |
VMSTATE_INT64_V(expire_time, UHCIState, 2),
|
422 |
VMSTATE_END_OF_LIST() |
423 |
} |
424 |
}; |
425 |
|
426 |
static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
427 |
{ |
428 |
UHCIState *s = opaque; |
429 |
|
430 |
addr &= 0x1f;
|
431 |
switch(addr) {
|
432 |
case 0x0c: |
433 |
s->sof_timing = val; |
434 |
break;
|
435 |
} |
436 |
} |
437 |
|
438 |
static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) |
439 |
{ |
440 |
UHCIState *s = opaque; |
441 |
uint32_t val; |
442 |
|
443 |
addr &= 0x1f;
|
444 |
switch(addr) {
|
445 |
case 0x0c: |
446 |
val = s->sof_timing; |
447 |
break;
|
448 |
default:
|
449 |
val = 0xff;
|
450 |
break;
|
451 |
} |
452 |
return val;
|
453 |
} |
454 |
|
455 |
static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
456 |
{ |
457 |
UHCIState *s = opaque; |
458 |
|
459 |
addr &= 0x1f;
|
460 |
trace_usb_uhci_mmio_writew(addr, val); |
461 |
|
462 |
switch(addr) {
|
463 |
case 0x00: |
464 |
if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
|
465 |
/* start frame processing */
|
466 |
trace_usb_uhci_schedule_start(); |
467 |
s->expire_time = qemu_get_clock_ns(vm_clock) + |
468 |
(get_ticks_per_sec() / FRAME_TIMER_FREQ); |
469 |
qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); |
470 |
s->status &= ~UHCI_STS_HCHALTED; |
471 |
} else if (!(val & UHCI_CMD_RS)) { |
472 |
s->status |= UHCI_STS_HCHALTED; |
473 |
} |
474 |
if (val & UHCI_CMD_GRESET) {
|
475 |
UHCIPort *port; |
476 |
int i;
|
477 |
|
478 |
/* send reset on the USB bus */
|
479 |
for(i = 0; i < NB_PORTS; i++) { |
480 |
port = &s->ports[i]; |
481 |
usb_device_reset(port->port.dev); |
482 |
} |
483 |
uhci_reset(s); |
484 |
return;
|
485 |
} |
486 |
if (val & UHCI_CMD_HCRESET) {
|
487 |
uhci_reset(s); |
488 |
return;
|
489 |
} |
490 |
s->cmd = val; |
491 |
break;
|
492 |
case 0x02: |
493 |
s->status &= ~val; |
494 |
/* XXX: the chip spec is not coherent, so we add a hidden
|
495 |
register to distinguish between IOC and SPD */
|
496 |
if (val & UHCI_STS_USBINT)
|
497 |
s->status2 = 0;
|
498 |
uhci_update_irq(s); |
499 |
break;
|
500 |
case 0x04: |
501 |
s->intr = val; |
502 |
uhci_update_irq(s); |
503 |
break;
|
504 |
case 0x06: |
505 |
if (s->status & UHCI_STS_HCHALTED)
|
506 |
s->frnum = val & 0x7ff;
|
507 |
break;
|
508 |
case 0x10 ... 0x1f: |
509 |
{ |
510 |
UHCIPort *port; |
511 |
USBDevice *dev; |
512 |
int n;
|
513 |
|
514 |
n = (addr >> 1) & 7; |
515 |
if (n >= NB_PORTS)
|
516 |
return;
|
517 |
port = &s->ports[n]; |
518 |
dev = port->port.dev; |
519 |
if (dev && dev->attached) {
|
520 |
/* port reset */
|
521 |
if ( (val & UHCI_PORT_RESET) &&
|
522 |
!(port->ctrl & UHCI_PORT_RESET) ) { |
523 |
usb_device_reset(dev); |
524 |
} |
525 |
} |
526 |
port->ctrl &= UHCI_PORT_READ_ONLY; |
527 |
port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); |
528 |
/* some bits are reset when a '1' is written to them */
|
529 |
port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); |
530 |
} |
531 |
break;
|
532 |
} |
533 |
} |
534 |
|
535 |
static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) |
536 |
{ |
537 |
UHCIState *s = opaque; |
538 |
uint32_t val; |
539 |
|
540 |
addr &= 0x1f;
|
541 |
switch(addr) {
|
542 |
case 0x00: |
543 |
val = s->cmd; |
544 |
break;
|
545 |
case 0x02: |
546 |
val = s->status; |
547 |
break;
|
548 |
case 0x04: |
549 |
val = s->intr; |
550 |
break;
|
551 |
case 0x06: |
552 |
val = s->frnum; |
553 |
break;
|
554 |
case 0x10 ... 0x1f: |
555 |
{ |
556 |
UHCIPort *port; |
557 |
int n;
|
558 |
n = (addr >> 1) & 7; |
559 |
if (n >= NB_PORTS)
|
560 |
goto read_default;
|
561 |
port = &s->ports[n]; |
562 |
val = port->ctrl; |
563 |
} |
564 |
break;
|
565 |
default:
|
566 |
read_default:
|
567 |
val = 0xff7f; /* disabled port */ |
568 |
break;
|
569 |
} |
570 |
|
571 |
trace_usb_uhci_mmio_readw(addr, val); |
572 |
|
573 |
return val;
|
574 |
} |
575 |
|
576 |
static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
577 |
{ |
578 |
UHCIState *s = opaque; |
579 |
|
580 |
addr &= 0x1f;
|
581 |
trace_usb_uhci_mmio_writel(addr, val); |
582 |
|
583 |
switch(addr) {
|
584 |
case 0x08: |
585 |
s->fl_base_addr = val & ~0xfff;
|
586 |
break;
|
587 |
} |
588 |
} |
589 |
|
590 |
static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) |
591 |
{ |
592 |
UHCIState *s = opaque; |
593 |
uint32_t val; |
594 |
|
595 |
addr &= 0x1f;
|
596 |
switch(addr) {
|
597 |
case 0x08: |
598 |
val = s->fl_base_addr; |
599 |
break;
|
600 |
default:
|
601 |
val = 0xffffffff;
|
602 |
break;
|
603 |
} |
604 |
trace_usb_uhci_mmio_readl(addr, val); |
605 |
return val;
|
606 |
} |
607 |
|
608 |
/* signal resume if controller suspended */
|
609 |
static void uhci_resume (void *opaque) |
610 |
{ |
611 |
UHCIState *s = (UHCIState *)opaque; |
612 |
|
613 |
if (!s)
|
614 |
return;
|
615 |
|
616 |
if (s->cmd & UHCI_CMD_EGSM) {
|
617 |
s->cmd |= UHCI_CMD_FGR; |
618 |
s->status |= UHCI_STS_RD; |
619 |
uhci_update_irq(s); |
620 |
} |
621 |
} |
622 |
|
623 |
static void uhci_attach(USBPort *port1) |
624 |
{ |
625 |
UHCIState *s = port1->opaque; |
626 |
UHCIPort *port = &s->ports[port1->index]; |
627 |
|
628 |
/* set connect status */
|
629 |
port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; |
630 |
|
631 |
/* update speed */
|
632 |
if (port->port.dev->speed == USB_SPEED_LOW) {
|
633 |
port->ctrl |= UHCI_PORT_LSDA; |
634 |
} else {
|
635 |
port->ctrl &= ~UHCI_PORT_LSDA; |
636 |
} |
637 |
|
638 |
uhci_resume(s); |
639 |
} |
640 |
|
641 |
static void uhci_detach(USBPort *port1) |
642 |
{ |
643 |
UHCIState *s = port1->opaque; |
644 |
UHCIPort *port = &s->ports[port1->index]; |
645 |
|
646 |
uhci_async_cancel_device(s, port1->dev); |
647 |
|
648 |
/* set connect status */
|
649 |
if (port->ctrl & UHCI_PORT_CCS) {
|
650 |
port->ctrl &= ~UHCI_PORT_CCS; |
651 |
port->ctrl |= UHCI_PORT_CSC; |
652 |
} |
653 |
/* disable port */
|
654 |
if (port->ctrl & UHCI_PORT_EN) {
|
655 |
port->ctrl &= ~UHCI_PORT_EN; |
656 |
port->ctrl |= UHCI_PORT_ENC; |
657 |
} |
658 |
|
659 |
uhci_resume(s); |
660 |
} |
661 |
|
662 |
static void uhci_child_detach(USBPort *port1, USBDevice *child) |
663 |
{ |
664 |
UHCIState *s = port1->opaque; |
665 |
|
666 |
uhci_async_cancel_device(s, child); |
667 |
} |
668 |
|
669 |
static void uhci_wakeup(USBPort *port1) |
670 |
{ |
671 |
UHCIState *s = port1->opaque; |
672 |
UHCIPort *port = &s->ports[port1->index]; |
673 |
|
674 |
if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
|
675 |
port->ctrl |= UHCI_PORT_RD; |
676 |
uhci_resume(s); |
677 |
} |
678 |
} |
679 |
|
680 |
static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
|
681 |
{ |
682 |
USBDevice *dev; |
683 |
int i;
|
684 |
|
685 |
for (i = 0; i < NB_PORTS; i++) { |
686 |
UHCIPort *port = &s->ports[i]; |
687 |
if (!(port->ctrl & UHCI_PORT_EN)) {
|
688 |
continue;
|
689 |
} |
690 |
dev = usb_find_device(&port->port, addr); |
691 |
if (dev != NULL) { |
692 |
return dev;
|
693 |
} |
694 |
} |
695 |
return NULL; |
696 |
} |
697 |
|
698 |
static void uhci_async_complete(USBPort *port, USBPacket *packet); |
699 |
static void uhci_process_frame(UHCIState *s); |
700 |
|
701 |
/* return -1 if fatal error (frame must be stopped)
|
702 |
0 if TD successful
|
703 |
1 if TD unsuccessful or inactive
|
704 |
*/
|
705 |
static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) |
706 |
{ |
707 |
int len = 0, max_len, err, ret; |
708 |
uint8_t pid; |
709 |
|
710 |
max_len = ((td->token >> 21) + 1) & 0x7ff; |
711 |
pid = td->token & 0xff;
|
712 |
|
713 |
ret = async->packet.result; |
714 |
|
715 |
if (td->ctrl & TD_CTRL_IOS)
|
716 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
717 |
|
718 |
if (ret < 0) |
719 |
goto out;
|
720 |
|
721 |
len = async->packet.result; |
722 |
td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
723 |
|
724 |
/* The NAK bit may have been set by a previous frame, so clear it
|
725 |
here. The docs are somewhat unclear, but win2k relies on this
|
726 |
behavior. */
|
727 |
td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); |
728 |
if (td->ctrl & TD_CTRL_IOC)
|
729 |
*int_mask |= 0x01;
|
730 |
|
731 |
if (pid == USB_TOKEN_IN) {
|
732 |
if (len > max_len) {
|
733 |
ret = USB_RET_BABBLE; |
734 |
goto out;
|
735 |
} |
736 |
|
737 |
if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
|
738 |
*int_mask |= 0x02;
|
739 |
/* short packet: do not update QH */
|
740 |
trace_usb_uhci_packet_complete_shortxfer(async->queue->token, |
741 |
async->td); |
742 |
return TD_RESULT_NEXT_QH;
|
743 |
} |
744 |
} |
745 |
|
746 |
/* success */
|
747 |
trace_usb_uhci_packet_complete_success(async->queue->token, async->td); |
748 |
return TD_RESULT_COMPLETE;
|
749 |
|
750 |
out:
|
751 |
/*
|
752 |
* We should not do any further processing on a queue with errors!
|
753 |
* This is esp. important for bulk endpoints with pipelining enabled
|
754 |
* (redirection to a real USB device), where we must cancel all the
|
755 |
* transfers after this one so that:
|
756 |
* 1) If they've completed already, they are not processed further
|
757 |
* causing more stalls, originating from the same failed transfer
|
758 |
* 2) If still in flight, they are cancelled before the guest does
|
759 |
* a clear stall, otherwise the guest and device can loose sync!
|
760 |
*/
|
761 |
while (!QTAILQ_EMPTY(&async->queue->asyncs)) {
|
762 |
UHCIAsync *as = QTAILQ_FIRST(&async->queue->asyncs); |
763 |
uhci_async_unlink(as); |
764 |
uhci_async_cancel(as); |
765 |
} |
766 |
|
767 |
switch(ret) {
|
768 |
case USB_RET_STALL:
|
769 |
td->ctrl |= TD_CTRL_STALL; |
770 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
771 |
s->status |= UHCI_STS_USBERR; |
772 |
if (td->ctrl & TD_CTRL_IOC) {
|
773 |
*int_mask |= 0x01;
|
774 |
} |
775 |
uhci_update_irq(s); |
776 |
trace_usb_uhci_packet_complete_stall(async->queue->token, async->td); |
777 |
return TD_RESULT_NEXT_QH;
|
778 |
|
779 |
case USB_RET_BABBLE:
|
780 |
td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; |
781 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
782 |
s->status |= UHCI_STS_USBERR; |
783 |
if (td->ctrl & TD_CTRL_IOC) {
|
784 |
*int_mask |= 0x01;
|
785 |
} |
786 |
uhci_update_irq(s); |
787 |
/* frame interrupted */
|
788 |
trace_usb_uhci_packet_complete_babble(async->queue->token, async->td); |
789 |
return TD_RESULT_STOP_FRAME;
|
790 |
|
791 |
case USB_RET_NAK:
|
792 |
td->ctrl |= TD_CTRL_NAK; |
793 |
if (pid == USB_TOKEN_SETUP)
|
794 |
break;
|
795 |
return TD_RESULT_NEXT_QH;
|
796 |
|
797 |
case USB_RET_IOERROR:
|
798 |
case USB_RET_NODEV:
|
799 |
default:
|
800 |
break;
|
801 |
} |
802 |
|
803 |
/* Retry the TD if error count is not zero */
|
804 |
|
805 |
td->ctrl |= TD_CTRL_TIMEOUT; |
806 |
err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
|
807 |
if (err != 0) { |
808 |
err--; |
809 |
if (err == 0) { |
810 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
811 |
s->status |= UHCI_STS_USBERR; |
812 |
if (td->ctrl & TD_CTRL_IOC)
|
813 |
*int_mask |= 0x01;
|
814 |
uhci_update_irq(s); |
815 |
trace_usb_uhci_packet_complete_error(async->queue->token, |
816 |
async->td); |
817 |
} |
818 |
} |
819 |
td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
|
820 |
(err << TD_CTRL_ERROR_SHIFT); |
821 |
return TD_RESULT_NEXT_QH;
|
822 |
} |
823 |
|
824 |
static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, |
825 |
uint32_t *int_mask, bool queuing)
|
826 |
{ |
827 |
UHCIAsync *async; |
828 |
int len = 0, max_len; |
829 |
uint8_t pid; |
830 |
USBDevice *dev; |
831 |
USBEndpoint *ep; |
832 |
|
833 |
/* Is active ? */
|
834 |
if (!(td->ctrl & TD_CTRL_ACTIVE))
|
835 |
return TD_RESULT_NEXT_QH;
|
836 |
|
837 |
async = uhci_async_find_td(s, addr, td); |
838 |
if (async) {
|
839 |
/* Already submitted */
|
840 |
async->queue->valid = 32;
|
841 |
|
842 |
if (!async->done)
|
843 |
return TD_RESULT_ASYNC_CONT;
|
844 |
if (queuing) {
|
845 |
/* we are busy filling the queue, we are not prepared
|
846 |
to consume completed packages then, just leave them
|
847 |
in async state */
|
848 |
return TD_RESULT_ASYNC_CONT;
|
849 |
} |
850 |
|
851 |
uhci_async_unlink(async); |
852 |
goto done;
|
853 |
} |
854 |
|
855 |
/* Allocate new packet */
|
856 |
async = uhci_async_alloc(uhci_queue_get(s, td), addr); |
857 |
|
858 |
/* valid needs to be large enough to handle 10 frame delay
|
859 |
* for initial isochronous requests
|
860 |
*/
|
861 |
async->queue->valid = 32;
|
862 |
async->isoc = td->ctrl & TD_CTRL_IOS; |
863 |
|
864 |
max_len = ((td->token >> 21) + 1) & 0x7ff; |
865 |
pid = td->token & 0xff;
|
866 |
|
867 |
dev = uhci_find_device(s, (td->token >> 8) & 0x7f); |
868 |
ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); |
869 |
usb_packet_setup(&async->packet, pid, ep); |
870 |
qemu_sglist_add(&async->sgl, td->buffer, max_len); |
871 |
usb_packet_map(&async->packet, &async->sgl); |
872 |
|
873 |
switch(pid) {
|
874 |
case USB_TOKEN_OUT:
|
875 |
case USB_TOKEN_SETUP:
|
876 |
len = usb_handle_packet(dev, &async->packet); |
877 |
if (len >= 0) |
878 |
len = max_len; |
879 |
break;
|
880 |
|
881 |
case USB_TOKEN_IN:
|
882 |
len = usb_handle_packet(dev, &async->packet); |
883 |
break;
|
884 |
|
885 |
default:
|
886 |
/* invalid pid : frame interrupted */
|
887 |
uhci_async_free(async); |
888 |
s->status |= UHCI_STS_HCPERR; |
889 |
uhci_update_irq(s); |
890 |
return TD_RESULT_STOP_FRAME;
|
891 |
} |
892 |
|
893 |
if (len == USB_RET_ASYNC) {
|
894 |
uhci_async_link(async); |
895 |
return TD_RESULT_ASYNC_START;
|
896 |
} |
897 |
|
898 |
async->packet.result = len; |
899 |
|
900 |
done:
|
901 |
len = uhci_complete_td(s, td, async, int_mask); |
902 |
usb_packet_unmap(&async->packet, &async->sgl); |
903 |
uhci_async_free(async); |
904 |
return len;
|
905 |
} |
906 |
|
907 |
static void uhci_async_complete(USBPort *port, USBPacket *packet) |
908 |
{ |
909 |
UHCIAsync *async = container_of(packet, UHCIAsync, packet); |
910 |
UHCIState *s = async->queue->uhci; |
911 |
|
912 |
if (async->isoc) {
|
913 |
UHCI_TD td; |
914 |
uint32_t link = async->td; |
915 |
uint32_t int_mask = 0, val;
|
916 |
|
917 |
pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); |
918 |
le32_to_cpus(&td.link); |
919 |
le32_to_cpus(&td.ctrl); |
920 |
le32_to_cpus(&td.token); |
921 |
le32_to_cpus(&td.buffer); |
922 |
|
923 |
uhci_async_unlink(async); |
924 |
uhci_complete_td(s, &td, async, &int_mask); |
925 |
s->pending_int_mask |= int_mask; |
926 |
|
927 |
/* update the status bits of the TD */
|
928 |
val = cpu_to_le32(td.ctrl); |
929 |
pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); |
930 |
uhci_async_free(async); |
931 |
} else {
|
932 |
async->done = 1;
|
933 |
if (s->frame_bytes < s->frame_bandwidth) {
|
934 |
qemu_bh_schedule(s->bh); |
935 |
} |
936 |
} |
937 |
} |
938 |
|
939 |
static int is_valid(uint32_t link) |
940 |
{ |
941 |
return (link & 1) == 0; |
942 |
} |
943 |
|
944 |
static int is_qh(uint32_t link) |
945 |
{ |
946 |
return (link & 2) != 0; |
947 |
} |
948 |
|
949 |
static int depth_first(uint32_t link) |
950 |
{ |
951 |
return (link & 4) != 0; |
952 |
} |
953 |
|
954 |
/* QH DB used for detecting QH loops */
|
955 |
#define UHCI_MAX_QUEUES 128 |
956 |
typedef struct { |
957 |
uint32_t addr[UHCI_MAX_QUEUES]; |
958 |
int count;
|
959 |
} QhDb; |
960 |
|
961 |
static void qhdb_reset(QhDb *db) |
962 |
{ |
963 |
db->count = 0;
|
964 |
} |
965 |
|
966 |
/* Add QH to DB. Returns 1 if already present or DB is full. */
|
967 |
static int qhdb_insert(QhDb *db, uint32_t addr) |
968 |
{ |
969 |
int i;
|
970 |
for (i = 0; i < db->count; i++) |
971 |
if (db->addr[i] == addr)
|
972 |
return 1; |
973 |
|
974 |
if (db->count >= UHCI_MAX_QUEUES)
|
975 |
return 1; |
976 |
|
977 |
db->addr[db->count++] = addr; |
978 |
return 0; |
979 |
} |
980 |
|
981 |
static void uhci_fill_queue(UHCIState *s, UHCI_TD *td) |
982 |
{ |
983 |
uint32_t int_mask = 0;
|
984 |
uint32_t plink = td->link; |
985 |
uint32_t token = uhci_queue_token(td); |
986 |
UHCI_TD ptd; |
987 |
int ret;
|
988 |
|
989 |
while (is_valid(plink)) {
|
990 |
pci_dma_read(&s->dev, plink & ~0xf, &ptd, sizeof(ptd)); |
991 |
le32_to_cpus(&ptd.link); |
992 |
le32_to_cpus(&ptd.ctrl); |
993 |
le32_to_cpus(&ptd.token); |
994 |
le32_to_cpus(&ptd.buffer); |
995 |
if (!(ptd.ctrl & TD_CTRL_ACTIVE)) {
|
996 |
break;
|
997 |
} |
998 |
if (uhci_queue_token(&ptd) != token) {
|
999 |
break;
|
1000 |
} |
1001 |
trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token);
|
1002 |
ret = uhci_handle_td(s, plink, &ptd, &int_mask, true);
|
1003 |
if (ret == TD_RESULT_ASYNC_CONT) {
|
1004 |
break;
|
1005 |
} |
1006 |
assert(ret == TD_RESULT_ASYNC_START); |
1007 |
assert(int_mask == 0);
|
1008 |
plink = ptd.link; |
1009 |
} |
1010 |
} |
1011 |
|
1012 |
static void uhci_process_frame(UHCIState *s) |
1013 |
{ |
1014 |
uint32_t frame_addr, link, old_td_ctrl, val, int_mask; |
1015 |
uint32_t curr_qh, td_count = 0;
|
1016 |
int cnt, ret;
|
1017 |
UHCI_TD td; |
1018 |
UHCI_QH qh; |
1019 |
QhDb qhdb; |
1020 |
|
1021 |
frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
1022 |
|
1023 |
pci_dma_read(&s->dev, frame_addr, &link, 4);
|
1024 |
le32_to_cpus(&link); |
1025 |
|
1026 |
int_mask = 0;
|
1027 |
curr_qh = 0;
|
1028 |
|
1029 |
qhdb_reset(&qhdb); |
1030 |
|
1031 |
for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
|
1032 |
if (s->frame_bytes >= s->frame_bandwidth) {
|
1033 |
/* We've reached the usb 1.1 bandwidth, which is
|
1034 |
1280 bytes/frame, stop processing */
|
1035 |
trace_usb_uhci_frame_stop_bandwidth(); |
1036 |
break;
|
1037 |
} |
1038 |
if (is_qh(link)) {
|
1039 |
/* QH */
|
1040 |
trace_usb_uhci_qh_load(link & ~0xf);
|
1041 |
|
1042 |
if (qhdb_insert(&qhdb, link)) {
|
1043 |
/*
|
1044 |
* We're going in circles. Which is not a bug because
|
1045 |
* HCD is allowed to do that as part of the BW management.
|
1046 |
*
|
1047 |
* Stop processing here if no transaction has been done
|
1048 |
* since we've been here last time.
|
1049 |
*/
|
1050 |
if (td_count == 0) { |
1051 |
trace_usb_uhci_frame_loop_stop_idle(); |
1052 |
break;
|
1053 |
} else {
|
1054 |
trace_usb_uhci_frame_loop_continue(); |
1055 |
td_count = 0;
|
1056 |
qhdb_reset(&qhdb); |
1057 |
qhdb_insert(&qhdb, link); |
1058 |
} |
1059 |
} |
1060 |
|
1061 |
pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); |
1062 |
le32_to_cpus(&qh.link); |
1063 |
le32_to_cpus(&qh.el_link); |
1064 |
|
1065 |
if (!is_valid(qh.el_link)) {
|
1066 |
/* QH w/o elements */
|
1067 |
curr_qh = 0;
|
1068 |
link = qh.link; |
1069 |
} else {
|
1070 |
/* QH with elements */
|
1071 |
curr_qh = link; |
1072 |
link = qh.el_link; |
1073 |
} |
1074 |
continue;
|
1075 |
} |
1076 |
|
1077 |
/* TD */
|
1078 |
pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); |
1079 |
le32_to_cpus(&td.link); |
1080 |
le32_to_cpus(&td.ctrl); |
1081 |
le32_to_cpus(&td.token); |
1082 |
le32_to_cpus(&td.buffer); |
1083 |
trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); |
1084 |
|
1085 |
old_td_ctrl = td.ctrl; |
1086 |
ret = uhci_handle_td(s, link, &td, &int_mask, false);
|
1087 |
if (old_td_ctrl != td.ctrl) {
|
1088 |
/* update the status bits of the TD */
|
1089 |
val = cpu_to_le32(td.ctrl); |
1090 |
pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); |
1091 |
} |
1092 |
|
1093 |
switch (ret) {
|
1094 |
case TD_RESULT_STOP_FRAME: /* interrupted frame */ |
1095 |
goto out;
|
1096 |
|
1097 |
case TD_RESULT_NEXT_QH:
|
1098 |
case TD_RESULT_ASYNC_CONT:
|
1099 |
trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); |
1100 |
link = curr_qh ? qh.link : td.link; |
1101 |
continue;
|
1102 |
|
1103 |
case TD_RESULT_ASYNC_START:
|
1104 |
trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); |
1105 |
if (is_valid(td.link)) {
|
1106 |
uhci_fill_queue(s, &td); |
1107 |
} |
1108 |
link = curr_qh ? qh.link : td.link; |
1109 |
continue;
|
1110 |
|
1111 |
case TD_RESULT_COMPLETE:
|
1112 |
trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); |
1113 |
link = td.link; |
1114 |
td_count++; |
1115 |
s->frame_bytes += (td.ctrl & 0x7ff) + 1; |
1116 |
|
1117 |
if (curr_qh) {
|
1118 |
/* update QH element link */
|
1119 |
qh.el_link = link; |
1120 |
val = cpu_to_le32(qh.el_link); |
1121 |
pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); |
1122 |
|
1123 |
if (!depth_first(link)) {
|
1124 |
/* done with this QH */
|
1125 |
curr_qh = 0;
|
1126 |
link = qh.link; |
1127 |
} |
1128 |
} |
1129 |
break;
|
1130 |
|
1131 |
default:
|
1132 |
assert(!"unknown return code");
|
1133 |
} |
1134 |
|
1135 |
/* go to the next entry */
|
1136 |
} |
1137 |
|
1138 |
out:
|
1139 |
s->pending_int_mask |= int_mask; |
1140 |
} |
1141 |
|
1142 |
static void uhci_bh(void *opaque) |
1143 |
{ |
1144 |
UHCIState *s = opaque; |
1145 |
uhci_process_frame(s); |
1146 |
} |
1147 |
|
1148 |
static void uhci_frame_timer(void *opaque) |
1149 |
{ |
1150 |
UHCIState *s = opaque; |
1151 |
|
1152 |
/* prepare the timer for the next frame */
|
1153 |
s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); |
1154 |
s->frame_bytes = 0;
|
1155 |
qemu_bh_cancel(s->bh); |
1156 |
|
1157 |
if (!(s->cmd & UHCI_CMD_RS)) {
|
1158 |
/* Full stop */
|
1159 |
trace_usb_uhci_schedule_stop(); |
1160 |
qemu_del_timer(s->frame_timer); |
1161 |
uhci_async_cancel_all(s); |
1162 |
/* set hchalted bit in status - UHCI11D 2.1.2 */
|
1163 |
s->status |= UHCI_STS_HCHALTED; |
1164 |
return;
|
1165 |
} |
1166 |
|
1167 |
/* Complete the previous frame */
|
1168 |
if (s->pending_int_mask) {
|
1169 |
s->status2 |= s->pending_int_mask; |
1170 |
s->status |= UHCI_STS_USBINT; |
1171 |
uhci_update_irq(s); |
1172 |
} |
1173 |
s->pending_int_mask = 0;
|
1174 |
|
1175 |
/* Start new frame */
|
1176 |
s->frnum = (s->frnum + 1) & 0x7ff; |
1177 |
|
1178 |
trace_usb_uhci_frame_start(s->frnum); |
1179 |
|
1180 |
uhci_async_validate_begin(s); |
1181 |
|
1182 |
uhci_process_frame(s); |
1183 |
|
1184 |
uhci_async_validate_end(s); |
1185 |
|
1186 |
qemu_mod_timer(s->frame_timer, s->expire_time); |
1187 |
} |
1188 |
|
1189 |
static const MemoryRegionPortio uhci_portio[] = { |
1190 |
{ 0, 32, 2, .write = uhci_ioport_writew, }, |
1191 |
{ 0, 32, 2, .read = uhci_ioport_readw, }, |
1192 |
{ 0, 32, 4, .write = uhci_ioport_writel, }, |
1193 |
{ 0, 32, 4, .read = uhci_ioport_readl, }, |
1194 |
{ 0, 32, 1, .write = uhci_ioport_writeb, }, |
1195 |
{ 0, 32, 1, .read = uhci_ioport_readb, }, |
1196 |
PORTIO_END_OF_LIST() |
1197 |
}; |
1198 |
|
1199 |
static const MemoryRegionOps uhci_ioport_ops = { |
1200 |
.old_portio = uhci_portio, |
1201 |
}; |
1202 |
|
1203 |
static USBPortOps uhci_port_ops = {
|
1204 |
.attach = uhci_attach, |
1205 |
.detach = uhci_detach, |
1206 |
.child_detach = uhci_child_detach, |
1207 |
.wakeup = uhci_wakeup, |
1208 |
.complete = uhci_async_complete, |
1209 |
}; |
1210 |
|
1211 |
static USBBusOps uhci_bus_ops = {
|
1212 |
}; |
1213 |
|
1214 |
static int usb_uhci_common_initfn(PCIDevice *dev) |
1215 |
{ |
1216 |
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
1217 |
UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1218 |
uint8_t *pci_conf = s->dev.config; |
1219 |
int i;
|
1220 |
|
1221 |
pci_conf[PCI_CLASS_PROG] = 0x00;
|
1222 |
/* TODO: reset value should be 0. */
|
1223 |
pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
|
1224 |
|
1225 |
switch (pc->device_id) {
|
1226 |
case PCI_DEVICE_ID_INTEL_82801I_UHCI1:
|
1227 |
s->irq_pin = 0; /* A */ |
1228 |
break;
|
1229 |
case PCI_DEVICE_ID_INTEL_82801I_UHCI2:
|
1230 |
s->irq_pin = 1; /* B */ |
1231 |
break;
|
1232 |
case PCI_DEVICE_ID_INTEL_82801I_UHCI3:
|
1233 |
s->irq_pin = 2; /* C */ |
1234 |
break;
|
1235 |
default:
|
1236 |
s->irq_pin = 3; /* D */ |
1237 |
break;
|
1238 |
} |
1239 |
pci_config_set_interrupt_pin(pci_conf, s->irq_pin + 1);
|
1240 |
|
1241 |
if (s->masterbus) {
|
1242 |
USBPort *ports[NB_PORTS]; |
1243 |
for(i = 0; i < NB_PORTS; i++) { |
1244 |
ports[i] = &s->ports[i].port; |
1245 |
} |
1246 |
if (usb_register_companion(s->masterbus, ports, NB_PORTS,
|
1247 |
s->firstport, s, &uhci_port_ops, |
1248 |
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
|
1249 |
return -1; |
1250 |
} |
1251 |
} else {
|
1252 |
usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev); |
1253 |
for (i = 0; i < NB_PORTS; i++) { |
1254 |
usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, |
1255 |
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); |
1256 |
} |
1257 |
} |
1258 |
s->bh = qemu_bh_new(uhci_bh, s); |
1259 |
s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); |
1260 |
s->num_ports_vmstate = NB_PORTS; |
1261 |
QTAILQ_INIT(&s->queues); |
1262 |
|
1263 |
qemu_register_reset(uhci_reset, s); |
1264 |
|
1265 |
memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20); |
1266 |
/* Use region 4 for consistency with real hardware. BSD guests seem
|
1267 |
to rely on this. */
|
1268 |
pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
|
1269 |
|
1270 |
return 0; |
1271 |
} |
1272 |
|
1273 |
static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) |
1274 |
{ |
1275 |
UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1276 |
uint8_t *pci_conf = s->dev.config; |
1277 |
|
1278 |
/* USB misc control 1/2 */
|
1279 |
pci_set_long(pci_conf + 0x40,0x00001000); |
1280 |
/* PM capability */
|
1281 |
pci_set_long(pci_conf + 0x80,0x00020001); |
1282 |
/* USB legacy support */
|
1283 |
pci_set_long(pci_conf + 0xc0,0x00002000); |
1284 |
|
1285 |
return usb_uhci_common_initfn(dev);
|
1286 |
} |
1287 |
|
1288 |
static void usb_uhci_exit(PCIDevice *dev) |
1289 |
{ |
1290 |
UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1291 |
|
1292 |
memory_region_destroy(&s->io_bar); |
1293 |
} |
1294 |
|
1295 |
static Property uhci_properties[] = {
|
1296 |
DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
|
1297 |
DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), |
1298 |
DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), |
1299 |
DEFINE_PROP_END_OF_LIST(), |
1300 |
}; |
1301 |
|
1302 |
static void piix3_uhci_class_init(ObjectClass *klass, void *data) |
1303 |
{ |
1304 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1305 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1306 |
|
1307 |
k->init = usb_uhci_common_initfn; |
1308 |
k->exit = usb_uhci_exit; |
1309 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
1310 |
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2; |
1311 |
k->revision = 0x01;
|
1312 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1313 |
dc->vmsd = &vmstate_uhci; |
1314 |
dc->props = uhci_properties; |
1315 |
} |
1316 |
|
1317 |
static TypeInfo piix3_uhci_info = {
|
1318 |
.name = "piix3-usb-uhci",
|
1319 |
.parent = TYPE_PCI_DEVICE, |
1320 |
.instance_size = sizeof(UHCIState),
|
1321 |
.class_init = piix3_uhci_class_init, |
1322 |
}; |
1323 |
|
1324 |
static void piix4_uhci_class_init(ObjectClass *klass, void *data) |
1325 |
{ |
1326 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1327 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1328 |
|
1329 |
k->init = usb_uhci_common_initfn; |
1330 |
k->exit = usb_uhci_exit; |
1331 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
1332 |
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2; |
1333 |
k->revision = 0x01;
|
1334 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1335 |
dc->vmsd = &vmstate_uhci; |
1336 |
dc->props = uhci_properties; |
1337 |
} |
1338 |
|
1339 |
static TypeInfo piix4_uhci_info = {
|
1340 |
.name = "piix4-usb-uhci",
|
1341 |
.parent = TYPE_PCI_DEVICE, |
1342 |
.instance_size = sizeof(UHCIState),
|
1343 |
.class_init = piix4_uhci_class_init, |
1344 |
}; |
1345 |
|
1346 |
static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data) |
1347 |
{ |
1348 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1349 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1350 |
|
1351 |
k->init = usb_uhci_vt82c686b_initfn; |
1352 |
k->exit = usb_uhci_exit; |
1353 |
k->vendor_id = PCI_VENDOR_ID_VIA; |
1354 |
k->device_id = PCI_DEVICE_ID_VIA_UHCI; |
1355 |
k->revision = 0x01;
|
1356 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1357 |
dc->vmsd = &vmstate_uhci; |
1358 |
dc->props = uhci_properties; |
1359 |
} |
1360 |
|
1361 |
static TypeInfo vt82c686b_uhci_info = {
|
1362 |
.name = "vt82c686b-usb-uhci",
|
1363 |
.parent = TYPE_PCI_DEVICE, |
1364 |
.instance_size = sizeof(UHCIState),
|
1365 |
.class_init = vt82c686b_uhci_class_init, |
1366 |
}; |
1367 |
|
1368 |
static void ich9_uhci1_class_init(ObjectClass *klass, void *data) |
1369 |
{ |
1370 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1371 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1372 |
|
1373 |
k->init = usb_uhci_common_initfn; |
1374 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
1375 |
k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1; |
1376 |
k->revision = 0x03;
|
1377 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1378 |
dc->vmsd = &vmstate_uhci; |
1379 |
dc->props = uhci_properties; |
1380 |
} |
1381 |
|
1382 |
static TypeInfo ich9_uhci1_info = {
|
1383 |
.name = "ich9-usb-uhci1",
|
1384 |
.parent = TYPE_PCI_DEVICE, |
1385 |
.instance_size = sizeof(UHCIState),
|
1386 |
.class_init = ich9_uhci1_class_init, |
1387 |
}; |
1388 |
|
1389 |
static void ich9_uhci2_class_init(ObjectClass *klass, void *data) |
1390 |
{ |
1391 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1392 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1393 |
|
1394 |
k->init = usb_uhci_common_initfn; |
1395 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
1396 |
k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2; |
1397 |
k->revision = 0x03;
|
1398 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1399 |
dc->vmsd = &vmstate_uhci; |
1400 |
dc->props = uhci_properties; |
1401 |
} |
1402 |
|
1403 |
static TypeInfo ich9_uhci2_info = {
|
1404 |
.name = "ich9-usb-uhci2",
|
1405 |
.parent = TYPE_PCI_DEVICE, |
1406 |
.instance_size = sizeof(UHCIState),
|
1407 |
.class_init = ich9_uhci2_class_init, |
1408 |
}; |
1409 |
|
1410 |
static void ich9_uhci3_class_init(ObjectClass *klass, void *data) |
1411 |
{ |
1412 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1413 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1414 |
|
1415 |
k->init = usb_uhci_common_initfn; |
1416 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
1417 |
k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3; |
1418 |
k->revision = 0x03;
|
1419 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1420 |
dc->vmsd = &vmstate_uhci; |
1421 |
dc->props = uhci_properties; |
1422 |
} |
1423 |
|
1424 |
static TypeInfo ich9_uhci3_info = {
|
1425 |
.name = "ich9-usb-uhci3",
|
1426 |
.parent = TYPE_PCI_DEVICE, |
1427 |
.instance_size = sizeof(UHCIState),
|
1428 |
.class_init = ich9_uhci3_class_init, |
1429 |
}; |
1430 |
|
1431 |
static void uhci_register_types(void) |
1432 |
{ |
1433 |
type_register_static(&piix3_uhci_info); |
1434 |
type_register_static(&piix4_uhci_info); |
1435 |
type_register_static(&vt82c686b_uhci_info); |
1436 |
type_register_static(&ich9_uhci1_info); |
1437 |
type_register_static(&ich9_uhci2_info); |
1438 |
type_register_static(&ich9_uhci3_info); |
1439 |
} |
1440 |
|
1441 |
type_init(uhci_register_types) |