Revision 01546fa6

b/hw/usb/hcd-xhci.c
380 380
    XHCISlot slots[MAXSLOTS];
381 381

  
382 382
    /* Runtime Registers */
383
    uint32_t mfindex;
384
    /* note: we only support one interrupter */
385 383
    uint32_t iman;
386 384
    uint32_t imod;
387 385
    uint32_t erstsz;
......
390 388
    uint32_t erdp_low;
391 389
    uint32_t erdp_high;
392 390

  
391
    int64_t mfindex_start;
392
    QEMUTimer *mfwrap_timer;
393

  
393 394
    dma_addr_t er_start;
394 395
    uint32_t er_size;
395 396
    bool er_pcs;
......
410 411
    uint32_t rsvd;
411 412
} XHCIEvRingSeg;
412 413

  
414
static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
415
                         unsigned int epid);
416
static void xhci_event(XHCIState *xhci, XHCIEvent *event);
417
static void xhci_write_event(XHCIState *xhci, XHCIEvent *event);
418

  
413 419
static const char *TRBType_names[] = {
414 420
    [TRB_RESERVED]                     = "TRB_RESERVED",
415 421
    [TR_NORMAL]                        = "TR_NORMAL",
......
462 468
                       ARRAY_SIZE(TRBType_names));
463 469
}
464 470

  
465
static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
466
                         unsigned int epid);
471
static uint64_t xhci_mfindex_get(XHCIState *xhci)
472
{
473
    int64_t now = qemu_get_clock_ns(vm_clock);
474
    return (now - xhci->mfindex_start) / 125000;
475
}
476

  
477
static void xhci_mfwrap_update(XHCIState *xhci)
478
{
479
    const uint32_t bits = USBCMD_RS | USBCMD_EWE;
480
    uint32_t mfindex, left;
481
    int64_t now;
482

  
483
    if ((xhci->usbcmd & bits) == bits) {
484
        now = qemu_get_clock_ns(vm_clock);
485
        mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
486
        left = 0x4000 - mfindex;
487
        qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000);
488
    } else {
489
        qemu_del_timer(xhci->mfwrap_timer);
490
    }
491
}
492

  
493
static void xhci_mfwrap_timer(void *opaque)
494
{
495
    XHCIState *xhci = opaque;
496
    XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
497

  
498
    xhci_event(xhci, &wrap);
499
    xhci_mfwrap_update(xhci);
500
}
467 501

  
468 502
static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
469 503
{
......
793 827
{
794 828
    trace_usb_xhci_run();
795 829
    xhci->usbsts &= ~USBSTS_HCH;
830
    xhci->mfindex_start = qemu_get_clock_ns(vm_clock);
796 831
}
797 832

  
798 833
static void xhci_stop(XHCIState *xhci)
......
2048 2083
        xhci_update_port(xhci, xhci->ports + i, 0);
2049 2084
    }
2050 2085

  
2051
    xhci->mfindex = 0;
2052 2086
    xhci->iman = 0;
2053 2087
    xhci->imod = 0;
2054 2088
    xhci->erstsz = 0;
......
2062 2096
    xhci->er_full = 0;
2063 2097
    xhci->ev_buffer_put = 0;
2064 2098
    xhci->ev_buffer_get = 0;
2099

  
2100
    xhci->mfindex_start = qemu_get_clock_ns(vm_clock);
2101
    xhci_mfwrap_update(xhci);
2065 2102
}
2066 2103

  
2067 2104
static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
......
2264 2301
            xhci_stop(xhci);
2265 2302
        }
2266 2303
        xhci->usbcmd = val & 0xc0f;
2304
        xhci_mfwrap_update(xhci);
2267 2305
        if (val & USBCMD_HCRST) {
2268 2306
            xhci_reset(&xhci->pci_dev.qdev);
2269 2307
        }
......
2315 2353

  
2316 2354
    switch (reg) {
2317 2355
    case 0x00: /* MFINDEX */
2318
        fprintf(stderr, "xhci_runtime_read: MFINDEX not yet implemented\n");
2319
        ret = xhci->mfindex;
2356
        ret = xhci_mfindex_get(xhci) & 0x3fff;
2320 2357
        break;
2321 2358
    case 0x20: /* IMAN */
2322 2359
        ret = xhci->iman;
......
2616 2653

  
2617 2654
    usb_xhci_init(xhci, &dev->qdev);
2618 2655

  
2656
    xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci);
2657

  
2619 2658
    xhci->irq = xhci->pci_dev.irq[0];
2620 2659

  
2621 2660
    memory_region_init_io(&xhci->mem, &xhci_mem_ops, xhci,

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