root / hw / usb / hcd-ehci.c @ 01e26b0e
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/*
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* QEMU USB EHCI Emulation
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*
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* Copyright(c) 2008 Emutex Ltd. (address@hidden)
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* Copyright(c) 2011-2012 Red Hat, Inc.
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*
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* Red Hat Authors:
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* Gerd Hoffmann <kraxel@redhat.com>
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* Hans de Goede <hdegoede@redhat.com>
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*
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* EHCI project was started by Mark Burkley, with contributions by
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* Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
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* Jan Kiszka and Vincent Palatin contributed bugfixes.
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*
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or(at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/usb/hcd-ehci.h" |
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/* Capability Registers Base Address - section 2.2 */
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#define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */ |
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#define HCIVERSION 0x0002 /* 2-bytes, i/f version # */ |
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#define HCSPARAMS 0x0004 /* 4-bytes, structural params */ |
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#define HCCPARAMS 0x0008 /* 4-bytes, capability params */ |
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#define EECP HCCPARAMS + 1 |
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#define HCSPPORTROUTE1 0x000c |
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#define HCSPPORTROUTE2 0x0010 |
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|
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#define USBCMD 0x0000 |
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#define USBCMD_RUNSTOP (1 << 0) // run / Stop |
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#define USBCMD_HCRESET (1 << 1) // HC Reset |
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#define USBCMD_FLS (3 << 2) // Frame List Size |
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#define USBCMD_FLS_SH 2 // Frame List Size Shift |
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#define USBCMD_PSE (1 << 4) // Periodic Schedule Enable |
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#define USBCMD_ASE (1 << 5) // Asynch Schedule Enable |
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#define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell |
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#define USBCMD_LHCR (1 << 7) // Light Host Controller Reset |
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#define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count |
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#define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable |
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#define USBCMD_ITC (0x7f << 16) // Int Threshold Control |
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#define USBCMD_ITC_SH 16 // Int Threshold Control Shift |
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|
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#define USBSTS 0x0004 |
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#define USBSTS_RO_MASK 0x0000003f |
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#define USBSTS_INT (1 << 0) // USB Interrupt |
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#define USBSTS_ERRINT (1 << 1) // Error Interrupt |
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#define USBSTS_PCD (1 << 2) // Port Change Detect |
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#define USBSTS_FLR (1 << 3) // Frame List Rollover |
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#define USBSTS_HSE (1 << 4) // Host System Error |
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#define USBSTS_IAA (1 << 5) // Interrupt on Async Advance |
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#define USBSTS_HALT (1 << 12) // HC Halted |
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#define USBSTS_REC (1 << 13) // Reclamation |
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#define USBSTS_PSS (1 << 14) // Periodic Schedule Status |
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#define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status |
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/*
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* Interrupt enable bits correspond to the interrupt active bits in USBSTS
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* so no need to redefine here.
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*/
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#define USBINTR 0x0008 |
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#define USBINTR_MASK 0x0000003f |
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#define FRINDEX 0x000c |
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#define CTRLDSSEGMENT 0x0010 |
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#define PERIODICLISTBASE 0x0014 |
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#define ASYNCLISTADDR 0x0018 |
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#define ASYNCLISTADDR_MASK 0xffffffe0 |
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#define CONFIGFLAG 0x0040 |
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/*
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* Bits that are reserved or are read-only are masked out of values
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* written to us by software
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*/
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#define PORTSC_RO_MASK 0x007001c0 |
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#define PORTSC_RWC_MASK 0x0000002a |
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#define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable |
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#define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable |
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#define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable |
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#define PORTSC_PTC (15 << 16) // Port Test Control |
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#define PORTSC_PTC_SH 16 // Port Test Control shift |
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#define PORTSC_PIC (3 << 14) // Port Indicator Control |
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#define PORTSC_PIC_SH 14 // Port Indicator Control Shift |
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#define PORTSC_POWNER (1 << 13) // Port Owner |
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#define PORTSC_PPOWER (1 << 12) // Port Power |
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#define PORTSC_LINESTAT (3 << 10) // Port Line Status |
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#define PORTSC_LINESTAT_SH 10 // Port Line Status Shift |
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#define PORTSC_PRESET (1 << 8) // Port Reset |
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#define PORTSC_SUSPEND (1 << 7) // Port Suspend |
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#define PORTSC_FPRES (1 << 6) // Force Port Resume |
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#define PORTSC_OCC (1 << 5) // Over Current Change |
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#define PORTSC_OCA (1 << 4) // Over Current Active |
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#define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change |
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#define PORTSC_PED (1 << 2) // Port Enable/Disable |
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#define PORTSC_CSC (1 << 1) // Connect Status Change |
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#define PORTSC_CONNECT (1 << 0) // Current Connect Status |
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#define FRAME_TIMER_FREQ 1000 |
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#define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) |
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#define NB_MAXINTRATE 8 // Max rate at which controller issues ints |
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#define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction |
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#define MAX_QH 100 // Max allowable queue heads in a chain |
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#define MIN_FR_PER_TICK 3 // Min frames to process when catching up |
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/* Internal periodic / asynchronous schedule state machine states
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*/
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typedef enum { |
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EST_INACTIVE = 1000,
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EST_ACTIVE, |
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EST_EXECUTING, |
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EST_SLEEPING, |
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/* The following states are internal to the state machine function
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*/
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EST_WAITLISTHEAD, |
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EST_FETCHENTRY, |
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EST_FETCHQH, |
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EST_FETCHITD, |
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EST_FETCHSITD, |
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EST_ADVANCEQUEUE, |
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EST_FETCHQTD, |
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EST_EXECUTE, |
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EST_WRITEBACK, |
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EST_HORIZONTALQH |
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} EHCI_STATES; |
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/* macros for accessing fields within next link pointer entry */
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#define NLPTR_GET(x) ((x) & 0xffffffe0) |
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#define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) |
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#define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid |
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/* link pointer types */
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#define NLPTR_TYPE_ITD 0 // isoc xfer descriptor |
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#define NLPTR_TYPE_QH 1 // queue head |
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#define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor |
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#define NLPTR_TYPE_FSTN 3 // frame span traversal node |
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#define SET_LAST_RUN_CLOCK(s) \
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(s)->last_run_ns = qemu_get_clock_ns(vm_clock); |
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/* nifty macros from Arnon's EHCI version */
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#define get_field(data, field) \
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(((data) & field##_MASK) >> field##_SH) |
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#define set_field(data, newval, field) do { \ |
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uint32_t val = *data; \ |
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val &= ~ field##_MASK; \ |
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val |= ((newval) << field##_SH) & field##_MASK; \ |
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*data = val; \ |
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} while(0) |
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static const char *ehci_state_names[] = { |
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[EST_INACTIVE] = "INACTIVE",
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[EST_ACTIVE] = "ACTIVE",
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[EST_EXECUTING] = "EXECUTING",
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[EST_SLEEPING] = "SLEEPING",
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[EST_WAITLISTHEAD] = "WAITLISTHEAD",
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[EST_FETCHENTRY] = "FETCH ENTRY",
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[EST_FETCHQH] = "FETCH QH",
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[EST_FETCHITD] = "FETCH ITD",
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[EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
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[EST_FETCHQTD] = "FETCH QTD",
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[EST_EXECUTE] = "EXECUTE",
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[EST_WRITEBACK] = "WRITEBACK",
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[EST_HORIZONTALQH] = "HORIZONTALQH",
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}; |
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static const char *ehci_mmio_names[] = { |
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[USBCMD] = "USBCMD",
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[USBSTS] = "USBSTS",
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[USBINTR] = "USBINTR",
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[FRINDEX] = "FRINDEX",
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[PERIODICLISTBASE] = "P-LIST BASE",
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[ASYNCLISTADDR] = "A-LIST ADDR",
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[CONFIGFLAG] = "CONFIGFLAG",
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}; |
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static int ehci_state_executing(EHCIQueue *q); |
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static int ehci_state_writeback(EHCIQueue *q); |
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static int ehci_fill_queue(EHCIPacket *p); |
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static const char *nr2str(const char **n, size_t len, uint32_t nr) |
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{ |
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if (nr < len && n[nr] != NULL) { |
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return n[nr];
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} else {
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return "unknown"; |
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} |
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} |
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static const char *state2str(uint32_t state) |
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{ |
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return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
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} |
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static const char *addr2str(hwaddr addr) |
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{ |
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return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
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} |
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static void ehci_trace_usbsts(uint32_t mask, int state) |
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{ |
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/* interrupts */
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if (mask & USBSTS_INT) {
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trace_usb_ehci_usbsts("INT", state);
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} |
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if (mask & USBSTS_ERRINT) {
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trace_usb_ehci_usbsts("ERRINT", state);
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} |
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if (mask & USBSTS_PCD) {
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trace_usb_ehci_usbsts("PCD", state);
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} |
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if (mask & USBSTS_FLR) {
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trace_usb_ehci_usbsts("FLR", state);
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} |
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if (mask & USBSTS_HSE) {
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trace_usb_ehci_usbsts("HSE", state);
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} |
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if (mask & USBSTS_IAA) {
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trace_usb_ehci_usbsts("IAA", state);
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} |
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/* status */
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if (mask & USBSTS_HALT) {
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trace_usb_ehci_usbsts("HALT", state);
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} |
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if (mask & USBSTS_REC) {
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trace_usb_ehci_usbsts("REC", state);
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} |
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if (mask & USBSTS_PSS) {
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trace_usb_ehci_usbsts("PSS", state);
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} |
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if (mask & USBSTS_ASS) {
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trace_usb_ehci_usbsts("ASS", state);
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} |
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} |
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static inline void ehci_set_usbsts(EHCIState *s, int mask) |
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{ |
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if ((s->usbsts & mask) == mask) {
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return;
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} |
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ehci_trace_usbsts(mask, 1);
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s->usbsts |= mask; |
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} |
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static inline void ehci_clear_usbsts(EHCIState *s, int mask) |
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{ |
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if ((s->usbsts & mask) == 0) { |
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return;
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} |
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ehci_trace_usbsts(mask, 0);
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s->usbsts &= ~mask; |
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} |
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/* update irq line */
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static inline void ehci_update_irq(EHCIState *s) |
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{ |
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int level = 0; |
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if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
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level = 1;
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} |
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trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr); |
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qemu_set_irq(s->irq, level); |
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} |
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/* flag interrupt condition */
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static inline void ehci_raise_irq(EHCIState *s, int intr) |
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{ |
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if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) {
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s->usbsts |= intr; |
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ehci_update_irq(s); |
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} else {
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s->usbsts_pending |= intr; |
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} |
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} |
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/*
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* Commit pending interrupts (added via ehci_raise_irq),
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* at the rate allowed by "Interrupt Threshold Control".
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*/
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static inline void ehci_commit_irq(EHCIState *s) |
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{ |
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uint32_t itc; |
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if (!s->usbsts_pending) {
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return;
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} |
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if (s->usbsts_frindex > s->frindex) {
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return;
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} |
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itc = (s->usbcmd >> 16) & 0xff; |
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s->usbsts |= s->usbsts_pending; |
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s->usbsts_pending = 0;
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s->usbsts_frindex = s->frindex + itc; |
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ehci_update_irq(s); |
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} |
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static void ehci_update_halt(EHCIState *s) |
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{ |
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if (s->usbcmd & USBCMD_RUNSTOP) {
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ehci_clear_usbsts(s, USBSTS_HALT); |
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} else {
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if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) {
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ehci_set_usbsts(s, USBSTS_HALT); |
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} |
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} |
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} |
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static void ehci_set_state(EHCIState *s, int async, int state) |
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{ |
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if (async) {
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trace_usb_ehci_state("async", state2str(state));
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s->astate = state; |
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if (s->astate == EST_INACTIVE) {
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ehci_clear_usbsts(s, USBSTS_ASS); |
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ehci_update_halt(s); |
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} else {
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ehci_set_usbsts(s, USBSTS_ASS); |
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} |
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} else {
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trace_usb_ehci_state("periodic", state2str(state));
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s->pstate = state; |
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if (s->pstate == EST_INACTIVE) {
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ehci_clear_usbsts(s, USBSTS_PSS); |
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ehci_update_halt(s); |
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} else {
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ehci_set_usbsts(s, USBSTS_PSS); |
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} |
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} |
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} |
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static int ehci_get_state(EHCIState *s, int async) |
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{ |
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return async ? s->astate : s->pstate;
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} |
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static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) |
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{ |
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if (async) {
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s->a_fetch_addr = addr; |
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} else {
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s->p_fetch_addr = addr; |
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} |
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} |
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static int ehci_get_fetch_addr(EHCIState *s, int async) |
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{ |
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return async ? s->a_fetch_addr : s->p_fetch_addr;
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} |
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static void ehci_trace_qh(EHCIQueue *q, hwaddr addr, EHCIqh *qh) |
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{ |
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/* need three here due to argument count limits */
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trace_usb_ehci_qh_ptrs(q, addr, qh->next, |
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qh->current_qtd, qh->next_qtd, qh->altnext_qtd); |
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trace_usb_ehci_qh_fields(addr, |
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get_field(qh->epchar, QH_EPCHAR_RL), |
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get_field(qh->epchar, QH_EPCHAR_MPLEN), |
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get_field(qh->epchar, QH_EPCHAR_EPS), |
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get_field(qh->epchar, QH_EPCHAR_EP), |
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get_field(qh->epchar, QH_EPCHAR_DEVADDR)); |
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trace_usb_ehci_qh_bits(addr, |
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(bool)(qh->epchar & QH_EPCHAR_C),
|
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(bool)(qh->epchar & QH_EPCHAR_H),
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(bool)(qh->epchar & QH_EPCHAR_DTC),
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(bool)(qh->epchar & QH_EPCHAR_I));
|
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} |
384 |
|
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static void ehci_trace_qtd(EHCIQueue *q, hwaddr addr, EHCIqtd *qtd) |
386 |
{ |
387 |
/* need three here due to argument count limits */
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trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); |
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trace_usb_ehci_qtd_fields(addr, |
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get_field(qtd->token, QTD_TOKEN_TBYTES), |
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get_field(qtd->token, QTD_TOKEN_CPAGE), |
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get_field(qtd->token, QTD_TOKEN_CERR), |
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get_field(qtd->token, QTD_TOKEN_PID)); |
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trace_usb_ehci_qtd_bits(addr, |
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(bool)(qtd->token & QTD_TOKEN_IOC),
|
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(bool)(qtd->token & QTD_TOKEN_ACTIVE),
|
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(bool)(qtd->token & QTD_TOKEN_HALT),
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(bool)(qtd->token & QTD_TOKEN_BABBLE),
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(bool)(qtd->token & QTD_TOKEN_XACTERR));
|
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} |
401 |
|
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static void ehci_trace_itd(EHCIState *s, hwaddr addr, EHCIitd *itd) |
403 |
{ |
404 |
trace_usb_ehci_itd(addr, itd->next, |
405 |
get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
|
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get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
|
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get_field(itd->bufptr[0], ITD_BUFPTR_EP),
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get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
|
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} |
410 |
|
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static void ehci_trace_sitd(EHCIState *s, hwaddr addr, |
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EHCIsitd *sitd) |
413 |
{ |
414 |
trace_usb_ehci_sitd(addr, sitd->next, |
415 |
(bool)(sitd->results & SITD_RESULTS_ACTIVE));
|
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} |
417 |
|
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static void ehci_trace_guest_bug(EHCIState *s, const char *message) |
419 |
{ |
420 |
trace_usb_ehci_guest_bug(message); |
421 |
fprintf(stderr, "ehci warning: %s\n", message);
|
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} |
423 |
|
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static inline bool ehci_enabled(EHCIState *s) |
425 |
{ |
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return s->usbcmd & USBCMD_RUNSTOP;
|
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} |
428 |
|
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static inline bool ehci_async_enabled(EHCIState *s) |
430 |
{ |
431 |
return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE);
|
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} |
433 |
|
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static inline bool ehci_periodic_enabled(EHCIState *s) |
435 |
{ |
436 |
return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE);
|
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} |
438 |
|
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/* packet management */
|
440 |
|
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static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
|
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{ |
443 |
EHCIPacket *p; |
444 |
|
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p = g_new0(EHCIPacket, 1);
|
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p->queue = q; |
447 |
usb_packet_init(&p->packet); |
448 |
QTAILQ_INSERT_TAIL(&q->packets, p, next); |
449 |
trace_usb_ehci_packet_action(p->queue, p, "alloc");
|
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return p;
|
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} |
452 |
|
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static void ehci_free_packet(EHCIPacket *p) |
454 |
{ |
455 |
if (p->async == EHCI_ASYNC_FINISHED) {
|
456 |
int state = ehci_get_state(p->queue->ehci, p->queue->async);
|
457 |
/* This is a normal, but rare condition (cancel racing completion) */
|
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fprintf(stderr, "EHCI: Warning packet completed but not processed\n");
|
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ehci_state_executing(p->queue); |
460 |
ehci_state_writeback(p->queue); |
461 |
ehci_set_state(p->queue->ehci, p->queue->async, state); |
462 |
/* state_writeback recurses into us with async == EHCI_ASYNC_NONE!! */
|
463 |
return;
|
464 |
} |
465 |
trace_usb_ehci_packet_action(p->queue, p, "free");
|
466 |
if (p->async == EHCI_ASYNC_INITIALIZED) {
|
467 |
usb_packet_unmap(&p->packet, &p->sgl); |
468 |
qemu_sglist_destroy(&p->sgl); |
469 |
} |
470 |
if (p->async == EHCI_ASYNC_INFLIGHT) {
|
471 |
usb_cancel_packet(&p->packet); |
472 |
usb_packet_unmap(&p->packet, &p->sgl); |
473 |
qemu_sglist_destroy(&p->sgl); |
474 |
} |
475 |
QTAILQ_REMOVE(&p->queue->packets, p, next); |
476 |
usb_packet_cleanup(&p->packet); |
477 |
g_free(p); |
478 |
} |
479 |
|
480 |
/* queue management */
|
481 |
|
482 |
static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async) |
483 |
{ |
484 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
485 |
EHCIQueue *q; |
486 |
|
487 |
q = g_malloc0(sizeof(*q));
|
488 |
q->ehci = ehci; |
489 |
q->qhaddr = addr; |
490 |
q->async = async; |
491 |
QTAILQ_INIT(&q->packets); |
492 |
QTAILQ_INSERT_HEAD(head, q, next); |
493 |
trace_usb_ehci_queue_action(q, "alloc");
|
494 |
return q;
|
495 |
} |
496 |
|
497 |
static int ehci_cancel_queue(EHCIQueue *q) |
498 |
{ |
499 |
EHCIPacket *p; |
500 |
int packets = 0; |
501 |
|
502 |
p = QTAILQ_FIRST(&q->packets); |
503 |
if (p == NULL) { |
504 |
return 0; |
505 |
} |
506 |
|
507 |
trace_usb_ehci_queue_action(q, "cancel");
|
508 |
do {
|
509 |
ehci_free_packet(p); |
510 |
packets++; |
511 |
} while ((p = QTAILQ_FIRST(&q->packets)) != NULL); |
512 |
return packets;
|
513 |
} |
514 |
|
515 |
static int ehci_reset_queue(EHCIQueue *q) |
516 |
{ |
517 |
int packets;
|
518 |
|
519 |
trace_usb_ehci_queue_action(q, "reset");
|
520 |
packets = ehci_cancel_queue(q); |
521 |
q->dev = NULL;
|
522 |
q->qtdaddr = 0;
|
523 |
return packets;
|
524 |
} |
525 |
|
526 |
static void ehci_free_queue(EHCIQueue *q, const char *warn) |
527 |
{ |
528 |
EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues; |
529 |
int cancelled;
|
530 |
|
531 |
trace_usb_ehci_queue_action(q, "free");
|
532 |
cancelled = ehci_cancel_queue(q); |
533 |
if (warn && cancelled > 0) { |
534 |
ehci_trace_guest_bug(q->ehci, warn); |
535 |
} |
536 |
QTAILQ_REMOVE(head, q, next); |
537 |
g_free(q); |
538 |
} |
539 |
|
540 |
static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
|
541 |
int async)
|
542 |
{ |
543 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
544 |
EHCIQueue *q; |
545 |
|
546 |
QTAILQ_FOREACH(q, head, next) { |
547 |
if (addr == q->qhaddr) {
|
548 |
return q;
|
549 |
} |
550 |
} |
551 |
return NULL; |
552 |
} |
553 |
|
554 |
static void ehci_queues_rip_unused(EHCIState *ehci, int async) |
555 |
{ |
556 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
557 |
const char *warn = async ? "guest unlinked busy QH" : NULL; |
558 |
uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4;
|
559 |
EHCIQueue *q, *tmp; |
560 |
|
561 |
QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
562 |
if (q->seen) {
|
563 |
q->seen = 0;
|
564 |
q->ts = ehci->last_run_ns; |
565 |
continue;
|
566 |
} |
567 |
if (ehci->last_run_ns < q->ts + maxage) {
|
568 |
continue;
|
569 |
} |
570 |
ehci_free_queue(q, warn); |
571 |
} |
572 |
} |
573 |
|
574 |
static void ehci_queues_rip_unseen(EHCIState *ehci, int async) |
575 |
{ |
576 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
577 |
EHCIQueue *q, *tmp; |
578 |
|
579 |
QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
580 |
if (!q->seen) {
|
581 |
ehci_free_queue(q, NULL);
|
582 |
} |
583 |
} |
584 |
} |
585 |
|
586 |
static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async) |
587 |
{ |
588 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
589 |
EHCIQueue *q, *tmp; |
590 |
|
591 |
QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
592 |
if (q->dev != dev) {
|
593 |
continue;
|
594 |
} |
595 |
ehci_free_queue(q, NULL);
|
596 |
} |
597 |
} |
598 |
|
599 |
static void ehci_queues_rip_all(EHCIState *ehci, int async) |
600 |
{ |
601 |
EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
602 |
const char *warn = async ? "guest stopped busy async schedule" : NULL; |
603 |
EHCIQueue *q, *tmp; |
604 |
|
605 |
QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
606 |
ehci_free_queue(q, warn); |
607 |
} |
608 |
} |
609 |
|
610 |
/* Attach or detach a device on root hub */
|
611 |
|
612 |
static void ehci_attach(USBPort *port) |
613 |
{ |
614 |
EHCIState *s = port->opaque; |
615 |
uint32_t *portsc = &s->portsc[port->index]; |
616 |
const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; |
617 |
|
618 |
trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc); |
619 |
|
620 |
if (*portsc & PORTSC_POWNER) {
|
621 |
USBPort *companion = s->companion_ports[port->index]; |
622 |
companion->dev = port->dev; |
623 |
companion->ops->attach(companion); |
624 |
return;
|
625 |
} |
626 |
|
627 |
*portsc |= PORTSC_CONNECT; |
628 |
*portsc |= PORTSC_CSC; |
629 |
|
630 |
ehci_raise_irq(s, USBSTS_PCD); |
631 |
ehci_commit_irq(s); |
632 |
} |
633 |
|
634 |
static void ehci_detach(USBPort *port) |
635 |
{ |
636 |
EHCIState *s = port->opaque; |
637 |
uint32_t *portsc = &s->portsc[port->index]; |
638 |
const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; |
639 |
|
640 |
trace_usb_ehci_port_detach(port->index, owner); |
641 |
|
642 |
if (*portsc & PORTSC_POWNER) {
|
643 |
USBPort *companion = s->companion_ports[port->index]; |
644 |
companion->ops->detach(companion); |
645 |
companion->dev = NULL;
|
646 |
/*
|
647 |
* EHCI spec 4.2.2: "When a disconnect occurs... On the event,
|
648 |
* the port ownership is returned immediately to the EHCI controller."
|
649 |
*/
|
650 |
*portsc &= ~PORTSC_POWNER; |
651 |
return;
|
652 |
} |
653 |
|
654 |
ehci_queues_rip_device(s, port->dev, 0);
|
655 |
ehci_queues_rip_device(s, port->dev, 1);
|
656 |
|
657 |
*portsc &= ~(PORTSC_CONNECT|PORTSC_PED); |
658 |
*portsc |= PORTSC_CSC; |
659 |
|
660 |
ehci_raise_irq(s, USBSTS_PCD); |
661 |
ehci_commit_irq(s); |
662 |
} |
663 |
|
664 |
static void ehci_child_detach(USBPort *port, USBDevice *child) |
665 |
{ |
666 |
EHCIState *s = port->opaque; |
667 |
uint32_t portsc = s->portsc[port->index]; |
668 |
|
669 |
if (portsc & PORTSC_POWNER) {
|
670 |
USBPort *companion = s->companion_ports[port->index]; |
671 |
companion->ops->child_detach(companion, child); |
672 |
return;
|
673 |
} |
674 |
|
675 |
ehci_queues_rip_device(s, child, 0);
|
676 |
ehci_queues_rip_device(s, child, 1);
|
677 |
} |
678 |
|
679 |
static void ehci_wakeup(USBPort *port) |
680 |
{ |
681 |
EHCIState *s = port->opaque; |
682 |
uint32_t portsc = s->portsc[port->index]; |
683 |
|
684 |
if (portsc & PORTSC_POWNER) {
|
685 |
USBPort *companion = s->companion_ports[port->index]; |
686 |
if (companion->ops->wakeup) {
|
687 |
companion->ops->wakeup(companion); |
688 |
} |
689 |
return;
|
690 |
} |
691 |
|
692 |
qemu_bh_schedule(s->async_bh); |
693 |
} |
694 |
|
695 |
static int ehci_register_companion(USBBus *bus, USBPort *ports[], |
696 |
uint32_t portcount, uint32_t firstport) |
697 |
{ |
698 |
EHCIState *s = container_of(bus, EHCIState, bus); |
699 |
uint32_t i; |
700 |
|
701 |
if (firstport + portcount > NB_PORTS) {
|
702 |
qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
|
703 |
"firstport on masterbus");
|
704 |
error_printf_unless_qmp( |
705 |
"firstport value of %u makes companion take ports %u - %u, which "
|
706 |
"is outside of the valid range of 0 - %u\n", firstport, firstport,
|
707 |
firstport + portcount - 1, NB_PORTS - 1); |
708 |
return -1; |
709 |
} |
710 |
|
711 |
for (i = 0; i < portcount; i++) { |
712 |
if (s->companion_ports[firstport + i]) {
|
713 |
qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
|
714 |
"an USB masterbus");
|
715 |
error_printf_unless_qmp( |
716 |
"port %u on masterbus %s already has a companion assigned\n",
|
717 |
firstport + i, bus->qbus.name); |
718 |
return -1; |
719 |
} |
720 |
} |
721 |
|
722 |
for (i = 0; i < portcount; i++) { |
723 |
s->companion_ports[firstport + i] = ports[i]; |
724 |
s->ports[firstport + i].speedmask |= |
725 |
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; |
726 |
/* Ensure devs attached before the initial reset go to the companion */
|
727 |
s->portsc[firstport + i] = PORTSC_POWNER; |
728 |
} |
729 |
|
730 |
s->companion_count++; |
731 |
s->caps[0x05] = (s->companion_count << 4) | portcount; |
732 |
|
733 |
return 0; |
734 |
} |
735 |
|
736 |
static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
|
737 |
{ |
738 |
USBDevice *dev; |
739 |
USBPort *port; |
740 |
int i;
|
741 |
|
742 |
for (i = 0; i < NB_PORTS; i++) { |
743 |
port = &ehci->ports[i]; |
744 |
if (!(ehci->portsc[i] & PORTSC_PED)) {
|
745 |
DPRINTF("Port %d not enabled\n", i);
|
746 |
continue;
|
747 |
} |
748 |
dev = usb_find_device(port, addr); |
749 |
if (dev != NULL) { |
750 |
return dev;
|
751 |
} |
752 |
} |
753 |
return NULL; |
754 |
} |
755 |
|
756 |
/* 4.1 host controller initialization */
|
757 |
static void ehci_reset(void *opaque) |
758 |
{ |
759 |
EHCIState *s = opaque; |
760 |
int i;
|
761 |
USBDevice *devs[NB_PORTS]; |
762 |
|
763 |
trace_usb_ehci_reset(); |
764 |
|
765 |
/*
|
766 |
* Do the detach before touching portsc, so that it correctly gets send to
|
767 |
* us or to our companion based on PORTSC_POWNER before the reset.
|
768 |
*/
|
769 |
for(i = 0; i < NB_PORTS; i++) { |
770 |
devs[i] = s->ports[i].dev; |
771 |
if (devs[i] && devs[i]->attached) {
|
772 |
usb_detach(&s->ports[i]); |
773 |
} |
774 |
} |
775 |
|
776 |
memset(&s->opreg, 0x00, sizeof(s->opreg)); |
777 |
memset(&s->portsc, 0x00, sizeof(s->portsc)); |
778 |
|
779 |
s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; |
780 |
s->usbsts = USBSTS_HALT; |
781 |
s->usbsts_pending = 0;
|
782 |
s->usbsts_frindex = 0;
|
783 |
|
784 |
s->astate = EST_INACTIVE; |
785 |
s->pstate = EST_INACTIVE; |
786 |
|
787 |
for(i = 0; i < NB_PORTS; i++) { |
788 |
if (s->companion_ports[i]) {
|
789 |
s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; |
790 |
} else {
|
791 |
s->portsc[i] = PORTSC_PPOWER; |
792 |
} |
793 |
if (devs[i] && devs[i]->attached) {
|
794 |
usb_attach(&s->ports[i]); |
795 |
usb_device_reset(devs[i]); |
796 |
} |
797 |
} |
798 |
ehci_queues_rip_all(s, 0);
|
799 |
ehci_queues_rip_all(s, 1);
|
800 |
qemu_del_timer(s->frame_timer); |
801 |
qemu_bh_cancel(s->async_bh); |
802 |
} |
803 |
|
804 |
static uint64_t ehci_caps_read(void *ptr, hwaddr addr, |
805 |
unsigned size)
|
806 |
{ |
807 |
EHCIState *s = ptr; |
808 |
return s->caps[addr];
|
809 |
} |
810 |
|
811 |
static uint64_t ehci_opreg_read(void *ptr, hwaddr addr, |
812 |
unsigned size)
|
813 |
{ |
814 |
EHCIState *s = ptr; |
815 |
uint32_t val; |
816 |
|
817 |
val = s->opreg[addr >> 2];
|
818 |
trace_usb_ehci_opreg_read(addr + s->opregbase, addr2str(addr), val); |
819 |
return val;
|
820 |
} |
821 |
|
822 |
static uint64_t ehci_port_read(void *ptr, hwaddr addr, |
823 |
unsigned size)
|
824 |
{ |
825 |
EHCIState *s = ptr; |
826 |
uint32_t val; |
827 |
|
828 |
val = s->portsc[addr >> 2];
|
829 |
trace_usb_ehci_portsc_read(addr + PORTSC_BEGIN, addr >> 2, val);
|
830 |
return val;
|
831 |
} |
832 |
|
833 |
static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) |
834 |
{ |
835 |
USBDevice *dev = s->ports[port].dev; |
836 |
uint32_t *portsc = &s->portsc[port]; |
837 |
uint32_t orig; |
838 |
|
839 |
if (s->companion_ports[port] == NULL) |
840 |
return;
|
841 |
|
842 |
owner = owner & PORTSC_POWNER; |
843 |
orig = *portsc & PORTSC_POWNER; |
844 |
|
845 |
if (!(owner ^ orig)) {
|
846 |
return;
|
847 |
} |
848 |
|
849 |
if (dev && dev->attached) {
|
850 |
usb_detach(&s->ports[port]); |
851 |
} |
852 |
|
853 |
*portsc &= ~PORTSC_POWNER; |
854 |
*portsc |= owner; |
855 |
|
856 |
if (dev && dev->attached) {
|
857 |
usb_attach(&s->ports[port]); |
858 |
} |
859 |
} |
860 |
|
861 |
static void ehci_port_write(void *ptr, hwaddr addr, |
862 |
uint64_t val, unsigned size)
|
863 |
{ |
864 |
EHCIState *s = ptr; |
865 |
int port = addr >> 2; |
866 |
uint32_t *portsc = &s->portsc[port]; |
867 |
uint32_t old = *portsc; |
868 |
USBDevice *dev = s->ports[port].dev; |
869 |
|
870 |
trace_usb_ehci_portsc_write(addr + PORTSC_BEGIN, addr >> 2, val);
|
871 |
|
872 |
/* Clear rwc bits */
|
873 |
*portsc &= ~(val & PORTSC_RWC_MASK); |
874 |
/* The guest may clear, but not set the PED bit */
|
875 |
*portsc &= val | ~PORTSC_PED; |
876 |
/* POWNER is masked out by RO_MASK as it is RO when we've no companion */
|
877 |
handle_port_owner_write(s, port, val); |
878 |
/* And finally apply RO_MASK */
|
879 |
val &= PORTSC_RO_MASK; |
880 |
|
881 |
if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
|
882 |
trace_usb_ehci_port_reset(port, 1);
|
883 |
} |
884 |
|
885 |
if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
|
886 |
trace_usb_ehci_port_reset(port, 0);
|
887 |
if (dev && dev->attached) {
|
888 |
usb_port_reset(&s->ports[port]); |
889 |
*portsc &= ~PORTSC_CSC; |
890 |
} |
891 |
|
892 |
/*
|
893 |
* Table 2.16 Set the enable bit(and enable bit change) to indicate
|
894 |
* to SW that this port has a high speed device attached
|
895 |
*/
|
896 |
if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
|
897 |
val |= PORTSC_PED; |
898 |
} |
899 |
} |
900 |
|
901 |
*portsc &= ~PORTSC_RO_MASK; |
902 |
*portsc |= val; |
903 |
trace_usb_ehci_portsc_change(addr + PORTSC_BEGIN, addr >> 2, *portsc, old);
|
904 |
} |
905 |
|
906 |
static void ehci_opreg_write(void *ptr, hwaddr addr, |
907 |
uint64_t val, unsigned size)
|
908 |
{ |
909 |
EHCIState *s = ptr; |
910 |
uint32_t *mmio = s->opreg + (addr >> 2);
|
911 |
uint32_t old = *mmio; |
912 |
int i;
|
913 |
|
914 |
trace_usb_ehci_opreg_write(addr + s->opregbase, addr2str(addr), val); |
915 |
|
916 |
switch (addr) {
|
917 |
case USBCMD:
|
918 |
if (val & USBCMD_HCRESET) {
|
919 |
ehci_reset(s); |
920 |
val = s->usbcmd; |
921 |
break;
|
922 |
} |
923 |
|
924 |
/* not supporting dynamic frame list size at the moment */
|
925 |
if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
|
926 |
fprintf(stderr, "attempt to set frame list size -- value %d\n",
|
927 |
(int)val & USBCMD_FLS);
|
928 |
val &= ~USBCMD_FLS; |
929 |
} |
930 |
|
931 |
if (val & USBCMD_IAAD) {
|
932 |
/*
|
933 |
* Process IAAD immediately, otherwise the Linux IAAD watchdog may
|
934 |
* trigger and re-use a qh without us seeing the unlink.
|
935 |
*/
|
936 |
s->async_stepdown = 0;
|
937 |
qemu_bh_schedule(s->async_bh); |
938 |
trace_usb_ehci_doorbell_ring(); |
939 |
} |
940 |
|
941 |
if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=
|
942 |
((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) { |
943 |
if (s->pstate == EST_INACTIVE) {
|
944 |
SET_LAST_RUN_CLOCK(s); |
945 |
} |
946 |
s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */
|
947 |
ehci_update_halt(s); |
948 |
s->async_stepdown = 0;
|
949 |
qemu_bh_schedule(s->async_bh); |
950 |
} |
951 |
break;
|
952 |
|
953 |
case USBSTS:
|
954 |
val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
|
955 |
ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
|
956 |
val = s->usbsts; |
957 |
ehci_update_irq(s); |
958 |
break;
|
959 |
|
960 |
case USBINTR:
|
961 |
val &= USBINTR_MASK; |
962 |
break;
|
963 |
|
964 |
case FRINDEX:
|
965 |
val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */ |
966 |
break;
|
967 |
|
968 |
case CONFIGFLAG:
|
969 |
val &= 0x1;
|
970 |
if (val) {
|
971 |
for(i = 0; i < NB_PORTS; i++) |
972 |
handle_port_owner_write(s, i, 0);
|
973 |
} |
974 |
break;
|
975 |
|
976 |
case PERIODICLISTBASE:
|
977 |
if (ehci_periodic_enabled(s)) {
|
978 |
fprintf(stderr, |
979 |
"ehci: PERIODIC list base register set while periodic schedule\n"
|
980 |
" is enabled and HC is enabled\n");
|
981 |
} |
982 |
break;
|
983 |
|
984 |
case ASYNCLISTADDR:
|
985 |
if (ehci_async_enabled(s)) {
|
986 |
fprintf(stderr, |
987 |
"ehci: ASYNC list address register set while async schedule\n"
|
988 |
" is enabled and HC is enabled\n");
|
989 |
} |
990 |
break;
|
991 |
} |
992 |
|
993 |
*mmio = val; |
994 |
trace_usb_ehci_opreg_change(addr + s->opregbase, addr2str(addr), |
995 |
*mmio, old); |
996 |
} |
997 |
|
998 |
|
999 |
// TODO : Put in common header file, duplication from usb-ohci.c
|
1000 |
|
1001 |
/* Get an array of dwords from main memory */
|
1002 |
static inline int get_dwords(EHCIState *ehci, uint32_t addr, |
1003 |
uint32_t *buf, int num)
|
1004 |
{ |
1005 |
int i;
|
1006 |
|
1007 |
for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
1008 |
dma_memory_read(ehci->dma, addr, buf, sizeof(*buf));
|
1009 |
*buf = le32_to_cpu(*buf); |
1010 |
} |
1011 |
|
1012 |
return 1; |
1013 |
} |
1014 |
|
1015 |
/* Put an array of dwords in to main memory */
|
1016 |
static inline int put_dwords(EHCIState *ehci, uint32_t addr, |
1017 |
uint32_t *buf, int num)
|
1018 |
{ |
1019 |
int i;
|
1020 |
|
1021 |
for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
1022 |
uint32_t tmp = cpu_to_le32(*buf); |
1023 |
dma_memory_write(ehci->dma, addr, &tmp, sizeof(tmp));
|
1024 |
} |
1025 |
|
1026 |
return 1; |
1027 |
} |
1028 |
|
1029 |
/*
|
1030 |
* Write the qh back to guest physical memory. This step isn't
|
1031 |
* in the EHCI spec but we need to do it since we don't share
|
1032 |
* physical memory with our guest VM.
|
1033 |
*
|
1034 |
* The first three dwords are read-only for the EHCI, so skip them
|
1035 |
* when writing back the qh.
|
1036 |
*/
|
1037 |
static void ehci_flush_qh(EHCIQueue *q) |
1038 |
{ |
1039 |
uint32_t *qh = (uint32_t *) &q->qh; |
1040 |
uint32_t dwords = sizeof(EHCIqh) >> 2; |
1041 |
uint32_t addr = NLPTR_GET(q->qhaddr); |
1042 |
|
1043 |
put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); |
1044 |
} |
1045 |
|
1046 |
// 4.10.2
|
1047 |
|
1048 |
static int ehci_qh_do_overlay(EHCIQueue *q) |
1049 |
{ |
1050 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
1051 |
int i;
|
1052 |
int dtoggle;
|
1053 |
int ping;
|
1054 |
int eps;
|
1055 |
int reload;
|
1056 |
|
1057 |
assert(p != NULL);
|
1058 |
assert(p->qtdaddr == q->qtdaddr); |
1059 |
|
1060 |
// remember values in fields to preserve in qh after overlay
|
1061 |
|
1062 |
dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; |
1063 |
ping = q->qh.token & QTD_TOKEN_PING; |
1064 |
|
1065 |
q->qh.current_qtd = p->qtdaddr; |
1066 |
q->qh.next_qtd = p->qtd.next; |
1067 |
q->qh.altnext_qtd = p->qtd.altnext; |
1068 |
q->qh.token = p->qtd.token; |
1069 |
|
1070 |
|
1071 |
eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); |
1072 |
if (eps == EHCI_QH_EPS_HIGH) {
|
1073 |
q->qh.token &= ~QTD_TOKEN_PING; |
1074 |
q->qh.token |= ping; |
1075 |
} |
1076 |
|
1077 |
reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1078 |
set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); |
1079 |
|
1080 |
for (i = 0; i < 5; i++) { |
1081 |
q->qh.bufptr[i] = p->qtd.bufptr[i]; |
1082 |
} |
1083 |
|
1084 |
if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
|
1085 |
// preserve QH DT bit
|
1086 |
q->qh.token &= ~QTD_TOKEN_DTOGGLE; |
1087 |
q->qh.token |= dtoggle; |
1088 |
} |
1089 |
|
1090 |
q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
|
1091 |
q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
|
1092 |
|
1093 |
ehci_flush_qh(q); |
1094 |
|
1095 |
return 0; |
1096 |
} |
1097 |
|
1098 |
static int ehci_init_transfer(EHCIPacket *p) |
1099 |
{ |
1100 |
uint32_t cpage, offset, bytes, plen; |
1101 |
dma_addr_t page; |
1102 |
|
1103 |
cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE); |
1104 |
bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES); |
1105 |
offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
|
1106 |
qemu_sglist_init(&p->sgl, 5, p->queue->ehci->dma);
|
1107 |
|
1108 |
while (bytes > 0) { |
1109 |
if (cpage > 4) { |
1110 |
fprintf(stderr, "cpage out of range (%d)\n", cpage);
|
1111 |
return -1; |
1112 |
} |
1113 |
|
1114 |
page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK; |
1115 |
page += offset; |
1116 |
plen = bytes; |
1117 |
if (plen > 4096 - offset) { |
1118 |
plen = 4096 - offset;
|
1119 |
offset = 0;
|
1120 |
cpage++; |
1121 |
} |
1122 |
|
1123 |
qemu_sglist_add(&p->sgl, page, plen); |
1124 |
bytes -= plen; |
1125 |
} |
1126 |
return 0; |
1127 |
} |
1128 |
|
1129 |
static void ehci_finish_transfer(EHCIQueue *q, int status) |
1130 |
{ |
1131 |
uint32_t cpage, offset; |
1132 |
|
1133 |
if (status > 0) { |
1134 |
/* update cpage & offset */
|
1135 |
cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); |
1136 |
offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
|
1137 |
|
1138 |
offset += status; |
1139 |
cpage += offset >> QTD_BUFPTR_SH; |
1140 |
offset &= ~QTD_BUFPTR_MASK; |
1141 |
|
1142 |
set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); |
1143 |
q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
|
1144 |
q->qh.bufptr[0] |= offset;
|
1145 |
} |
1146 |
} |
1147 |
|
1148 |
static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) |
1149 |
{ |
1150 |
EHCIPacket *p; |
1151 |
EHCIState *s = port->opaque; |
1152 |
uint32_t portsc = s->portsc[port->index]; |
1153 |
|
1154 |
if (portsc & PORTSC_POWNER) {
|
1155 |
USBPort *companion = s->companion_ports[port->index]; |
1156 |
companion->ops->complete(companion, packet); |
1157 |
return;
|
1158 |
} |
1159 |
|
1160 |
p = container_of(packet, EHCIPacket, packet); |
1161 |
assert(p->async == EHCI_ASYNC_INFLIGHT); |
1162 |
|
1163 |
if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
|
1164 |
trace_usb_ehci_packet_action(p->queue, p, "remove");
|
1165 |
ehci_free_packet(p); |
1166 |
return;
|
1167 |
} |
1168 |
|
1169 |
trace_usb_ehci_packet_action(p->queue, p, "wakeup");
|
1170 |
p->async = EHCI_ASYNC_FINISHED; |
1171 |
p->usb_status = packet->status ? packet->status : packet->actual_length; |
1172 |
|
1173 |
if (p->queue->async) {
|
1174 |
qemu_bh_schedule(p->queue->ehci->async_bh); |
1175 |
} |
1176 |
} |
1177 |
|
1178 |
static void ehci_execute_complete(EHCIQueue *q) |
1179 |
{ |
1180 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
1181 |
|
1182 |
assert(p != NULL);
|
1183 |
assert(p->qtdaddr == q->qtdaddr); |
1184 |
assert(p->async == EHCI_ASYNC_INITIALIZED || |
1185 |
p->async == EHCI_ASYNC_FINISHED); |
1186 |
|
1187 |
DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
|
1188 |
q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status); |
1189 |
|
1190 |
if (p->usb_status < 0) { |
1191 |
switch (p->usb_status) {
|
1192 |
case USB_RET_IOERROR:
|
1193 |
case USB_RET_NODEV:
|
1194 |
q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); |
1195 |
set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
|
1196 |
ehci_raise_irq(q->ehci, USBSTS_ERRINT); |
1197 |
break;
|
1198 |
case USB_RET_STALL:
|
1199 |
q->qh.token |= QTD_TOKEN_HALT; |
1200 |
ehci_raise_irq(q->ehci, USBSTS_ERRINT); |
1201 |
break;
|
1202 |
case USB_RET_NAK:
|
1203 |
set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
|
1204 |
return; /* We're not done yet with this transaction */ |
1205 |
case USB_RET_BABBLE:
|
1206 |
q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); |
1207 |
ehci_raise_irq(q->ehci, USBSTS_ERRINT); |
1208 |
break;
|
1209 |
default:
|
1210 |
/* should not be triggerable */
|
1211 |
fprintf(stderr, "USB invalid response %d\n", p->usb_status);
|
1212 |
assert(0);
|
1213 |
break;
|
1214 |
} |
1215 |
} else {
|
1216 |
// TODO check 4.12 for splits
|
1217 |
uint32_t tbytes = get_field(q->qh.token, QTD_TOKEN_TBYTES); |
1218 |
|
1219 |
if (tbytes && p->pid == USB_TOKEN_IN) {
|
1220 |
tbytes -= p->usb_status; |
1221 |
if (tbytes) {
|
1222 |
/* 4.15.1.2 must raise int on a short input packet */
|
1223 |
ehci_raise_irq(q->ehci, USBSTS_INT); |
1224 |
} |
1225 |
} else {
|
1226 |
tbytes = 0;
|
1227 |
} |
1228 |
|
1229 |
DPRINTF("updating tbytes to %d\n", tbytes);
|
1230 |
set_field(&q->qh.token, tbytes, QTD_TOKEN_TBYTES); |
1231 |
} |
1232 |
ehci_finish_transfer(q, p->usb_status); |
1233 |
usb_packet_unmap(&p->packet, &p->sgl); |
1234 |
qemu_sglist_destroy(&p->sgl); |
1235 |
p->async = EHCI_ASYNC_NONE; |
1236 |
|
1237 |
q->qh.token ^= QTD_TOKEN_DTOGGLE; |
1238 |
q->qh.token &= ~QTD_TOKEN_ACTIVE; |
1239 |
|
1240 |
if (q->qh.token & QTD_TOKEN_IOC) {
|
1241 |
ehci_raise_irq(q->ehci, USBSTS_INT); |
1242 |
if (q->async) {
|
1243 |
q->ehci->int_req_by_async = true;
|
1244 |
} |
1245 |
} |
1246 |
} |
1247 |
|
1248 |
/* 4.10.3 returns "again" */
|
1249 |
static int ehci_execute(EHCIPacket *p, const char *action) |
1250 |
{ |
1251 |
USBEndpoint *ep; |
1252 |
int endp;
|
1253 |
bool spd;
|
1254 |
|
1255 |
assert(p->async == EHCI_ASYNC_NONE || |
1256 |
p->async == EHCI_ASYNC_INITIALIZED); |
1257 |
|
1258 |
if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) {
|
1259 |
fprintf(stderr, "Attempting to execute inactive qtd\n");
|
1260 |
return -1; |
1261 |
} |
1262 |
|
1263 |
if (get_field(p->qtd.token, QTD_TOKEN_TBYTES) > BUFF_SIZE) {
|
1264 |
ehci_trace_guest_bug(p->queue->ehci, |
1265 |
"guest requested more bytes than allowed");
|
1266 |
return -1; |
1267 |
} |
1268 |
|
1269 |
p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; |
1270 |
switch (p->pid) {
|
1271 |
case 0: |
1272 |
p->pid = USB_TOKEN_OUT; |
1273 |
break;
|
1274 |
case 1: |
1275 |
p->pid = USB_TOKEN_IN; |
1276 |
break;
|
1277 |
case 2: |
1278 |
p->pid = USB_TOKEN_SETUP; |
1279 |
break;
|
1280 |
default:
|
1281 |
fprintf(stderr, "bad token\n");
|
1282 |
break;
|
1283 |
} |
1284 |
|
1285 |
endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP); |
1286 |
ep = usb_ep_get(p->queue->dev, p->pid, endp); |
1287 |
|
1288 |
if (p->async == EHCI_ASYNC_NONE) {
|
1289 |
if (ehci_init_transfer(p) != 0) { |
1290 |
return -1; |
1291 |
} |
1292 |
|
1293 |
spd = (p->pid == USB_TOKEN_IN && NLPTR_TBIT(p->qtd.altnext) == 0);
|
1294 |
usb_packet_setup(&p->packet, p->pid, ep, p->qtdaddr, spd, |
1295 |
(p->qtd.token & QTD_TOKEN_IOC) != 0);
|
1296 |
usb_packet_map(&p->packet, &p->sgl); |
1297 |
p->async = EHCI_ASYNC_INITIALIZED; |
1298 |
} |
1299 |
|
1300 |
trace_usb_ehci_packet_action(p->queue, p, action); |
1301 |
usb_handle_packet(p->queue->dev, &p->packet); |
1302 |
DPRINTF("submit: qh 0x%x next 0x%x qtd 0x%x pid 0x%x len %zd endp 0x%x "
|
1303 |
"status %d actual_length %d\n", p->queue->qhaddr, p->qtd.next,
|
1304 |
p->qtdaddr, p->pid, p->packet.iov.size, endp, p->packet.status, |
1305 |
p->packet.actual_length); |
1306 |
|
1307 |
if (p->packet.actual_length > BUFF_SIZE) {
|
1308 |
fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
|
1309 |
return -1; |
1310 |
} |
1311 |
|
1312 |
return 1; |
1313 |
} |
1314 |
|
1315 |
/* 4.7.2
|
1316 |
*/
|
1317 |
|
1318 |
static int ehci_process_itd(EHCIState *ehci, |
1319 |
EHCIitd *itd, |
1320 |
uint32_t addr) |
1321 |
{ |
1322 |
USBDevice *dev; |
1323 |
USBEndpoint *ep; |
1324 |
int ret;
|
1325 |
uint32_t i, len, pid, dir, devaddr, endp; |
1326 |
uint32_t pg, off, ptr1, ptr2, max, mult; |
1327 |
|
1328 |
dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
|
1329 |
devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
|
1330 |
endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
|
1331 |
max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
|
1332 |
mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
|
1333 |
|
1334 |
for(i = 0; i < 8; i++) { |
1335 |
if (itd->transact[i] & ITD_XACT_ACTIVE) {
|
1336 |
pg = get_field(itd->transact[i], ITD_XACT_PGSEL); |
1337 |
off = itd->transact[i] & ITD_XACT_OFFSET_MASK; |
1338 |
ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); |
1339 |
ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
|
1340 |
len = get_field(itd->transact[i], ITD_XACT_LENGTH); |
1341 |
|
1342 |
if (len > max * mult) {
|
1343 |
len = max * mult; |
1344 |
} |
1345 |
|
1346 |
if (len > BUFF_SIZE) {
|
1347 |
return -1; |
1348 |
} |
1349 |
|
1350 |
qemu_sglist_init(&ehci->isgl, 2, ehci->dma);
|
1351 |
if (off + len > 4096) { |
1352 |
/* transfer crosses page border */
|
1353 |
uint32_t len2 = off + len - 4096;
|
1354 |
uint32_t len1 = len - len2; |
1355 |
qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); |
1356 |
qemu_sglist_add(&ehci->isgl, ptr2, len2); |
1357 |
} else {
|
1358 |
qemu_sglist_add(&ehci->isgl, ptr1 + off, len); |
1359 |
} |
1360 |
|
1361 |
pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; |
1362 |
|
1363 |
dev = ehci_find_device(ehci, devaddr); |
1364 |
ep = usb_ep_get(dev, pid, endp); |
1365 |
if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) {
|
1366 |
usb_packet_setup(&ehci->ipacket, pid, ep, addr, false,
|
1367 |
(itd->transact[i] & ITD_XACT_IOC) != 0);
|
1368 |
usb_packet_map(&ehci->ipacket, &ehci->isgl); |
1369 |
usb_handle_packet(dev, &ehci->ipacket); |
1370 |
usb_packet_unmap(&ehci->ipacket, &ehci->isgl); |
1371 |
ret = (ehci->ipacket.status == USB_RET_SUCCESS) ? |
1372 |
ehci->ipacket.actual_length : ehci->ipacket.status; |
1373 |
} else {
|
1374 |
DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
|
1375 |
ret = USB_RET_NAK; |
1376 |
} |
1377 |
qemu_sglist_destroy(&ehci->isgl); |
1378 |
|
1379 |
if (ret < 0) { |
1380 |
switch (ret) {
|
1381 |
default:
|
1382 |
fprintf(stderr, "Unexpected iso usb result: %d\n", ret);
|
1383 |
/* Fall through */
|
1384 |
case USB_RET_IOERROR:
|
1385 |
case USB_RET_NODEV:
|
1386 |
/* 3.3.2: XACTERR is only allowed on IN transactions */
|
1387 |
if (dir) {
|
1388 |
itd->transact[i] |= ITD_XACT_XACTERR; |
1389 |
ehci_raise_irq(ehci, USBSTS_ERRINT); |
1390 |
} |
1391 |
break;
|
1392 |
case USB_RET_BABBLE:
|
1393 |
itd->transact[i] |= ITD_XACT_BABBLE; |
1394 |
ehci_raise_irq(ehci, USBSTS_ERRINT); |
1395 |
break;
|
1396 |
case USB_RET_NAK:
|
1397 |
/* no data for us, so do a zero-length transfer */
|
1398 |
ret = 0;
|
1399 |
break;
|
1400 |
} |
1401 |
} |
1402 |
if (ret >= 0) { |
1403 |
if (!dir) {
|
1404 |
/* OUT */
|
1405 |
set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH); |
1406 |
} else {
|
1407 |
/* IN */
|
1408 |
set_field(&itd->transact[i], ret, ITD_XACT_LENGTH); |
1409 |
} |
1410 |
} |
1411 |
if (itd->transact[i] & ITD_XACT_IOC) {
|
1412 |
ehci_raise_irq(ehci, USBSTS_INT); |
1413 |
} |
1414 |
itd->transact[i] &= ~ITD_XACT_ACTIVE; |
1415 |
} |
1416 |
} |
1417 |
return 0; |
1418 |
} |
1419 |
|
1420 |
|
1421 |
/* This state is the entry point for asynchronous schedule
|
1422 |
* processing. Entry here consitutes a EHCI start event state (4.8.5)
|
1423 |
*/
|
1424 |
static int ehci_state_waitlisthead(EHCIState *ehci, int async) |
1425 |
{ |
1426 |
EHCIqh qh; |
1427 |
int i = 0; |
1428 |
int again = 0; |
1429 |
uint32_t entry = ehci->asynclistaddr; |
1430 |
|
1431 |
/* set reclamation flag at start event (4.8.6) */
|
1432 |
if (async) {
|
1433 |
ehci_set_usbsts(ehci, USBSTS_REC); |
1434 |
} |
1435 |
|
1436 |
ehci_queues_rip_unused(ehci, async); |
1437 |
|
1438 |
/* Find the head of the list (4.9.1.1) */
|
1439 |
for(i = 0; i < MAX_QH; i++) { |
1440 |
get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh, |
1441 |
sizeof(EHCIqh) >> 2); |
1442 |
ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
|
1443 |
|
1444 |
if (qh.epchar & QH_EPCHAR_H) {
|
1445 |
if (async) {
|
1446 |
entry |= (NLPTR_TYPE_QH << 1);
|
1447 |
} |
1448 |
|
1449 |
ehci_set_fetch_addr(ehci, async, entry); |
1450 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
1451 |
again = 1;
|
1452 |
goto out;
|
1453 |
} |
1454 |
|
1455 |
entry = qh.next; |
1456 |
if (entry == ehci->asynclistaddr) {
|
1457 |
break;
|
1458 |
} |
1459 |
} |
1460 |
|
1461 |
/* no head found for list. */
|
1462 |
|
1463 |
ehci_set_state(ehci, async, EST_ACTIVE); |
1464 |
|
1465 |
out:
|
1466 |
return again;
|
1467 |
} |
1468 |
|
1469 |
|
1470 |
/* This state is the entry point for periodic schedule processing as
|
1471 |
* well as being a continuation state for async processing.
|
1472 |
*/
|
1473 |
static int ehci_state_fetchentry(EHCIState *ehci, int async) |
1474 |
{ |
1475 |
int again = 0; |
1476 |
uint32_t entry = ehci_get_fetch_addr(ehci, async); |
1477 |
|
1478 |
if (NLPTR_TBIT(entry)) {
|
1479 |
ehci_set_state(ehci, async, EST_ACTIVE); |
1480 |
goto out;
|
1481 |
} |
1482 |
|
1483 |
/* section 4.8, only QH in async schedule */
|
1484 |
if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
|
1485 |
fprintf(stderr, "non queue head request in async schedule\n");
|
1486 |
return -1; |
1487 |
} |
1488 |
|
1489 |
switch (NLPTR_TYPE_GET(entry)) {
|
1490 |
case NLPTR_TYPE_QH:
|
1491 |
ehci_set_state(ehci, async, EST_FETCHQH); |
1492 |
again = 1;
|
1493 |
break;
|
1494 |
|
1495 |
case NLPTR_TYPE_ITD:
|
1496 |
ehci_set_state(ehci, async, EST_FETCHITD); |
1497 |
again = 1;
|
1498 |
break;
|
1499 |
|
1500 |
case NLPTR_TYPE_STITD:
|
1501 |
ehci_set_state(ehci, async, EST_FETCHSITD); |
1502 |
again = 1;
|
1503 |
break;
|
1504 |
|
1505 |
default:
|
1506 |
/* TODO: handle FSTN type */
|
1507 |
fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
|
1508 |
"which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
|
1509 |
return -1; |
1510 |
} |
1511 |
|
1512 |
out:
|
1513 |
return again;
|
1514 |
} |
1515 |
|
1516 |
static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) |
1517 |
{ |
1518 |
EHCIPacket *p; |
1519 |
uint32_t entry, devaddr, endp; |
1520 |
EHCIQueue *q; |
1521 |
EHCIqh qh; |
1522 |
|
1523 |
entry = ehci_get_fetch_addr(ehci, async); |
1524 |
q = ehci_find_queue_by_qh(ehci, entry, async); |
1525 |
if (NULL == q) { |
1526 |
q = ehci_alloc_queue(ehci, entry, async); |
1527 |
} |
1528 |
p = QTAILQ_FIRST(&q->packets); |
1529 |
|
1530 |
q->seen++; |
1531 |
if (q->seen > 1) { |
1532 |
/* we are going in circles -- stop processing */
|
1533 |
ehci_set_state(ehci, async, EST_ACTIVE); |
1534 |
q = NULL;
|
1535 |
goto out;
|
1536 |
} |
1537 |
|
1538 |
get_dwords(ehci, NLPTR_GET(q->qhaddr), |
1539 |
(uint32_t *) &qh, sizeof(EHCIqh) >> 2); |
1540 |
ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &qh); |
1541 |
|
1542 |
/*
|
1543 |
* The overlay area of the qh should never be changed by the guest,
|
1544 |
* except when idle, in which case the reset is a nop.
|
1545 |
*/
|
1546 |
devaddr = get_field(qh.epchar, QH_EPCHAR_DEVADDR); |
1547 |
endp = get_field(qh.epchar, QH_EPCHAR_EP); |
1548 |
if ((devaddr != get_field(q->qh.epchar, QH_EPCHAR_DEVADDR)) ||
|
1549 |
(endp != get_field(q->qh.epchar, QH_EPCHAR_EP)) || |
1550 |
(memcmp(&qh.current_qtd, &q->qh.current_qtd, |
1551 |
9 * sizeof(uint32_t)) != 0) || |
1552 |
(q->dev != NULL && q->dev->addr != devaddr)) {
|
1553 |
if (ehci_reset_queue(q) > 0) { |
1554 |
ehci_trace_guest_bug(ehci, "guest updated active QH");
|
1555 |
} |
1556 |
p = NULL;
|
1557 |
} |
1558 |
q->qh = qh; |
1559 |
|
1560 |
q->transact_ctr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
1561 |
if (q->transact_ctr == 0) { /* Guest bug in some versions of windows */ |
1562 |
q->transact_ctr = 4;
|
1563 |
} |
1564 |
|
1565 |
if (q->dev == NULL) { |
1566 |
q->dev = ehci_find_device(q->ehci, devaddr); |
1567 |
} |
1568 |
|
1569 |
if (p && p->async == EHCI_ASYNC_FINISHED) {
|
1570 |
/* I/O finished -- continue processing queue */
|
1571 |
trace_usb_ehci_packet_action(p->queue, p, "complete");
|
1572 |
ehci_set_state(ehci, async, EST_EXECUTING); |
1573 |
goto out;
|
1574 |
} |
1575 |
|
1576 |
if (async && (q->qh.epchar & QH_EPCHAR_H)) {
|
1577 |
|
1578 |
/* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
|
1579 |
if (ehci->usbsts & USBSTS_REC) {
|
1580 |
ehci_clear_usbsts(ehci, USBSTS_REC); |
1581 |
} else {
|
1582 |
DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
|
1583 |
" - done processing\n", q->qhaddr);
|
1584 |
ehci_set_state(ehci, async, EST_ACTIVE); |
1585 |
q = NULL;
|
1586 |
goto out;
|
1587 |
} |
1588 |
} |
1589 |
|
1590 |
#if EHCI_DEBUG
|
1591 |
if (q->qhaddr != q->qh.next) {
|
1592 |
DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
|
1593 |
q->qhaddr, |
1594 |
q->qh.epchar & QH_EPCHAR_H, |
1595 |
q->qh.token & QTD_TOKEN_HALT, |
1596 |
q->qh.token & QTD_TOKEN_ACTIVE, |
1597 |
q->qh.next); |
1598 |
} |
1599 |
#endif
|
1600 |
|
1601 |
if (q->qh.token & QTD_TOKEN_HALT) {
|
1602 |
ehci_set_state(ehci, async, EST_HORIZONTALQH); |
1603 |
|
1604 |
} else if ((q->qh.token & QTD_TOKEN_ACTIVE) && |
1605 |
(NLPTR_TBIT(q->qh.current_qtd) == 0)) {
|
1606 |
q->qtdaddr = q->qh.current_qtd; |
1607 |
ehci_set_state(ehci, async, EST_FETCHQTD); |
1608 |
|
1609 |
} else {
|
1610 |
/* EHCI spec version 1.0 Section 4.10.2 */
|
1611 |
ehci_set_state(ehci, async, EST_ADVANCEQUEUE); |
1612 |
} |
1613 |
|
1614 |
out:
|
1615 |
return q;
|
1616 |
} |
1617 |
|
1618 |
static int ehci_state_fetchitd(EHCIState *ehci, int async) |
1619 |
{ |
1620 |
uint32_t entry; |
1621 |
EHCIitd itd; |
1622 |
|
1623 |
assert(!async); |
1624 |
entry = ehci_get_fetch_addr(ehci, async); |
1625 |
|
1626 |
get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
1627 |
sizeof(EHCIitd) >> 2); |
1628 |
ehci_trace_itd(ehci, entry, &itd); |
1629 |
|
1630 |
if (ehci_process_itd(ehci, &itd, entry) != 0) { |
1631 |
return -1; |
1632 |
} |
1633 |
|
1634 |
put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
1635 |
sizeof(EHCIitd) >> 2); |
1636 |
ehci_set_fetch_addr(ehci, async, itd.next); |
1637 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
1638 |
|
1639 |
return 1; |
1640 |
} |
1641 |
|
1642 |
static int ehci_state_fetchsitd(EHCIState *ehci, int async) |
1643 |
{ |
1644 |
uint32_t entry; |
1645 |
EHCIsitd sitd; |
1646 |
|
1647 |
assert(!async); |
1648 |
entry = ehci_get_fetch_addr(ehci, async); |
1649 |
|
1650 |
get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd, |
1651 |
sizeof(EHCIsitd) >> 2); |
1652 |
ehci_trace_sitd(ehci, entry, &sitd); |
1653 |
|
1654 |
if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
|
1655 |
/* siTD is not active, nothing to do */;
|
1656 |
} else {
|
1657 |
/* TODO: split transfers are not implemented */
|
1658 |
fprintf(stderr, "WARNING: Skipping active siTD\n");
|
1659 |
} |
1660 |
|
1661 |
ehci_set_fetch_addr(ehci, async, sitd.next); |
1662 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
1663 |
return 1; |
1664 |
} |
1665 |
|
1666 |
/* Section 4.10.2 - paragraph 3 */
|
1667 |
static int ehci_state_advqueue(EHCIQueue *q) |
1668 |
{ |
1669 |
#if 0
|
1670 |
/* TO-DO: 4.10.2 - paragraph 2
|
1671 |
* if I-bit is set to 1 and QH is not active
|
1672 |
* go to horizontal QH
|
1673 |
*/
|
1674 |
if (I-bit set) {
|
1675 |
ehci_set_state(ehci, async, EST_HORIZONTALQH);
|
1676 |
goto out;
|
1677 |
}
|
1678 |
#endif
|
1679 |
|
1680 |
/*
|
1681 |
* want data and alt-next qTD is valid
|
1682 |
*/
|
1683 |
if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && |
1684 |
(NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
|
1685 |
q->qtdaddr = q->qh.altnext_qtd; |
1686 |
ehci_set_state(q->ehci, q->async, EST_FETCHQTD); |
1687 |
|
1688 |
/*
|
1689 |
* next qTD is valid
|
1690 |
*/
|
1691 |
} else if (NLPTR_TBIT(q->qh.next_qtd) == 0) { |
1692 |
q->qtdaddr = q->qh.next_qtd; |
1693 |
ehci_set_state(q->ehci, q->async, EST_FETCHQTD); |
1694 |
|
1695 |
/*
|
1696 |
* no valid qTD, try next QH
|
1697 |
*/
|
1698 |
} else {
|
1699 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
1700 |
} |
1701 |
|
1702 |
return 1; |
1703 |
} |
1704 |
|
1705 |
/* Section 4.10.2 - paragraph 4 */
|
1706 |
static int ehci_state_fetchqtd(EHCIQueue *q) |
1707 |
{ |
1708 |
EHCIqtd qtd; |
1709 |
EHCIPacket *p; |
1710 |
int again = 1; |
1711 |
|
1712 |
get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd, |
1713 |
sizeof(EHCIqtd) >> 2); |
1714 |
ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd); |
1715 |
|
1716 |
p = QTAILQ_FIRST(&q->packets); |
1717 |
if (p != NULL) { |
1718 |
if (p->qtdaddr != q->qtdaddr ||
|
1719 |
(!NLPTR_TBIT(p->qtd.next) && (p->qtd.next != qtd.next)) || |
1720 |
(!NLPTR_TBIT(p->qtd.altnext) && (p->qtd.altnext != qtd.altnext)) || |
1721 |
p->qtd.bufptr[0] != qtd.bufptr[0]) { |
1722 |
ehci_cancel_queue(q); |
1723 |
ehci_trace_guest_bug(q->ehci, "guest updated active QH or qTD");
|
1724 |
p = NULL;
|
1725 |
} else {
|
1726 |
p->qtd = qtd; |
1727 |
ehci_qh_do_overlay(q); |
1728 |
} |
1729 |
} |
1730 |
|
1731 |
if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
|
1732 |
if (p != NULL) { |
1733 |
/* transfer canceled by guest (clear active) */
|
1734 |
ehci_cancel_queue(q); |
1735 |
p = NULL;
|
1736 |
} |
1737 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
1738 |
} else if (p != NULL) { |
1739 |
switch (p->async) {
|
1740 |
case EHCI_ASYNC_NONE:
|
1741 |
case EHCI_ASYNC_INITIALIZED:
|
1742 |
/* Not yet executed (MULT), or previously nacked (int) packet */
|
1743 |
ehci_set_state(q->ehci, q->async, EST_EXECUTE); |
1744 |
break;
|
1745 |
case EHCI_ASYNC_INFLIGHT:
|
1746 |
/* Check if the guest has added new tds to the queue */
|
1747 |
again = ehci_fill_queue(QTAILQ_LAST(&q->packets, pkts_head)); |
1748 |
/* Unfinished async handled packet, go horizontal */
|
1749 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
1750 |
break;
|
1751 |
case EHCI_ASYNC_FINISHED:
|
1752 |
/*
|
1753 |
* We get here when advqueue moves to a packet which is already
|
1754 |
* finished, which can happen with packets queued up by fill_queue
|
1755 |
*/
|
1756 |
ehci_set_state(q->ehci, q->async, EST_EXECUTING); |
1757 |
break;
|
1758 |
} |
1759 |
} else {
|
1760 |
p = ehci_alloc_packet(q); |
1761 |
p->qtdaddr = q->qtdaddr; |
1762 |
p->qtd = qtd; |
1763 |
ehci_set_state(q->ehci, q->async, EST_EXECUTE); |
1764 |
} |
1765 |
|
1766 |
return again;
|
1767 |
} |
1768 |
|
1769 |
static int ehci_state_horizqh(EHCIQueue *q) |
1770 |
{ |
1771 |
int again = 0; |
1772 |
|
1773 |
if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
|
1774 |
ehci_set_fetch_addr(q->ehci, q->async, q->qh.next); |
1775 |
ehci_set_state(q->ehci, q->async, EST_FETCHENTRY); |
1776 |
again = 1;
|
1777 |
} else {
|
1778 |
ehci_set_state(q->ehci, q->async, EST_ACTIVE); |
1779 |
} |
1780 |
|
1781 |
return again;
|
1782 |
} |
1783 |
|
1784 |
/* Returns "again" */
|
1785 |
static int ehci_fill_queue(EHCIPacket *p) |
1786 |
{ |
1787 |
USBEndpoint *ep = p->packet.ep; |
1788 |
EHCIQueue *q = p->queue; |
1789 |
EHCIqtd qtd = p->qtd; |
1790 |
uint32_t qtdaddr, start_addr = p->qtdaddr; |
1791 |
|
1792 |
for (;;) {
|
1793 |
if (NLPTR_TBIT(qtd.next) != 0) { |
1794 |
break;
|
1795 |
} |
1796 |
qtdaddr = qtd.next; |
1797 |
/*
|
1798 |
* Detect circular td lists, Windows creates these, counting on the
|
1799 |
* active bit going low after execution to make the queue stop.
|
1800 |
*/
|
1801 |
if (qtdaddr == start_addr) {
|
1802 |
break;
|
1803 |
} |
1804 |
get_dwords(q->ehci, NLPTR_GET(qtdaddr), |
1805 |
(uint32_t *) &qtd, sizeof(EHCIqtd) >> 2); |
1806 |
ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd); |
1807 |
if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
|
1808 |
break;
|
1809 |
} |
1810 |
p = ehci_alloc_packet(q); |
1811 |
p->qtdaddr = qtdaddr; |
1812 |
p->qtd = qtd; |
1813 |
if (ehci_execute(p, "queue") == -1) { |
1814 |
return -1; |
1815 |
} |
1816 |
assert(p->packet.status == USB_RET_ASYNC); |
1817 |
p->async = EHCI_ASYNC_INFLIGHT; |
1818 |
} |
1819 |
usb_device_flush_ep_queue(ep->dev, ep); |
1820 |
return 1; |
1821 |
} |
1822 |
|
1823 |
static int ehci_state_execute(EHCIQueue *q) |
1824 |
{ |
1825 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
1826 |
int again = 0; |
1827 |
|
1828 |
assert(p != NULL);
|
1829 |
assert(p->qtdaddr == q->qtdaddr); |
1830 |
|
1831 |
if (ehci_qh_do_overlay(q) != 0) { |
1832 |
return -1; |
1833 |
} |
1834 |
|
1835 |
// TODO verify enough time remains in the uframe as in 4.4.1.1
|
1836 |
// TODO write back ptr to async list when done or out of time
|
1837 |
|
1838 |
/* 4.10.3, bottom of page 82, go horizontal on transaction counter == 0 */
|
1839 |
if (!q->async && q->transact_ctr == 0) { |
1840 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
1841 |
again = 1;
|
1842 |
goto out;
|
1843 |
} |
1844 |
|
1845 |
if (q->async) {
|
1846 |
ehci_set_usbsts(q->ehci, USBSTS_REC); |
1847 |
} |
1848 |
|
1849 |
again = ehci_execute(p, "process");
|
1850 |
if (again == -1) { |
1851 |
goto out;
|
1852 |
} |
1853 |
if (p->packet.status == USB_RET_ASYNC) {
|
1854 |
ehci_flush_qh(q); |
1855 |
trace_usb_ehci_packet_action(p->queue, p, "async");
|
1856 |
p->async = EHCI_ASYNC_INFLIGHT; |
1857 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
1858 |
if (q->async) {
|
1859 |
again = ehci_fill_queue(p); |
1860 |
} else {
|
1861 |
again = 1;
|
1862 |
} |
1863 |
goto out;
|
1864 |
} |
1865 |
if (p->packet.status == USB_RET_SUCCESS) {
|
1866 |
p->usb_status = p->packet.actual_length; |
1867 |
} else {
|
1868 |
p->usb_status = p->packet.status; |
1869 |
} |
1870 |
|
1871 |
ehci_set_state(q->ehci, q->async, EST_EXECUTING); |
1872 |
again = 1;
|
1873 |
|
1874 |
out:
|
1875 |
return again;
|
1876 |
} |
1877 |
|
1878 |
static int ehci_state_executing(EHCIQueue *q) |
1879 |
{ |
1880 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
1881 |
|
1882 |
assert(p != NULL);
|
1883 |
assert(p->qtdaddr == q->qtdaddr); |
1884 |
|
1885 |
ehci_execute_complete(q); |
1886 |
|
1887 |
/* 4.10.3 */
|
1888 |
if (!q->async && q->transact_ctr > 0) { |
1889 |
q->transact_ctr--; |
1890 |
} |
1891 |
|
1892 |
/* 4.10.5 */
|
1893 |
if (p->usb_status == USB_RET_NAK) {
|
1894 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
1895 |
} else {
|
1896 |
ehci_set_state(q->ehci, q->async, EST_WRITEBACK); |
1897 |
} |
1898 |
|
1899 |
ehci_flush_qh(q); |
1900 |
return 1; |
1901 |
} |
1902 |
|
1903 |
|
1904 |
static int ehci_state_writeback(EHCIQueue *q) |
1905 |
{ |
1906 |
EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
1907 |
uint32_t *qtd, addr; |
1908 |
int again = 0; |
1909 |
|
1910 |
/* Write back the QTD from the QH area */
|
1911 |
assert(p != NULL);
|
1912 |
assert(p->qtdaddr == q->qtdaddr); |
1913 |
|
1914 |
ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd); |
1915 |
qtd = (uint32_t *) &q->qh.next_qtd; |
1916 |
addr = NLPTR_GET(p->qtdaddr); |
1917 |
put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2); |
1918 |
ehci_free_packet(p); |
1919 |
|
1920 |
/*
|
1921 |
* EHCI specs say go horizontal here.
|
1922 |
*
|
1923 |
* We can also advance the queue here for performance reasons. We
|
1924 |
* need to take care to only take that shortcut in case we've
|
1925 |
* processed the qtd just written back without errors, i.e. halt
|
1926 |
* bit is clear.
|
1927 |
*/
|
1928 |
if (q->qh.token & QTD_TOKEN_HALT) {
|
1929 |
ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
1930 |
again = 1;
|
1931 |
} else {
|
1932 |
ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE); |
1933 |
again = 1;
|
1934 |
} |
1935 |
return again;
|
1936 |
} |
1937 |
|
1938 |
/*
|
1939 |
* This is the state machine that is common to both async and periodic
|
1940 |
*/
|
1941 |
|
1942 |
static void ehci_advance_state(EHCIState *ehci, int async) |
1943 |
{ |
1944 |
EHCIQueue *q = NULL;
|
1945 |
int again;
|
1946 |
|
1947 |
do {
|
1948 |
switch(ehci_get_state(ehci, async)) {
|
1949 |
case EST_WAITLISTHEAD:
|
1950 |
again = ehci_state_waitlisthead(ehci, async); |
1951 |
break;
|
1952 |
|
1953 |
case EST_FETCHENTRY:
|
1954 |
again = ehci_state_fetchentry(ehci, async); |
1955 |
break;
|
1956 |
|
1957 |
case EST_FETCHQH:
|
1958 |
q = ehci_state_fetchqh(ehci, async); |
1959 |
if (q != NULL) { |
1960 |
assert(q->async == async); |
1961 |
again = 1;
|
1962 |
} else {
|
1963 |
again = 0;
|
1964 |
} |
1965 |
break;
|
1966 |
|
1967 |
case EST_FETCHITD:
|
1968 |
again = ehci_state_fetchitd(ehci, async); |
1969 |
break;
|
1970 |
|
1971 |
case EST_FETCHSITD:
|
1972 |
again = ehci_state_fetchsitd(ehci, async); |
1973 |
break;
|
1974 |
|
1975 |
case EST_ADVANCEQUEUE:
|
1976 |
again = ehci_state_advqueue(q); |
1977 |
break;
|
1978 |
|
1979 |
case EST_FETCHQTD:
|
1980 |
again = ehci_state_fetchqtd(q); |
1981 |
break;
|
1982 |
|
1983 |
case EST_HORIZONTALQH:
|
1984 |
again = ehci_state_horizqh(q); |
1985 |
break;
|
1986 |
|
1987 |
case EST_EXECUTE:
|
1988 |
again = ehci_state_execute(q); |
1989 |
if (async) {
|
1990 |
ehci->async_stepdown = 0;
|
1991 |
} |
1992 |
break;
|
1993 |
|
1994 |
case EST_EXECUTING:
|
1995 |
assert(q != NULL);
|
1996 |
if (async) {
|
1997 |
ehci->async_stepdown = 0;
|
1998 |
} |
1999 |
again = ehci_state_executing(q); |
2000 |
break;
|
2001 |
|
2002 |
case EST_WRITEBACK:
|
2003 |
assert(q != NULL);
|
2004 |
again = ehci_state_writeback(q); |
2005 |
break;
|
2006 |
|
2007 |
default:
|
2008 |
fprintf(stderr, "Bad state!\n");
|
2009 |
again = -1;
|
2010 |
assert(0);
|
2011 |
break;
|
2012 |
} |
2013 |
|
2014 |
if (again < 0) { |
2015 |
fprintf(stderr, "processing error - resetting ehci HC\n");
|
2016 |
ehci_reset(ehci); |
2017 |
again = 0;
|
2018 |
} |
2019 |
} |
2020 |
while (again);
|
2021 |
} |
2022 |
|
2023 |
static void ehci_advance_async_state(EHCIState *ehci) |
2024 |
{ |
2025 |
const int async = 1; |
2026 |
|
2027 |
switch(ehci_get_state(ehci, async)) {
|
2028 |
case EST_INACTIVE:
|
2029 |
if (!ehci_async_enabled(ehci)) {
|
2030 |
break;
|
2031 |
} |
2032 |
ehci_set_state(ehci, async, EST_ACTIVE); |
2033 |
// No break, fall through to ACTIVE
|
2034 |
|
2035 |
case EST_ACTIVE:
|
2036 |
if (!ehci_async_enabled(ehci)) {
|
2037 |
ehci_queues_rip_all(ehci, async); |
2038 |
ehci_set_state(ehci, async, EST_INACTIVE); |
2039 |
break;
|
2040 |
} |
2041 |
|
2042 |
/* make sure guest has acknowledged the doorbell interrupt */
|
2043 |
/* TO-DO: is this really needed? */
|
2044 |
if (ehci->usbsts & USBSTS_IAA) {
|
2045 |
DPRINTF("IAA status bit still set.\n");
|
2046 |
break;
|
2047 |
} |
2048 |
|
2049 |
/* check that address register has been set */
|
2050 |
if (ehci->asynclistaddr == 0) { |
2051 |
break;
|
2052 |
} |
2053 |
|
2054 |
ehci_set_state(ehci, async, EST_WAITLISTHEAD); |
2055 |
ehci_advance_state(ehci, async); |
2056 |
|
2057 |
/* If the doorbell is set, the guest wants to make a change to the
|
2058 |
* schedule. The host controller needs to release cached data.
|
2059 |
* (section 4.8.2)
|
2060 |
*/
|
2061 |
if (ehci->usbcmd & USBCMD_IAAD) {
|
2062 |
/* Remove all unseen qhs from the async qhs queue */
|
2063 |
ehci_queues_rip_unseen(ehci, async); |
2064 |
trace_usb_ehci_doorbell_ack(); |
2065 |
ehci->usbcmd &= ~USBCMD_IAAD; |
2066 |
ehci_raise_irq(ehci, USBSTS_IAA); |
2067 |
} |
2068 |
break;
|
2069 |
|
2070 |
default:
|
2071 |
/* this should only be due to a developer mistake */
|
2072 |
fprintf(stderr, "ehci: Bad asynchronous state %d. "
|
2073 |
"Resetting to active\n", ehci->astate);
|
2074 |
assert(0);
|
2075 |
} |
2076 |
} |
2077 |
|
2078 |
static void ehci_advance_periodic_state(EHCIState *ehci) |
2079 |
{ |
2080 |
uint32_t entry; |
2081 |
uint32_t list; |
2082 |
const int async = 0; |
2083 |
|
2084 |
// 4.6
|
2085 |
|
2086 |
switch(ehci_get_state(ehci, async)) {
|
2087 |
case EST_INACTIVE:
|
2088 |
if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) { |
2089 |
ehci_set_state(ehci, async, EST_ACTIVE); |
2090 |
// No break, fall through to ACTIVE
|
2091 |
} else
|
2092 |
break;
|
2093 |
|
2094 |
case EST_ACTIVE:
|
2095 |
if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) { |
2096 |
ehci_queues_rip_all(ehci, async); |
2097 |
ehci_set_state(ehci, async, EST_INACTIVE); |
2098 |
break;
|
2099 |
} |
2100 |
|
2101 |
list = ehci->periodiclistbase & 0xfffff000;
|
2102 |
/* check that register has been set */
|
2103 |
if (list == 0) { |
2104 |
break;
|
2105 |
} |
2106 |
list |= ((ehci->frindex & 0x1ff8) >> 1); |
2107 |
|
2108 |
dma_memory_read(ehci->dma, list, &entry, sizeof entry);
|
2109 |
entry = le32_to_cpu(entry); |
2110 |
|
2111 |
DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
|
2112 |
ehci->frindex / 8, list, entry);
|
2113 |
ehci_set_fetch_addr(ehci, async,entry); |
2114 |
ehci_set_state(ehci, async, EST_FETCHENTRY); |
2115 |
ehci_advance_state(ehci, async); |
2116 |
ehci_queues_rip_unused(ehci, async); |
2117 |
break;
|
2118 |
|
2119 |
default:
|
2120 |
/* this should only be due to a developer mistake */
|
2121 |
fprintf(stderr, "ehci: Bad periodic state %d. "
|
2122 |
"Resetting to active\n", ehci->pstate);
|
2123 |
assert(0);
|
2124 |
} |
2125 |
} |
2126 |
|
2127 |
static void ehci_update_frindex(EHCIState *ehci, int frames) |
2128 |
{ |
2129 |
int i;
|
2130 |
|
2131 |
if (!ehci_enabled(ehci)) {
|
2132 |
return;
|
2133 |
} |
2134 |
|
2135 |
for (i = 0; i < frames; i++) { |
2136 |
ehci->frindex += 8;
|
2137 |
|
2138 |
if (ehci->frindex == 0x00002000) { |
2139 |
ehci_raise_irq(ehci, USBSTS_FLR); |
2140 |
} |
2141 |
|
2142 |
if (ehci->frindex == 0x00004000) { |
2143 |
ehci_raise_irq(ehci, USBSTS_FLR); |
2144 |
ehci->frindex = 0;
|
2145 |
if (ehci->usbsts_frindex >= 0x00004000) { |
2146 |
ehci->usbsts_frindex -= 0x00004000;
|
2147 |
} else {
|
2148 |
ehci->usbsts_frindex = 0;
|
2149 |
} |
2150 |
} |
2151 |
} |
2152 |
} |
2153 |
|
2154 |
static void ehci_frame_timer(void *opaque) |
2155 |
{ |
2156 |
EHCIState *ehci = opaque; |
2157 |
int need_timer = 0; |
2158 |
int64_t expire_time, t_now; |
2159 |
uint64_t ns_elapsed; |
2160 |
int frames, skipped_frames;
|
2161 |
int i;
|
2162 |
|
2163 |
t_now = qemu_get_clock_ns(vm_clock); |
2164 |
ns_elapsed = t_now - ehci->last_run_ns; |
2165 |
frames = ns_elapsed / FRAME_TIMER_NS; |
2166 |
|
2167 |
if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) {
|
2168 |
need_timer++; |
2169 |
ehci->async_stepdown = 0;
|
2170 |
|
2171 |
if (frames > ehci->maxframes) {
|
2172 |
skipped_frames = frames - ehci->maxframes; |
2173 |
ehci_update_frindex(ehci, skipped_frames); |
2174 |
ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames; |
2175 |
frames -= skipped_frames; |
2176 |
DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
|
2177 |
} |
2178 |
|
2179 |
for (i = 0; i < frames; i++) { |
2180 |
/*
|
2181 |
* If we're running behind schedule, we should not catch up
|
2182 |
* too fast, as that will make some guests unhappy:
|
2183 |
* 1) We must process a minimum of MIN_FR_PER_TICK frames,
|
2184 |
* otherwise we will never catch up
|
2185 |
* 2) Process frames until the guest has requested an irq (IOC)
|
2186 |
*/
|
2187 |
if (i >= MIN_FR_PER_TICK) {
|
2188 |
ehci_commit_irq(ehci); |
2189 |
if ((ehci->usbsts & USBINTR_MASK) & ehci->usbintr) {
|
2190 |
break;
|
2191 |
} |
2192 |
} |
2193 |
ehci_update_frindex(ehci, 1);
|
2194 |
ehci_advance_periodic_state(ehci); |
2195 |
ehci->last_run_ns += FRAME_TIMER_NS; |
2196 |
} |
2197 |
} else {
|
2198 |
if (ehci->async_stepdown < ehci->maxframes / 2) { |
2199 |
ehci->async_stepdown++; |
2200 |
} |
2201 |
ehci_update_frindex(ehci, frames); |
2202 |
ehci->last_run_ns += FRAME_TIMER_NS * frames; |
2203 |
} |
2204 |
|
2205 |
/* Async is not inside loop since it executes everything it can once
|
2206 |
* called
|
2207 |
*/
|
2208 |
if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {
|
2209 |
need_timer++; |
2210 |
ehci_advance_async_state(ehci); |
2211 |
} |
2212 |
|
2213 |
ehci_commit_irq(ehci); |
2214 |
if (ehci->usbsts_pending) {
|
2215 |
need_timer++; |
2216 |
ehci->async_stepdown = 0;
|
2217 |
} |
2218 |
|
2219 |
if (need_timer) {
|
2220 |
/* If we've raised int, we speed up the timer, so that we quickly
|
2221 |
* notice any new packets queued up in response */
|
2222 |
if (ehci->int_req_by_async && (ehci->usbsts & USBSTS_INT)) {
|
2223 |
expire_time = t_now + get_ticks_per_sec() / (FRAME_TIMER_FREQ * 2);
|
2224 |
ehci->int_req_by_async = false;
|
2225 |
} else {
|
2226 |
expire_time = t_now + (get_ticks_per_sec() |
2227 |
* (ehci->async_stepdown+1) / FRAME_TIMER_FREQ);
|
2228 |
} |
2229 |
qemu_mod_timer(ehci->frame_timer, expire_time); |
2230 |
} |
2231 |
} |
2232 |
|
2233 |
static const MemoryRegionOps ehci_mmio_caps_ops = { |
2234 |
.read = ehci_caps_read, |
2235 |
.valid.min_access_size = 1,
|
2236 |
.valid.max_access_size = 4,
|
2237 |
.impl.min_access_size = 1,
|
2238 |
.impl.max_access_size = 1,
|
2239 |
.endianness = DEVICE_LITTLE_ENDIAN, |
2240 |
}; |
2241 |
|
2242 |
static const MemoryRegionOps ehci_mmio_opreg_ops = { |
2243 |
.read = ehci_opreg_read, |
2244 |
.write = ehci_opreg_write, |
2245 |
.valid.min_access_size = 4,
|
2246 |
.valid.max_access_size = 4,
|
2247 |
.endianness = DEVICE_LITTLE_ENDIAN, |
2248 |
}; |
2249 |
|
2250 |
static const MemoryRegionOps ehci_mmio_port_ops = { |
2251 |
.read = ehci_port_read, |
2252 |
.write = ehci_port_write, |
2253 |
.valid.min_access_size = 4,
|
2254 |
.valid.max_access_size = 4,
|
2255 |
.endianness = DEVICE_LITTLE_ENDIAN, |
2256 |
}; |
2257 |
|
2258 |
static USBPortOps ehci_port_ops = {
|
2259 |
.attach = ehci_attach, |
2260 |
.detach = ehci_detach, |
2261 |
.child_detach = ehci_child_detach, |
2262 |
.wakeup = ehci_wakeup, |
2263 |
.complete = ehci_async_complete_packet, |
2264 |
}; |
2265 |
|
2266 |
static USBBusOps ehci_bus_ops = {
|
2267 |
.register_companion = ehci_register_companion, |
2268 |
}; |
2269 |
|
2270 |
static int usb_ehci_post_load(void *opaque, int version_id) |
2271 |
{ |
2272 |
EHCIState *s = opaque; |
2273 |
int i;
|
2274 |
|
2275 |
for (i = 0; i < NB_PORTS; i++) { |
2276 |
USBPort *companion = s->companion_ports[i]; |
2277 |
if (companion == NULL) { |
2278 |
continue;
|
2279 |
} |
2280 |
if (s->portsc[i] & PORTSC_POWNER) {
|
2281 |
companion->dev = s->ports[i].dev; |
2282 |
} else {
|
2283 |
companion->dev = NULL;
|
2284 |
} |
2285 |
} |
2286 |
|
2287 |
return 0; |
2288 |
} |
2289 |
|
2290 |
static void usb_ehci_vm_state_change(void *opaque, int running, RunState state) |
2291 |
{ |
2292 |
EHCIState *ehci = opaque; |
2293 |
|
2294 |
/*
|
2295 |
* We don't migrate the EHCIQueue-s, instead we rebuild them for the
|
2296 |
* schedule in guest memory. We must do the rebuilt ASAP, so that
|
2297 |
* USB-devices which have async handled packages have a packet in the
|
2298 |
* ep queue to match the completion with.
|
2299 |
*/
|
2300 |
if (state == RUN_STATE_RUNNING) {
|
2301 |
ehci_advance_async_state(ehci); |
2302 |
} |
2303 |
|
2304 |
/*
|
2305 |
* The schedule rebuilt from guest memory could cause the migration dest
|
2306 |
* to miss a QH unlink, and fail to cancel packets, since the unlinked QH
|
2307 |
* will never have existed on the destination. Therefor we must flush the
|
2308 |
* async schedule on savevm to catch any not yet noticed unlinks.
|
2309 |
*/
|
2310 |
if (state == RUN_STATE_SAVE_VM) {
|
2311 |
ehci_advance_async_state(ehci); |
2312 |
ehci_queues_rip_unseen(ehci, 1);
|
2313 |
} |
2314 |
} |
2315 |
|
2316 |
const VMStateDescription vmstate_ehci = {
|
2317 |
.name = "ehci-core",
|
2318 |
.version_id = 2,
|
2319 |
.minimum_version_id = 1,
|
2320 |
.post_load = usb_ehci_post_load, |
2321 |
.fields = (VMStateField[]) { |
2322 |
/* mmio registers */
|
2323 |
VMSTATE_UINT32(usbcmd, EHCIState), |
2324 |
VMSTATE_UINT32(usbsts, EHCIState), |
2325 |
VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2),
|
2326 |
VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2),
|
2327 |
VMSTATE_UINT32(usbintr, EHCIState), |
2328 |
VMSTATE_UINT32(frindex, EHCIState), |
2329 |
VMSTATE_UINT32(ctrldssegment, EHCIState), |
2330 |
VMSTATE_UINT32(periodiclistbase, EHCIState), |
2331 |
VMSTATE_UINT32(asynclistaddr, EHCIState), |
2332 |
VMSTATE_UINT32(configflag, EHCIState), |
2333 |
VMSTATE_UINT32(portsc[0], EHCIState),
|
2334 |
VMSTATE_UINT32(portsc[1], EHCIState),
|
2335 |
VMSTATE_UINT32(portsc[2], EHCIState),
|
2336 |
VMSTATE_UINT32(portsc[3], EHCIState),
|
2337 |
VMSTATE_UINT32(portsc[4], EHCIState),
|
2338 |
VMSTATE_UINT32(portsc[5], EHCIState),
|
2339 |
/* frame timer */
|
2340 |
VMSTATE_TIMER(frame_timer, EHCIState), |
2341 |
VMSTATE_UINT64(last_run_ns, EHCIState), |
2342 |
VMSTATE_UINT32(async_stepdown, EHCIState), |
2343 |
/* schedule state */
|
2344 |
VMSTATE_UINT32(astate, EHCIState), |
2345 |
VMSTATE_UINT32(pstate, EHCIState), |
2346 |
VMSTATE_UINT32(a_fetch_addr, EHCIState), |
2347 |
VMSTATE_UINT32(p_fetch_addr, EHCIState), |
2348 |
VMSTATE_END_OF_LIST() |
2349 |
} |
2350 |
}; |
2351 |
|
2352 |
void usb_ehci_initfn(EHCIState *s, DeviceState *dev)
|
2353 |
{ |
2354 |
int i;
|
2355 |
|
2356 |
/* 2.2 host controller interface version */
|
2357 |
s->caps[0x00] = (uint8_t)(s->opregbase - s->capsbase);
|
2358 |
s->caps[0x01] = 0x00; |
2359 |
s->caps[0x02] = 0x00; |
2360 |
s->caps[0x03] = 0x01; /* HC version */ |
2361 |
s->caps[0x04] = NB_PORTS; /* Number of downstream ports */ |
2362 |
s->caps[0x05] = 0x00; /* No companion ports at present */ |
2363 |
s->caps[0x06] = 0x00; |
2364 |
s->caps[0x07] = 0x00; |
2365 |
s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */ |
2366 |
s->caps[0x0a] = 0x00; |
2367 |
s->caps[0x0b] = 0x00; |
2368 |
|
2369 |
usb_bus_new(&s->bus, &ehci_bus_ops, dev); |
2370 |
for(i = 0; i < NB_PORTS; i++) { |
2371 |
usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, |
2372 |
USB_SPEED_MASK_HIGH); |
2373 |
s->ports[i].dev = 0;
|
2374 |
} |
2375 |
|
2376 |
s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); |
2377 |
s->async_bh = qemu_bh_new(ehci_frame_timer, s); |
2378 |
QTAILQ_INIT(&s->aqueues); |
2379 |
QTAILQ_INIT(&s->pqueues); |
2380 |
usb_packet_init(&s->ipacket); |
2381 |
|
2382 |
qemu_register_reset(ehci_reset, s); |
2383 |
qemu_add_vm_change_state_handler(usb_ehci_vm_state_change, s); |
2384 |
|
2385 |
memory_region_init(&s->mem, "ehci", MMIO_SIZE);
|
2386 |
memory_region_init_io(&s->mem_caps, &ehci_mmio_caps_ops, s, |
2387 |
"capabilities", CAPA_SIZE);
|
2388 |
memory_region_init_io(&s->mem_opreg, &ehci_mmio_opreg_ops, s, |
2389 |
"operational", PORTSC_BEGIN);
|
2390 |
memory_region_init_io(&s->mem_ports, &ehci_mmio_port_ops, s, |
2391 |
"ports", PORTSC_END - PORTSC_BEGIN);
|
2392 |
|
2393 |
memory_region_add_subregion(&s->mem, s->capsbase, &s->mem_caps); |
2394 |
memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg); |
2395 |
memory_region_add_subregion(&s->mem, s->opregbase + PORTSC_BEGIN, |
2396 |
&s->mem_ports); |
2397 |
} |
2398 |
|
2399 |
/*
|
2400 |
* vim: expandtab ts=4
|
2401 |
*/
|