tcg/optimize: simplify shift/rot r, 0, a => movi r, 0 cases
shift/rot r, 0, a is equivalent to movi r, 0.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/optimize: simplify and r, a, 0 cases
and r, a, 0 is equivalent to a movi r, 0.
tcg/optimize: simplify or/xor r, a, 0 cases
or/xor r, a, 0 is equivalent to a mov r, a.
tcg/optimize: split expression simplification
Split expression simplification in multiple parts so that a given opcan appear multiple times. This patch should not change anything.
tcg: improve profiler
Now that there are two passes of optimization (optimize.c, liveness)there is no point of outputing the statistics of the liveness partonly. Update the code to take into account both optimizations.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
tcg/s390: fix ld/st with CONFIG_TCG_PASS_AREG0
The load/store slow path has been broken in e141ab52d:- We need to move 4 registers for store functions and 3 registers for load functions and not the reverse.- According to the s390x calling convention the arguments of a function...
tcg/mips: fix broken CONFIG_TCG_PASS_AREG0 code
The CONFIG_TCG_PASS_AREG0 code for calling ld/st helpers wasbroken in that it did not respect the ABI requirement that 64bit values were passed in even-odd register pairs. The simplestway to fix this is to implement some new utility functions...
tcg/ia64: fix and optimize ld/st slow path
Store slow path has been broken in e141ab52d:- the arguments are shifted before the last one (mem_index) is written.- the shift is done for both slow and fast paths.
Fix that. Also optimize a bit by bundling the move together. This still...
tcg/ia64: fix prologue/epilogue
Prologue and epilogue code has been broken in cea5f9a28.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: Fix broken CONFIG_TCG_PASS_AREG0 code
tci: don't write zero for reloc in tci_out_label
If tci_out_label is called in the context of tcg_gen_code_search_pc, wecould be overwriting an already patched relocation with zero -- and notrepatch it because the set_label is past search_pc, causing a QEMU crash...
TCG: Fix compile breakage in tcg_dump_ops
Commit eeacee4d865 changed the syntax of tcg_dump_ops, but didn't convertall users (notably missing the ppc ones) to it. Fix them to the new syntax.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: malc <av1474@comtv.ru>
qemu-log: cleanup
Don't use global variables directly but via accessor functions. Rename globals.
Convert macros to functions, add GCC format attributes.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg/ppc: Handle _CALL_DARWIN being undefined on Darwin
powerpc-apple-darwin9-gcc-4.2.1 (GCC) 4.2.1 (Apple Inc. build 5577)does not define _CALL_DARWIN, leading to unexpected behavior w.r.t.register clobbering and stack frame layout.
Since _CALL_DARWIN is a reserved identifier, define a custom...
tcg/ppc64: Don't hardcode register numbers for qemu_ld/st
Facilitates using r3 for prepended AREG0.
Signed-off-by: Andreas F?rber <afaerber@suse.de>Signed-off-by: malc <av1474@comtv.ru>
tcg/ppc64: Fix CONFIG_TCG_PASS_AREG0
In qemu_ld/st load the registers for the helper calls directly ratherthan rotating them around afterwards for AREG0.
Also clobber the additional register.
tcg/ppc: Don't hardcode register numbers
Also assure i64 alignment where necessary.
Alignment code optimization suggested by malc.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Alexander Graf <agraf@suse.de>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
tcg/ppc: Clobber r5 for 64-bit qemu_ld
This accounts for the additional addr_reg2 register.
tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 mode
Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3,based on patches by malc.
Also adjust the registers clobbered, based on patch by Alex.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Alexander Graf <agraf@suse.de>...
tcg/ppc: Do not overwrite lower address word on Darwin and AIX
For targets where TARGET_LONG_BITS != 32, i.e. 64-bit guests,addr_reg is moved to r4. For hosts without TCG_TARGET_CALL_ALIGN_ARGSeither data_reg2 or data_reg or a masked version thereof would overwrite...
Bail out if CONFIG_TCG_PASS_AREG0 is defined
Signed-off-by: malc <av1474@comtv.ru>
Restore consistent formatting
tcg/i386: Use GDB JIT debugging interface only for hosts with ELF
Not all i386 / x86_64 hosts use ELF.Ask the compiler whether ELF is used.
On w64, gdb crashes when ELF_HOST_MACHINE is defined.
Cc: Blue Swirl <blauwirbel@gmail.com>Acked-by: Richard Henderson <rth@twiddle.net>...
tcg/i386: Add support for w64 ABI
w64 uses the registers rcx, rdx, r8 and r9 for function arguments,so it needs a different declaration of tcg_target_call_iarg_regs.
rax, rcx, rdx, r8, r9, r10 and r11 may be changed by function calls.
rbx, rbp, rdi, rsi, r12, r13, r14 and r15 remain unchanged by function calls....
qemu tcg: Remove one entry of INDEX_op_ld_i64 from ppc_op_defs
There two entries of INDEX_op_ld_i64 in the ppc_op_defs. That causes anassertion failure in tcg_add_target_add_op_defs() when --enable-debug isused on a ppc64 backend (that's ppc64 host, not target)....
tcg-sparc: Add debug_frame support.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg-hppa: Add debug_frame support.
tcg: Allow ELF_HOST_FLAGS and ELF_OSABI overrides in gdb-jit.
tcg: Add debug_info to JIT ELF image.
This allows us to actually supply a function name in softmmu builds;gdb doesn't pick up the minimal symbol table otherwise. Also add abit of documentation and statically generate more of the ELF image.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
tcg: Use the GDB JIT debugging interface.
This allows us to generate unwind info for the dynamicly generatedcode in the code_gen_buffer. Only i386 is converted at this point.
tcg: fix sparc host for AREG0 free operation
e141ab52d2ea5d0bc6ad3b1ad32841127ca04adc didn't handlethe other memory access helper case, fix.
softmmu templates: optionally pass CPUState to memory access functions
Optionally, make memory access helpers take a parameter for CPUStateinstead of relying on global env.
On most targets, perform simple moves to reorder registers. On i386,switch from regparm(3) calling convention to standard stack-based...
i386: Remove REGPARM
Use stack based calling convention (GCC default) for interfacing withgenerated code instead of register based convention (regparm(3)).
w64: Fix data type of next_tb and tcg_qemu_tb_exec
next_tb is the numeric value of a tcg target (= QEMU host) address.
Using tcg_target_ulong instead of unsigned long shows this and makesthe code portable for hosts with an unusual size of long (w64).
The type cast '(long)(next_tb & ~3)' was not needed (casting...
Fix large memory chunks allocation with tcg_malloc.
An attempt to allocate a large memory chunk after a small one resulted incircular links in list of pools. It caused the same memory beingallocated twice for different arrays.
Now pools for large memory chunks are kept in separate list and are...
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
tcg: Improve tcg_out_label and fix its usage for w64
tcg_out_label is always called with a third argument of pointer typewhich was casted to tcg_target_long.
These casts can be avoided by changing the prototype of tcg_out_label.
There was also a cast to long. For most hosts with...
w64: fix type casts when calling flush_icache_range
Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
w64: Change data type of parameters for flush_icache_range
The TCG targets i386 and tci needed a change of the functionprototype for w64.
This change is currently not needed for the other TCG targets,but it can be applied to avoid code differences.
Cc: Blue Swirl <blauwirbel@gmail.com>...
w64: Fix data type of parameters for flush_icache_range
flush_icache_range takes two address parameters which must be largeenough to address any address of the host.
For hosts with sizeof(unsigned long) == sizeof(void *), this patchchanges nothing. All currently supported hosts fall into this category....
tcg: Rearrange definitions and include statements
This change makes tcg_target_ulong available in tcg-target.h.
tcg: Remove unneeded include statements
The standard include files are already included in qemu-common.h.
malloc.h and alloca.h were needed for alloca() which was removedfrom TCG code some years ago when switching from dyngen to TCG(see commit 49516bc0d622112caac9df628caf19010fda8b67)....
tcg-arm: fix a typo in comments
ARM still doesn't support 16GB buffers in 32-bit modes, replace the16GB by 16MB in the comment.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
tcg/arm: Use r6 as TCG_AREG0 to avoid clash with Thumb framepointer
On ARM, in Thumb mode r7 is used for the framepointer; this meantthat we would fail to compile in debug mode because we were using r7for TCG_AREG0. Shift to r6 instead to avoid this clash....
tcg/arm: remove fixed map code buffer restriction
On ARM, don't map the code buffer at a fixed location, and fix up thecall/goto tcg routines to let it do long jumps.
Mapping the code buffer at a fixed address could sometimes result in it beingmapped over the top of the heap with pretty random results....
tcg: make tcg_const_ptr actually accept a pointer argument
Make tcg_const_ptr() include a cast so that you can pass it apointer. This allows us to drop the casts we had in all the placesthat use this macro.
Acked-by: Andreas Färber <andreas.faerber@web.de>...
tcg: Remove redundant declarations of TCG_TARGET_REG_BITS
TCG_TARGET_REG_BITS is declared in tcg.h for all TCG targets.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
fix spelling in tcg sub directory
Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
tci: Make flush_icache_range() inline
This is standard for other tcg targets and improves tci, too.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
tcg-sparc: Fix set-but-not used warnings.
In both cases, val is computed, but then not used in thesubsequent line, which then re-computes the quantity ina different type (int32_t vs unsigned long).
Keep the computation type that's been working so far....
Merge branch 's390-1.0' of git://repo.or.cz/qemu/agraf
tcg: Use TCGReg for standard tcg-target entry points.
Including tcg_out_ld, tcg_out_st, tcg_out_mov, tcg_out_movi.
Signed-off-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Stefan Weil <sw@weilnetz.de>...
tcg: Standardize on TCGReg as the enum for hard registers
Most targets did not name the enum; tci used TCGRegister.
tcg-ppc64: Fix compile errors for userspace only builds with gcc 4.6
tcg/ppc64/tcg-target.c has a couple of places where variables are setunconditionally, but otherwise used only for softmmu builds, notuserspace only builds. This causes compiler warnings (which are fatal...
Merge branch 'tci' of git://qemu.weilnetz.de/qemu
tcg: Fix whitespace in tcg-op.h.
Removing the only tabs in the file.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: malc <av1474@comtv.ru>
tcg: Fix regression in tcg_gen_deposit_i64.
The error being caused by the failure to copy the other half ofthe input to the output after having narrowed the deposit operation.
tcg: TCG targets may define tcg_qemu_tb_exec
Targets may use a non standard definition of tcg_tb_execby defining this macro in their tcg_target.h.
This is used here by ppc. It will be used by the TCG interpreter, too.
Cc: malc <av1474@comtv.ru>Signed-off-by: Stefan Weil <sw@weilnetz.de>
tcg: Make ARRAY_SIZE(tcg_op_defs) globally available
tcg_op_defs was already a global array.
The tci disassembler also needs ARRAY_SIZE(tcg_op_defs),so add a new global constant with this value.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
tcg: Add bytecode generator for tcg interpreter
Unlike other tcg target code generators, this one does not generatemachine code for some cpu. It generates machine independent bytecodewhich is interpreted later.
This allows running QEMU on any host.
Interpreted bytecode is slower than direct execution of generated...
tcg: Optimize some forms of deposit.
If the deposit replaces the entire word, optimize to a move.
If we're inserting to the top of the word, avoid the mask of arg2as we'll be shifting out all of the garbage and shifting in zeros.
If the host is 32-bit, reduce a 64-bit deposit to a 32-bit deposit...
tcg: Fix spelling in comment (varables -> variables)
tcg/s390: Remove unused tcg_out_addi()
Remove the unused function tcg_out_addi() from the s390 TCG backend;this brings it into line with other backends.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Acked-by: Richard Henderson <rth@twiddle.net>...
tcg/ia64: Remove unused tcg_out_addi()
Remove the unused function tcg_out_addi() from the ia64 TCG backend;this brings it into line with other backends.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg-i386: Introduce limited deposit support
x86 cannot provide an optimized generic deposit implementation. But atleast for a few special cases, namely for writing bits 0..7, 8..15, and0..15, versions using only a single instruction are feasible.Introducing such limited support improves emulating 16-bit x86 code on...
tcg/arm: Remove unused tcg_out_addi()
Remove the unused function tcg_out_addi() from the ARM TCG backend;this fixes a compilation failure on ARM hosts with newer gcc.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>...
tcg: Add some assertions
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg: Add forward declarations for local functions
These functions are defined in the tcg target specific filetcg-target.c.
The forward declarations assert that every tcg target usesthe same function prototype.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.h
It is now declared for all tcg targets in tcg.h,so the tcg target specific declarations are redundant.
tcg: Declare TCG_TARGET_REG_BITS in tcg.h
TCG_TARGET_REG_BITS can be determined by the compiler,so there is no need to declare it for each individual tcg target.
This is especially important for new tcg targetswhich will be supported by the tcg interpreter....
tcg/ppc64: Only one call output register needed for 64 bit hosts
The second register is only needed for 32 bit hosts.
Cc: Vassili Karpov <av1474@comtv.ru>Fine-with-me'd-by: Vassili Karpov <av1474@comtv.ru>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
tcg/sparc: Only one call output register needed for 64 bit hosts
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg/s390: Only one call output register needed for 64 bit hosts
Cc: Alexander Graf <agraf@suse.de>Acked-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg/ia64: Only one call output register needed for 64 bit hosts
The second register is never used for ia64 hosts.
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg/i386: Only one call output register needed for 64 bit hosts
tcg/ppc64: Fix zero extension code generation bug for ppc64 host
The ppc64 code generation backend uses an rldicr (Rotate Left DoubleImmediate and Clear Right) instruction to implement zero extension ofa 32 bit quantity to a 64 bit quantity (INDEX_op_ext32u_i64). However...
tcg/ppc/tcg-target.c: Avoid 'set but not used' gcc warnings
Move the declaration and initialisation of some variables intcg_out_qemu_ld and tcg_out_qemu_st inside CONFIG_SOFTMMU, toavoid the "variable set but not used" warning of gcc 4.6.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
TCG: improve optimizer debugging
Use enum TCGOpcode instead of plain old int so that the name ofcurrent op can be seen in GDB. Add a default case to switchso that GCC does not complain about unhandled enum cases.
tcg: Update --enable-debug for TCG_OPF_NOT_PRESENT.
Signed-off-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
tcg/ppc64: fix 16/32 mixup
tcg/ppc64: implement not_i32/64 and ext32u_i64
tcg/ppc32: implement deposit_i32
tcg-ia64: Fix typos in AREG0 setup in prologue.
tcg: Constant fold neg, andc, orc, eqv, nand, nor.
tcg-hppa: Fix CPU_TEMP_BUF_NLONGS oversight.
tcg: Always define all of the TCGOpcode enum members.
By always defining these symbols, we can eliminate a lot of ifdefs.
To allow this to be checked reliably, the semantics of theTCG_TARGET_HAS_* macros must be changed from def/undef to true/false.This allows even more ifdefs to be removed, converting them into...
tcg: Add and use TCG_OPF_64BIT.
This allows the simplification of the op_bits function fromtcg/optimize.c.
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
TCG: fix copy propagation
Copy propagation introduced in 22613af4a6d9602001e6d0e7b6d98aa40aa018dcconsidered only global registers. However, register temps and stackallocated locals must be handled differently because register tempsdon't survive across brcond....
TCG: fix breakage by previous patch
Fix incorrect logic and typos in previous commit1bfd07bdfe56cea43dbe258dcb161e46b0ee29b7.
TCG: fix breakage on some RISC hosts
Fix breakage by a640f03178c22355a158fa9378e4f8bfa4f517a6and 55c0975c5b358e948b9ae7bd7b07eff92508e756.
Some TCG targets don't implement all TCG ops, so makeoptimizing those conditional.
Do constant folding for unary operations.
Perform constant folding for NOT and EXT{8,16,32}{S,U} operations.
Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Do constant folding for boolean operations.
Perform constant folding for AND, OR, XOR operations.
Do constant folding for shift operations.
Perform constant forlding for SHR, SHL, SAR, ROTR, ROTL operations.
Do constant folding for basic arithmetic operations.
Perform actual constant folding for ADD, SUB and MUL operations.
Add copy and constant propagation.
Make tcg_constant_folding do copy and constant propagation. It is apreparational work before actual constant folding.
Add TCG optimizations stub
Added file tcg/optimize.c to hold TCG optimizations. Function tcg_optimizeis called from tcg_gen_code_common. It calls other functions performingspecific optimizations. Stub for constant folding was added.
Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>...
tcg/mips: Fix regression caused by typo (copy + paste bug)
cppcheck reports an error:qemu/tcg/mips/tcg-target.c:1487: error: Invalid number of character (()
The unpatched code won't compile on mips hosts starting with commitcea5f9a28faa528b6b1b117c9ab2d8828f473fef....
tcg/README: Expand advice on number of TCG ops per target insn
Expand the note on the number of TCG ops generated per target insn,to be clearer about the range of applicability of the 20 op ruleof thumb. Also add a note about the hard MAX_OP_PER_INSTR limit....
TCG/PPC: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCG temps.