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1	79aceca5	bellard	/*
2	79aceca5	bellard	* PPC emulation for qemu: main translation routines.
3	79aceca5	bellard	*
4	79aceca5	bellard	* Copyright (c) 2003 Jocelyn Mayer
5	79aceca5	bellard	*
6	79aceca5	bellard	* This library is free software; you can redistribute it and/or
7	79aceca5	bellard	* modify it under the terms of the GNU Lesser General Public
8	79aceca5	bellard	* License as published by the Free Software Foundation; either
9	79aceca5	bellard	* version 2 of the License, or (at your option) any later version.
10	79aceca5	bellard	*
11	79aceca5	bellard	* This library is distributed in the hope that it will be useful,
12	79aceca5	bellard	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	79aceca5	bellard	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	79aceca5	bellard	* Lesser General Public License for more details.
15	79aceca5	bellard	*
16	79aceca5	bellard	* You should have received a copy of the GNU Lesser General Public
17	79aceca5	bellard	* License along with this library; if not, write to the Free Software
18	79aceca5	bellard	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19	79aceca5	bellard	*/
20	c6a1c22b	bellard	#include <stdarg.h>
21	c6a1c22b	bellard	#include <stdlib.h>
22	c6a1c22b	bellard	#include <stdio.h>
23	c6a1c22b	bellard	#include <string.h>
24	c6a1c22b	bellard	#include <inttypes.h>
25	c6a1c22b	bellard
26	79aceca5	bellard	#include "cpu.h"
27	c6a1c22b	bellard	#include "exec-all.h"
28	79aceca5	bellard	#include "disas.h"
29	79aceca5	bellard
30	79aceca5	bellard	//#define DO_SINGLE_STEP
31	9fddaa0c	bellard	//#define PPC_DEBUG_DISAS
32	79aceca5	bellard
33	79aceca5	bellard	enum {
34	79aceca5	bellard	#define DEF(s, n, copy_size) INDEX_op_ ## s,
35	79aceca5	bellard	#include "opc.h"
36	79aceca5	bellard	#undef DEF
37	79aceca5	bellard	NB_OPS,
38	79aceca5	bellard	};
39	79aceca5	bellard
40	79aceca5	bellard	static uint16_t *gen_opc_ptr;
41	79aceca5	bellard	static uint32_t *gen_opparam_ptr;
42	79aceca5	bellard
43	79aceca5	bellard	#include "gen-op.h"
44	28b6751f	bellard
45	28b6751f	bellard	#define GEN8(func, NAME) \
46	9a64fbe4	bellard	static GenOpFunc *NAME ## _table [8] = { \
47	9a64fbe4	bellard	NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
48	9a64fbe4	bellard	NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
49	9a64fbe4	bellard	}; \
50	9a64fbe4	bellard	static inline void func(int n) \
51	9a64fbe4	bellard	{ \
52	9a64fbe4	bellard	NAME ## _table[n](); \
53	9a64fbe4	bellard	}
54	9a64fbe4	bellard
55	9a64fbe4	bellard	#define GEN16(func, NAME) \
56	9a64fbe4	bellard	static GenOpFunc *NAME ## _table [16] = { \
57	9a64fbe4	bellard	NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
58	9a64fbe4	bellard	NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
59	9a64fbe4	bellard	NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
60	9a64fbe4	bellard	NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
61	9a64fbe4	bellard	}; \
62	9a64fbe4	bellard	static inline void func(int n) \
63	9a64fbe4	bellard	{ \
64	9a64fbe4	bellard	NAME ## _table[n](); \
65	28b6751f	bellard	}
66	28b6751f	bellard
67	28b6751f	bellard	#define GEN32(func, NAME) \
68	9a64fbe4	bellard	static GenOpFunc *NAME ## _table [32] = { \
69	9a64fbe4	bellard	NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
70	9a64fbe4	bellard	NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
71	9a64fbe4	bellard	NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
72	9a64fbe4	bellard	NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
73	9a64fbe4	bellard	NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
74	9a64fbe4	bellard	NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
75	9a64fbe4	bellard	NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
76	9a64fbe4	bellard	NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
77	9a64fbe4	bellard	}; \
78	9a64fbe4	bellard	static inline void func(int n) \
79	9a64fbe4	bellard	{ \
80	9a64fbe4	bellard	NAME ## _table[n](); \
81	9a64fbe4	bellard	}
82	9a64fbe4	bellard
83	9a64fbe4	bellard	/* Condition register moves */
84	9a64fbe4	bellard	GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
85	9a64fbe4	bellard	GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
86	9a64fbe4	bellard	GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
87	9a64fbe4	bellard	GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
88	28b6751f	bellard
89	fb0eaffc	bellard	/* Floating point condition and status register moves */
90	fb0eaffc	bellard	GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
91	fb0eaffc	bellard	GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
92	fb0eaffc	bellard	GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
93	fb0eaffc	bellard	static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
94	fb0eaffc	bellard	&gen_op_store_T0_fpscri_fpscr0,
95	fb0eaffc	bellard	&gen_op_store_T0_fpscri_fpscr1,
96	fb0eaffc	bellard	&gen_op_store_T0_fpscri_fpscr2,
97	fb0eaffc	bellard	&gen_op_store_T0_fpscri_fpscr3,
98	fb0eaffc	bellard	&gen_op_store_T0_fpscri_fpscr4,
99	fb0eaffc	bellard	&gen_op_store_T0_fpscri_fpscr5,
100	fb0eaffc	bellard	&gen_op_store_T0_fpscri_fpscr6,
101	fb0eaffc	bellard	&gen_op_store_T0_fpscri_fpscr7,
102	fb0eaffc	bellard	};
103	fb0eaffc	bellard	static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
104	fb0eaffc	bellard	{
105	fb0eaffc	bellard	(*gen_op_store_T0_fpscri_fpscr_table[n])(param);
106	fb0eaffc	bellard	}
107	fb0eaffc	bellard
108	9a64fbe4	bellard	/* Segment register moves */
109	9a64fbe4	bellard	GEN16(gen_op_load_sr, gen_op_load_sr);
110	9a64fbe4	bellard	GEN16(gen_op_store_sr, gen_op_store_sr);
111	28b6751f	bellard
112	9a64fbe4	bellard	/* General purpose registers moves */
113	9a64fbe4	bellard	GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
114	9a64fbe4	bellard	GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
115	9a64fbe4	bellard	GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
116	9a64fbe4	bellard
117	9a64fbe4	bellard	GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
118	9a64fbe4	bellard	GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
119	9a64fbe4	bellard	GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
120	28b6751f	bellard
121	fb0eaffc	bellard	/* floating point registers moves */
122	fb0eaffc	bellard	GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
123	fb0eaffc	bellard	GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
124	fb0eaffc	bellard	GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
125	fb0eaffc	bellard	GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
126	fb0eaffc	bellard	GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
127	fb0eaffc	bellard	GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
128	79aceca5	bellard
129	79aceca5	bellard	static uint8_t spr_access[1024 / 2];
130	79aceca5	bellard
131	79aceca5	bellard	/* internal defines */
132	79aceca5	bellard	typedef struct DisasContext {
133	79aceca5	bellard	struct TranslationBlock *tb;
134	046d6672	bellard	uint32_t nip;
135	79aceca5	bellard	uint32_t opcode;
136	9a64fbe4	bellard	uint32_t exception;
137	9a64fbe4	bellard	/* Execution mode */
138	9a64fbe4	bellard	#if !defined(CONFIG_USER_ONLY)
139	79aceca5	bellard	int supervisor;
140	9a64fbe4	bellard	#endif
141	9a64fbe4	bellard	/* Routine used to access memory */
142	9a64fbe4	bellard	int mem_idx;
143	79aceca5	bellard	} DisasContext;
144	79aceca5	bellard
145	79aceca5	bellard	typedef struct opc_handler_t {
146	79aceca5	bellard	/* invalid bits */
147	79aceca5	bellard	uint32_t inval;
148	9a64fbe4	bellard	/* instruction type */
149	9a64fbe4	bellard	uint32_t type;
150	79aceca5	bellard	/* handler */
151	79aceca5	bellard	void (handler)(DisasContext ctx);
152	79aceca5	bellard	} opc_handler_t;
153	79aceca5	bellard
154	9fddaa0c	bellard	#define RET_EXCP(ctx, excp, error) \
155	79aceca5	bellard	do { \
156	9fddaa0c	bellard	if ((ctx)->exception == EXCP_NONE) { \
157	9fddaa0c	bellard	gen_op_update_nip((ctx)->nip); \
158	9fddaa0c	bellard	} \
159	9fddaa0c	bellard	gen_op_raise_exception_err((excp), (error)); \
160	9fddaa0c	bellard	ctx->exception = (excp); \
161	79aceca5	bellard	} while (0)
162	79aceca5	bellard
163	9fddaa0c	bellard	#define RET_INVAL(ctx) \
164	9fddaa0c	bellard	RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL \| EXCP_INVAL_INVAL)
165	9fddaa0c	bellard
166	9fddaa0c	bellard	#define RET_PRIVOPC(ctx) \
167	9fddaa0c	bellard	RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL \| EXCP_PRIV_OPC)
168	9a64fbe4	bellard
169	9fddaa0c	bellard	#define RET_PRIVREG(ctx) \
170	9fddaa0c	bellard	RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL \| EXCP_PRIV_REG)
171	9a64fbe4	bellard
172	9fddaa0c	bellard	#define RET_MTMSR(ctx) \
173	9fddaa0c	bellard	RET_EXCP((ctx), EXCP_MTMSR, 0)
174	79aceca5	bellard
175	79aceca5	bellard	#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
176	79aceca5	bellard	static void gen_##name (DisasContext *ctx); \
177	79aceca5	bellard	GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
178	79aceca5	bellard	static void gen_##name (DisasContext *ctx)
179	79aceca5	bellard
180	79aceca5	bellard	typedef struct opcode_t {
181	79aceca5	bellard	unsigned char opc1, opc2, opc3;
182	79aceca5	bellard	opc_handler_t handler;
183	79aceca5	bellard	} opcode_t;
184	79aceca5	bellard
185	79aceca5	bellard	/* Instruction decoding */
186	79aceca5	bellard	#define EXTRACT_HELPER(name, shift, nb) \
187	79aceca5	bellard	static inline uint32_t name (uint32_t opcode) \
188	79aceca5	bellard	{ \
189	79aceca5	bellard	return (opcode >> (shift)) & ((1 << (nb)) - 1); \
190	79aceca5	bellard	}
191	79aceca5	bellard
192	79aceca5	bellard	#define EXTRACT_SHELPER(name, shift, nb) \
193	79aceca5	bellard	static inline int32_t name (uint32_t opcode) \
194	79aceca5	bellard	{ \
195	79aceca5	bellard	return s_ext16((opcode >> (shift)) & ((1 << (nb)) - 1)); \
196	79aceca5	bellard	}
197	79aceca5	bellard
198	79aceca5	bellard	/* Opcode part 1 */
199	79aceca5	bellard	EXTRACT_HELPER(opc1, 26, 6);
200	79aceca5	bellard	/* Opcode part 2 */
201	79aceca5	bellard	EXTRACT_HELPER(opc2, 1, 5);
202	79aceca5	bellard	/* Opcode part 3 */
203	79aceca5	bellard	EXTRACT_HELPER(opc3, 6, 5);
204	79aceca5	bellard	/* Update Cr0 flags */
205	79aceca5	bellard	EXTRACT_HELPER(Rc, 0, 1);
206	79aceca5	bellard	/* Destination */
207	79aceca5	bellard	EXTRACT_HELPER(rD, 21, 5);
208	79aceca5	bellard	/* Source */
209	79aceca5	bellard	EXTRACT_HELPER(rS, 21, 5);
210	79aceca5	bellard	/* First operand */
211	79aceca5	bellard	EXTRACT_HELPER(rA, 16, 5);
212	79aceca5	bellard	/* Second operand */
213	79aceca5	bellard	EXTRACT_HELPER(rB, 11, 5);
214	79aceca5	bellard	/* Third operand */
215	79aceca5	bellard	EXTRACT_HELPER(rC, 6, 5);
216	79aceca5	bellard	/* Get CRn */
217	79aceca5	bellard	EXTRACT_HELPER(crfD, 23, 3);
218	79aceca5	bellard	EXTRACT_HELPER(crfS, 18, 3);
219	79aceca5	bellard	EXTRACT_HELPER(crbD, 21, 5);
220	79aceca5	bellard	EXTRACT_HELPER(crbA, 16, 5);
221	79aceca5	bellard	EXTRACT_HELPER(crbB, 11, 5);
222	79aceca5	bellard	/* SPR / TBL */
223	79aceca5	bellard	EXTRACT_HELPER(SPR, 11, 10);
224	79aceca5	bellard	/* Get constants */
225	79aceca5	bellard	EXTRACT_HELPER(IMM, 12, 8);
226	79aceca5	bellard	/* 16 bits signed immediate value */
227	79aceca5	bellard	EXTRACT_SHELPER(SIMM, 0, 16);
228	79aceca5	bellard	/* 16 bits unsigned immediate value */
229	79aceca5	bellard	EXTRACT_HELPER(UIMM, 0, 16);
230	79aceca5	bellard	/* Bit count */
231	79aceca5	bellard	EXTRACT_HELPER(NB, 11, 5);
232	79aceca5	bellard	/* Shift count */
233	79aceca5	bellard	EXTRACT_HELPER(SH, 11, 5);
234	79aceca5	bellard	/* Mask start */
235	79aceca5	bellard	EXTRACT_HELPER(MB, 6, 5);
236	79aceca5	bellard	/* Mask end */
237	79aceca5	bellard	EXTRACT_HELPER(ME, 1, 5);
238	fb0eaffc	bellard	/* Trap operand */
239	fb0eaffc	bellard	EXTRACT_HELPER(TO, 21, 5);
240	79aceca5	bellard
241	79aceca5	bellard	EXTRACT_HELPER(CRM, 12, 8);
242	79aceca5	bellard	EXTRACT_HELPER(FM, 17, 8);
243	79aceca5	bellard	EXTRACT_HELPER(SR, 16, 4);
244	fb0eaffc	bellard	EXTRACT_HELPER(FPIMM, 20, 4);
245	fb0eaffc	bellard
246	79aceca5	bellard	/* Jump target decoding */
247	79aceca5	bellard	/* Displacement */
248	79aceca5	bellard	EXTRACT_SHELPER(d, 0, 16);
249	79aceca5	bellard	/* Immediate address */
250	79aceca5	bellard	static inline uint32_t LI (uint32_t opcode)
251	79aceca5	bellard	{
252	79aceca5	bellard	return (opcode >> 0) & 0x03FFFFFC;
253	79aceca5	bellard	}
254	79aceca5	bellard
255	79aceca5	bellard	static inline uint32_t BD (uint32_t opcode)
256	79aceca5	bellard	{
257	79aceca5	bellard	return (opcode >> 0) & 0xFFFC;
258	79aceca5	bellard	}
259	79aceca5	bellard
260	79aceca5	bellard	EXTRACT_HELPER(BO, 21, 5);
261	79aceca5	bellard	EXTRACT_HELPER(BI, 16, 5);
262	79aceca5	bellard	/* Absolute/relative address */
263	79aceca5	bellard	EXTRACT_HELPER(AA, 1, 1);
264	79aceca5	bellard	/* Link */
265	79aceca5	bellard	EXTRACT_HELPER(LK, 0, 1);
266	79aceca5	bellard
267	79aceca5	bellard	/* Create a mask between <start> and <end> bits */
268	79aceca5	bellard	static inline uint32_t MASK (uint32_t start, uint32_t end)
269	79aceca5	bellard	{
270	79aceca5	bellard	uint32_t ret;
271	79aceca5	bellard
272	79aceca5	bellard	ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
273	79aceca5	bellard	if (start > end)
274	79aceca5	bellard	return ~ret;
275	79aceca5	bellard
276	79aceca5	bellard	return ret;
277	79aceca5	bellard	}
278	79aceca5	bellard
279	79aceca5	bellard	#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
280	1ef59d0a	bellard	__attribute__ ((section(".opcodes"), unused, aligned (8) )) \
281	79aceca5	bellard	static opcode_t opc_##name = { \
282	79aceca5	bellard	.opc1 = op1, \
283	79aceca5	bellard	.opc2 = op2, \
284	79aceca5	bellard	.opc3 = op3, \
285	79aceca5	bellard	.handler = { \
286	79aceca5	bellard	.inval = invl, \
287	9a64fbe4	bellard	.type = _typ, \
288	79aceca5	bellard	.handler = &gen_##name, \
289	79aceca5	bellard	}, \
290	79aceca5	bellard	}
291	79aceca5	bellard
292	79aceca5	bellard	#define GEN_OPCODE_MARK(name) \
293	1ef59d0a	bellard	__attribute__ ((section(".opcodes"), unused, aligned (8) )) \
294	79aceca5	bellard	static opcode_t opc_##name = { \
295	79aceca5	bellard	.opc1 = 0xFF, \
296	79aceca5	bellard	.opc2 = 0xFF, \
297	79aceca5	bellard	.opc3 = 0xFF, \
298	79aceca5	bellard	.handler = { \
299	79aceca5	bellard	.inval = 0x00000000, \
300	9a64fbe4	bellard	.type = 0x00, \
301	79aceca5	bellard	.handler = NULL, \
302	79aceca5	bellard	}, \
303	79aceca5	bellard	}
304	79aceca5	bellard
305	79aceca5	bellard	/* Start opcode list */
306	79aceca5	bellard	GEN_OPCODE_MARK(start);
307	79aceca5	bellard
308	79aceca5	bellard	/* Invalid instruction */
309	9a64fbe4	bellard	GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
310	9a64fbe4	bellard	{
311	9fddaa0c	bellard	RET_INVAL(ctx);
312	9a64fbe4	bellard	}
313	9a64fbe4	bellard
314	9a64fbe4	bellard	/* Special opcode to stop emulation */
315	9a64fbe4	bellard	GEN_HANDLER(stop, 0x06, 0x00, 0xFF, 0x03FFFFC1, PPC_COMMON)
316	79aceca5	bellard	{
317	9fddaa0c	bellard	RET_EXCP(ctx, EXCP_HLT, 0);
318	9a64fbe4	bellard	}
319	9a64fbe4	bellard
320	9a64fbe4	bellard	/* Special opcode to call open-firmware */
321	9a64fbe4	bellard	GEN_HANDLER(of_enter, 0x06, 0x01, 0xFF, 0x03FFFFC1, PPC_COMMON)
322	9a64fbe4	bellard	{
323	9fddaa0c	bellard	RET_EXCP(ctx, EXCP_OFCALL, 0);
324	9a64fbe4	bellard	}
325	9a64fbe4	bellard
326	9a64fbe4	bellard	/* Special opcode to call RTAS */
327	9a64fbe4	bellard	GEN_HANDLER(rtas_enter, 0x06, 0x02, 0xFF, 0x03FFFFC1, PPC_COMMON)
328	9a64fbe4	bellard	{
329	9a64fbe4	bellard	printf("RTAS entry point !\n");
330	9fddaa0c	bellard	RET_EXCP(ctx, EXCP_RTASCALL, 0);
331	79aceca5	bellard	}
332	79aceca5	bellard
333	79aceca5	bellard	static opc_handler_t invalid_handler = {
334	79aceca5	bellard	.inval = 0xFFFFFFFF,
335	9a64fbe4	bellard	.type = PPC_NONE,
336	79aceca5	bellard	.handler = gen_invalid,
337	79aceca5	bellard	};
338	79aceca5	bellard
339	79aceca5	bellard	/* Integer arithmetic */
340	79aceca5	bellard	#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
341	79aceca5	bellard	GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
342	79aceca5	bellard	{ \
343	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
344	79aceca5	bellard	gen_op_load_gpr_T1(rB(ctx->opcode)); \
345	79aceca5	bellard	gen_op_##name(); \
346	79aceca5	bellard	if (Rc(ctx->opcode) != 0) \
347	79aceca5	bellard	gen_op_set_Rc0(); \
348	79aceca5	bellard	gen_op_store_T0_gpr(rD(ctx->opcode)); \
349	79aceca5	bellard	}
350	79aceca5	bellard
351	79aceca5	bellard	#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
352	79aceca5	bellard	GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
353	79aceca5	bellard	{ \
354	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
355	79aceca5	bellard	gen_op_load_gpr_T1(rB(ctx->opcode)); \
356	79aceca5	bellard	gen_op_##name(); \
357	79aceca5	bellard	if (Rc(ctx->opcode) != 0) \
358	79aceca5	bellard	gen_op_set_Rc0_ov(); \
359	79aceca5	bellard	gen_op_store_T0_gpr(rD(ctx->opcode)); \
360	79aceca5	bellard	}
361	79aceca5	bellard
362	79aceca5	bellard	#define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
363	79aceca5	bellard	GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
364	79aceca5	bellard	{ \
365	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
366	79aceca5	bellard	gen_op_##name(); \
367	79aceca5	bellard	if (Rc(ctx->opcode) != 0) \
368	79aceca5	bellard	gen_op_set_Rc0(); \
369	79aceca5	bellard	gen_op_store_T0_gpr(rD(ctx->opcode)); \
370	79aceca5	bellard	}
371	79aceca5	bellard	#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
372	79aceca5	bellard	GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
373	79aceca5	bellard	{ \
374	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
375	79aceca5	bellard	gen_op_##name(); \
376	79aceca5	bellard	if (Rc(ctx->opcode) != 0) \
377	79aceca5	bellard	gen_op_set_Rc0_ov(); \
378	79aceca5	bellard	gen_op_store_T0_gpr(rD(ctx->opcode)); \
379	79aceca5	bellard	}
380	79aceca5	bellard
381	79aceca5	bellard	/* Two operands arithmetic functions */
382	79aceca5	bellard	#define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
383	79aceca5	bellard	__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
384	79aceca5	bellard	__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 \| 0x10, 0x00000000)
385	79aceca5	bellard
386	79aceca5	bellard	/* Two operands arithmetic functions with no overflow allowed */
387	79aceca5	bellard	#define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
388	79aceca5	bellard	__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
389	79aceca5	bellard
390	79aceca5	bellard	/* One operand arithmetic functions */
391	79aceca5	bellard	#define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
392	79aceca5	bellard	__GEN_INT_ARITH1(name, opc1, opc2, opc3) \
393	79aceca5	bellard	__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 \| 0x10)
394	79aceca5	bellard
395	79aceca5	bellard	/* add add. addo addo. */
396	79aceca5	bellard	GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08);
397	79aceca5	bellard	/* addc addc. addco addco. */
398	79aceca5	bellard	GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00);
399	79aceca5	bellard	/* adde adde. addeo addeo. */
400	79aceca5	bellard	GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04);
401	79aceca5	bellard	/* addme addme. addmeo addmeo. */
402	79aceca5	bellard	GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07);
403	79aceca5	bellard	/* addze addze. addzeo addzeo. */
404	79aceca5	bellard	GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06);
405	79aceca5	bellard	/* divw divw. divwo divwo. */
406	79aceca5	bellard	GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F);
407	79aceca5	bellard	/* divwu divwu. divwuo divwuo. */
408	79aceca5	bellard	GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E);
409	79aceca5	bellard	/* mulhw mulhw. */
410	79aceca5	bellard	GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02);
411	79aceca5	bellard	/* mulhwu mulhwu. */
412	79aceca5	bellard	GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
413	79aceca5	bellard	/* mullw mullw. mullwo mullwo. */
414	79aceca5	bellard	GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07);
415	79aceca5	bellard	/* neg neg. nego nego. */
416	79aceca5	bellard	GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03);
417	79aceca5	bellard	/* subf subf. subfo subfo. */
418	79aceca5	bellard	GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01);
419	79aceca5	bellard	/* subfc subfc. subfco subfco. */
420	79aceca5	bellard	GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00);
421	79aceca5	bellard	/* subfe subfe. subfeo subfeo. */
422	79aceca5	bellard	GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04);
423	79aceca5	bellard	/* subfme subfme. subfmeo subfmeo. */
424	79aceca5	bellard	GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
425	79aceca5	bellard	/* subfze subfze. subfzeo subfzeo. */
426	79aceca5	bellard	GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
427	79aceca5	bellard	/* addi */
428	79aceca5	bellard	GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
429	79aceca5	bellard	{
430	79aceca5	bellard	int32_t simm = SIMM(ctx->opcode);
431	79aceca5	bellard
432	79aceca5	bellard	if (rA(ctx->opcode) == 0) {
433	79aceca5	bellard	gen_op_set_T0(simm);
434	79aceca5	bellard	} else {
435	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
436	79aceca5	bellard	gen_op_addi(simm);
437	79aceca5	bellard	}
438	79aceca5	bellard	gen_op_store_T0_gpr(rD(ctx->opcode));
439	79aceca5	bellard	}
440	79aceca5	bellard	/* addic */
441	79aceca5	bellard	GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
442	79aceca5	bellard	{
443	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
444	79aceca5	bellard	gen_op_addic(SIMM(ctx->opcode));
445	79aceca5	bellard	gen_op_store_T0_gpr(rD(ctx->opcode));
446	79aceca5	bellard	}
447	79aceca5	bellard	/* addic. */
448	79aceca5	bellard	GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
449	79aceca5	bellard	{
450	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
451	79aceca5	bellard	gen_op_addic(SIMM(ctx->opcode));
452	79aceca5	bellard	gen_op_set_Rc0();
453	79aceca5	bellard	gen_op_store_T0_gpr(rD(ctx->opcode));
454	79aceca5	bellard	}
455	79aceca5	bellard	/* addis */
456	79aceca5	bellard	GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
457	79aceca5	bellard	{
458	79aceca5	bellard	int32_t simm = SIMM(ctx->opcode);
459	79aceca5	bellard
460	79aceca5	bellard	if (rA(ctx->opcode) == 0) {
461	79aceca5	bellard	gen_op_set_T0(simm << 16);
462	79aceca5	bellard	} else {
463	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
464	79aceca5	bellard	gen_op_addi(simm << 16);
465	79aceca5	bellard	}
466	79aceca5	bellard	gen_op_store_T0_gpr(rD(ctx->opcode));
467	79aceca5	bellard	}
468	79aceca5	bellard	/* mulli */
469	79aceca5	bellard	GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
470	79aceca5	bellard	{
471	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
472	79aceca5	bellard	gen_op_mulli(SIMM(ctx->opcode));
473	79aceca5	bellard	gen_op_store_T0_gpr(rD(ctx->opcode));
474	79aceca5	bellard	}
475	79aceca5	bellard	/* subfic */
476	79aceca5	bellard	GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
477	79aceca5	bellard	{
478	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
479	79aceca5	bellard	gen_op_subfic(SIMM(ctx->opcode));
480	79aceca5	bellard	gen_op_store_T0_gpr(rD(ctx->opcode));
481	79aceca5	bellard	}
482	79aceca5	bellard
483	79aceca5	bellard	/* Integer comparison */
484	79aceca5	bellard	#define GEN_CMP(name, opc) \
485	79aceca5	bellard	GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
486	79aceca5	bellard	{ \
487	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
488	79aceca5	bellard	gen_op_load_gpr_T1(rB(ctx->opcode)); \
489	79aceca5	bellard	gen_op_##name(); \
490	79aceca5	bellard	gen_op_store_T0_crf(crfD(ctx->opcode)); \
491	79aceca5	bellard	}
492	79aceca5	bellard
493	79aceca5	bellard	/* cmp */
494	79aceca5	bellard	GEN_CMP(cmp, 0x00);
495	79aceca5	bellard	/* cmpi */
496	79aceca5	bellard	GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
497	79aceca5	bellard	{
498	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
499	79aceca5	bellard	gen_op_cmpi(SIMM(ctx->opcode));
500	79aceca5	bellard	gen_op_store_T0_crf(crfD(ctx->opcode));
501	79aceca5	bellard	}
502	79aceca5	bellard	/* cmpl */
503	79aceca5	bellard	GEN_CMP(cmpl, 0x01);
504	79aceca5	bellard	/* cmpli */
505	79aceca5	bellard	GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
506	79aceca5	bellard	{
507	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
508	79aceca5	bellard	gen_op_cmpli(UIMM(ctx->opcode));
509	79aceca5	bellard	gen_op_store_T0_crf(crfD(ctx->opcode));
510	79aceca5	bellard	}
511	79aceca5	bellard
512	79aceca5	bellard	/* Integer logical */
513	79aceca5	bellard	#define __GEN_LOGICAL2(name, opc2, opc3) \
514	79aceca5	bellard	GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
515	79aceca5	bellard	{ \
516	79aceca5	bellard	gen_op_load_gpr_T0(rS(ctx->opcode)); \
517	79aceca5	bellard	gen_op_load_gpr_T1(rB(ctx->opcode)); \
518	79aceca5	bellard	gen_op_##name(); \
519	79aceca5	bellard	if (Rc(ctx->opcode) != 0) \
520	79aceca5	bellard	gen_op_set_Rc0(); \
521	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode)); \
522	79aceca5	bellard	}
523	79aceca5	bellard	#define GEN_LOGICAL2(name, opc) \
524	79aceca5	bellard	__GEN_LOGICAL2(name, 0x1C, opc)
525	79aceca5	bellard
526	79aceca5	bellard	#define GEN_LOGICAL1(name, opc) \
527	79aceca5	bellard	GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
528	79aceca5	bellard	{ \
529	79aceca5	bellard	gen_op_load_gpr_T0(rS(ctx->opcode)); \
530	79aceca5	bellard	gen_op_##name(); \
531	79aceca5	bellard	if (Rc(ctx->opcode) != 0) \
532	79aceca5	bellard	gen_op_set_Rc0(); \
533	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode)); \
534	79aceca5	bellard	}
535	79aceca5	bellard
536	79aceca5	bellard	/* and & and. */
537	79aceca5	bellard	GEN_LOGICAL2(and, 0x00);
538	79aceca5	bellard	/* andc & andc. */
539	79aceca5	bellard	GEN_LOGICAL2(andc, 0x01);
540	79aceca5	bellard	/* andi. */
541	79aceca5	bellard	GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
542	79aceca5	bellard	{
543	79aceca5	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
544	79aceca5	bellard	gen_op_andi_(UIMM(ctx->opcode));
545	79aceca5	bellard	gen_op_set_Rc0();
546	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode));
547	79aceca5	bellard	}
548	79aceca5	bellard	/* andis. */
549	79aceca5	bellard	GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
550	79aceca5	bellard	{
551	79aceca5	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
552	79aceca5	bellard	gen_op_andi_(UIMM(ctx->opcode) << 16);
553	79aceca5	bellard	gen_op_set_Rc0();
554	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode));
555	79aceca5	bellard	}
556	79aceca5	bellard
557	79aceca5	bellard	/* cntlzw */
558	79aceca5	bellard	GEN_LOGICAL1(cntlzw, 0x00);
559	79aceca5	bellard	/* eqv & eqv. */
560	79aceca5	bellard	GEN_LOGICAL2(eqv, 0x08);
561	79aceca5	bellard	/* extsb & extsb. */
562	79aceca5	bellard	GEN_LOGICAL1(extsb, 0x1D);
563	79aceca5	bellard	/* extsh & extsh. */
564	79aceca5	bellard	GEN_LOGICAL1(extsh, 0x1C);
565	79aceca5	bellard	/* nand & nand. */
566	79aceca5	bellard	GEN_LOGICAL2(nand, 0x0E);
567	79aceca5	bellard	/* nor & nor. */
568	79aceca5	bellard	GEN_LOGICAL2(nor, 0x03);
569	9a64fbe4	bellard
570	79aceca5	bellard	/* or & or. */
571	9a64fbe4	bellard	GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
572	9a64fbe4	bellard	{
573	9a64fbe4	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
574	9a64fbe4	bellard	/* Optimisation for mr case */
575	9a64fbe4	bellard	if (rS(ctx->opcode) != rB(ctx->opcode)) {
576	9a64fbe4	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
577	9a64fbe4	bellard	gen_op_or();
578	9a64fbe4	bellard	}
579	9a64fbe4	bellard	if (Rc(ctx->opcode) != 0)
580	9a64fbe4	bellard	gen_op_set_Rc0();
581	9a64fbe4	bellard	gen_op_store_T0_gpr(rA(ctx->opcode));
582	9a64fbe4	bellard	}
583	9a64fbe4	bellard
584	79aceca5	bellard	/* orc & orc. */
585	79aceca5	bellard	GEN_LOGICAL2(orc, 0x0C);
586	79aceca5	bellard	/* xor & xor. */
587	9a64fbe4	bellard	GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
588	9a64fbe4	bellard	{
589	9a64fbe4	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
590	9a64fbe4	bellard	/* Optimisation for "set to zero" case */
591	9a64fbe4	bellard	if (rS(ctx->opcode) != rB(ctx->opcode)) {
592	9a64fbe4	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
593	9a64fbe4	bellard	gen_op_xor();
594	9a64fbe4	bellard	} else {
595	9a64fbe4	bellard	gen_op_set_T0(0);
596	9a64fbe4	bellard	}
597	9a64fbe4	bellard	if (Rc(ctx->opcode) != 0)
598	9a64fbe4	bellard	gen_op_set_Rc0();
599	9a64fbe4	bellard	gen_op_store_T0_gpr(rA(ctx->opcode));
600	9a64fbe4	bellard	}
601	79aceca5	bellard	/* ori */
602	79aceca5	bellard	GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
603	79aceca5	bellard	{
604	79aceca5	bellard	uint32_t uimm = UIMM(ctx->opcode);
605	79aceca5	bellard
606	9a64fbe4	bellard	if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
607	9a64fbe4	bellard	/* NOP */
608	9a64fbe4	bellard	return;
609	79aceca5	bellard	}
610	79aceca5	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
611	9a64fbe4	bellard	if (uimm != 0)
612	79aceca5	bellard	gen_op_ori(uimm);
613	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode));
614	79aceca5	bellard	}
615	79aceca5	bellard	/* oris */
616	79aceca5	bellard	GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
617	79aceca5	bellard	{
618	79aceca5	bellard	uint32_t uimm = UIMM(ctx->opcode);
619	79aceca5	bellard
620	9a64fbe4	bellard	if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
621	9a64fbe4	bellard	/* NOP */
622	9a64fbe4	bellard	return;
623	79aceca5	bellard	}
624	79aceca5	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
625	9a64fbe4	bellard	if (uimm != 0)
626	79aceca5	bellard	gen_op_ori(uimm << 16);
627	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode));
628	79aceca5	bellard	}
629	79aceca5	bellard	/* xori */
630	79aceca5	bellard	GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
631	79aceca5	bellard	{
632	9a64fbe4	bellard	uint32_t uimm = UIMM(ctx->opcode);
633	9a64fbe4	bellard
634	9a64fbe4	bellard	if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
635	9a64fbe4	bellard	/* NOP */
636	9a64fbe4	bellard	return;
637	9a64fbe4	bellard	}
638	79aceca5	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
639	9a64fbe4	bellard	if (uimm != 0)
640	4b3686fa	bellard	gen_op_xori(uimm);
641	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode));
642	79aceca5	bellard	}
643	79aceca5	bellard
644	79aceca5	bellard	/* xoris */
645	79aceca5	bellard	GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
646	79aceca5	bellard	{
647	9a64fbe4	bellard	uint32_t uimm = UIMM(ctx->opcode);
648	9a64fbe4	bellard
649	9a64fbe4	bellard	if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
650	9a64fbe4	bellard	/* NOP */
651	9a64fbe4	bellard	return;
652	9a64fbe4	bellard	}
653	79aceca5	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
654	9a64fbe4	bellard	if (uimm != 0)
655	4b3686fa	bellard	gen_op_xori(uimm << 16);
656	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode));
657	79aceca5	bellard	}
658	79aceca5	bellard
659	79aceca5	bellard	/* Integer rotate */
660	79aceca5	bellard	/* rlwimi & rlwimi. */
661	79aceca5	bellard	GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
662	79aceca5	bellard	{
663	79aceca5	bellard	uint32_t mb, me;
664	79aceca5	bellard
665	79aceca5	bellard	mb = MB(ctx->opcode);
666	79aceca5	bellard	me = ME(ctx->opcode);
667	79aceca5	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
668	fb0eaffc	bellard	gen_op_load_gpr_T1(rA(ctx->opcode));
669	79aceca5	bellard	gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
670	79aceca5	bellard	if (Rc(ctx->opcode) != 0)
671	79aceca5	bellard	gen_op_set_Rc0();
672	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode));
673	79aceca5	bellard	}
674	79aceca5	bellard	/* rlwinm & rlwinm. */
675	79aceca5	bellard	GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
676	79aceca5	bellard	{
677	79aceca5	bellard	uint32_t mb, me, sh;
678	79aceca5	bellard
679	79aceca5	bellard	sh = SH(ctx->opcode);
680	79aceca5	bellard	mb = MB(ctx->opcode);
681	79aceca5	bellard	me = ME(ctx->opcode);
682	79aceca5	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
683	4b3686fa	bellard	#if 1 // TRY
684	4b3686fa	bellard	if (sh == 0) {
685	4b3686fa	bellard	gen_op_andi_(MASK(mb, me));
686	4b3686fa	bellard	goto store;
687	4b3686fa	bellard	}
688	4b3686fa	bellard	#endif
689	79aceca5	bellard	if (mb == 0) {
690	79aceca5	bellard	if (me == 31) {
691	79aceca5	bellard	gen_op_rotlwi(sh);
692	79aceca5	bellard	goto store;
693	4b3686fa	bellard	#if 0
694	79aceca5	bellard	} else if (me == (31 - sh)) {
695	79aceca5	bellard	gen_op_slwi(sh);
696	79aceca5	bellard	goto store;
697	4b3686fa	bellard	#endif
698	79aceca5	bellard	}
699	79aceca5	bellard	} else if (me == 31) {
700	4b3686fa	bellard	#if 0
701	79aceca5	bellard	if (sh == (32 - mb)) {
702	79aceca5	bellard	gen_op_srwi(mb);
703	79aceca5	bellard	goto store;
704	79aceca5	bellard	}
705	4b3686fa	bellard	#endif
706	79aceca5	bellard	}
707	79aceca5	bellard	gen_op_rlwinm(sh, MASK(mb, me));
708	79aceca5	bellard	store:
709	79aceca5	bellard	if (Rc(ctx->opcode) != 0)
710	79aceca5	bellard	gen_op_set_Rc0();
711	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode));
712	79aceca5	bellard	}
713	79aceca5	bellard	/* rlwnm & rlwnm. */
714	79aceca5	bellard	GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
715	79aceca5	bellard	{
716	79aceca5	bellard	uint32_t mb, me;
717	79aceca5	bellard
718	79aceca5	bellard	mb = MB(ctx->opcode);
719	79aceca5	bellard	me = ME(ctx->opcode);
720	79aceca5	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
721	79aceca5	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
722	79aceca5	bellard	if (mb == 0 && me == 31) {
723	79aceca5	bellard	gen_op_rotl();
724	79aceca5	bellard	} else
725	79aceca5	bellard	{
726	79aceca5	bellard	gen_op_rlwnm(MASK(mb, me));
727	79aceca5	bellard	}
728	79aceca5	bellard	if (Rc(ctx->opcode) != 0)
729	79aceca5	bellard	gen_op_set_Rc0();
730	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode));
731	79aceca5	bellard	}
732	79aceca5	bellard
733	79aceca5	bellard	/* Integer shift */
734	79aceca5	bellard	/* slw & slw. */
735	79aceca5	bellard	__GEN_LOGICAL2(slw, 0x18, 0x00);
736	79aceca5	bellard	/* sraw & sraw. */
737	79aceca5	bellard	__GEN_LOGICAL2(sraw, 0x18, 0x18);
738	79aceca5	bellard	/* srawi & srawi. */
739	79aceca5	bellard	GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
740	79aceca5	bellard	{
741	79aceca5	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
742	79aceca5	bellard	gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
743	79aceca5	bellard	if (Rc(ctx->opcode) != 0)
744	79aceca5	bellard	gen_op_set_Rc0();
745	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode));
746	79aceca5	bellard	}
747	79aceca5	bellard	/* srw & srw. */
748	79aceca5	bellard	__GEN_LOGICAL2(srw, 0x18, 0x10);
749	79aceca5	bellard
750	79aceca5	bellard	/* Floating-Point arithmetic */
751	9a64fbe4	bellard	#define _GEN_FLOAT_ACB(name, op1, op2) \
752	9a64fbe4	bellard	GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
753	9a64fbe4	bellard	{ \
754	9a64fbe4	bellard	gen_op_reset_scrfx(); \
755	9a64fbe4	bellard	gen_op_load_fpr_FT0(rA(ctx->opcode)); \
756	9a64fbe4	bellard	gen_op_load_fpr_FT1(rC(ctx->opcode)); \
757	9a64fbe4	bellard	gen_op_load_fpr_FT2(rB(ctx->opcode)); \
758	9a64fbe4	bellard	gen_op_f##name(); \
759	9a64fbe4	bellard	gen_op_store_FT0_fpr(rD(ctx->opcode)); \
760	9a64fbe4	bellard	if (Rc(ctx->opcode)) \
761	9a64fbe4	bellard	gen_op_set_Rc1(); \
762	9a64fbe4	bellard	}
763	9a64fbe4	bellard
764	9a64fbe4	bellard	#define GEN_FLOAT_ACB(name, op2) \
765	9a64fbe4	bellard	_GEN_FLOAT_ACB(name, 0x3F, op2); \
766	9a64fbe4	bellard	_GEN_FLOAT_ACB(name##s, 0x3B, op2);
767	9a64fbe4	bellard
768	9a64fbe4	bellard	#define _GEN_FLOAT_AB(name, op1, op2, inval) \
769	9a64fbe4	bellard	GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
770	9a64fbe4	bellard	{ \
771	9a64fbe4	bellard	gen_op_reset_scrfx(); \
772	9a64fbe4	bellard	gen_op_load_fpr_FT0(rA(ctx->opcode)); \
773	9a64fbe4	bellard	gen_op_load_fpr_FT1(rB(ctx->opcode)); \
774	9a64fbe4	bellard	gen_op_f##name(); \
775	9a64fbe4	bellard	gen_op_store_FT0_fpr(rD(ctx->opcode)); \
776	9a64fbe4	bellard	if (Rc(ctx->opcode)) \
777	9a64fbe4	bellard	gen_op_set_Rc1(); \
778	9a64fbe4	bellard	}
779	9a64fbe4	bellard	#define GEN_FLOAT_AB(name, op2, inval) \
780	9a64fbe4	bellard	_GEN_FLOAT_AB(name, 0x3F, op2, inval); \
781	9a64fbe4	bellard	_GEN_FLOAT_AB(name##s, 0x3B, op2, inval);
782	9a64fbe4	bellard
783	9a64fbe4	bellard	#define _GEN_FLOAT_AC(name, op1, op2, inval) \
784	9a64fbe4	bellard	GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
785	9a64fbe4	bellard	{ \
786	9a64fbe4	bellard	gen_op_reset_scrfx(); \
787	9a64fbe4	bellard	gen_op_load_fpr_FT0(rA(ctx->opcode)); \
788	9a64fbe4	bellard	gen_op_load_fpr_FT1(rC(ctx->opcode)); \
789	9a64fbe4	bellard	gen_op_f##name(); \
790	9a64fbe4	bellard	gen_op_store_FT0_fpr(rD(ctx->opcode)); \
791	9a64fbe4	bellard	if (Rc(ctx->opcode)) \
792	9a64fbe4	bellard	gen_op_set_Rc1(); \
793	9a64fbe4	bellard	}
794	9a64fbe4	bellard	#define GEN_FLOAT_AC(name, op2, inval) \
795	9a64fbe4	bellard	_GEN_FLOAT_AC(name, 0x3F, op2, inval); \
796	9a64fbe4	bellard	_GEN_FLOAT_AC(name##s, 0x3B, op2, inval);
797	9a64fbe4	bellard
798	9a64fbe4	bellard	#define GEN_FLOAT_B(name, op2, op3) \
799	9a64fbe4	bellard	GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
800	9a64fbe4	bellard	{ \
801	9a64fbe4	bellard	gen_op_reset_scrfx(); \
802	9a64fbe4	bellard	gen_op_load_fpr_FT0(rB(ctx->opcode)); \
803	9a64fbe4	bellard	gen_op_f##name(); \
804	9a64fbe4	bellard	gen_op_store_FT0_fpr(rD(ctx->opcode)); \
805	9a64fbe4	bellard	if (Rc(ctx->opcode)) \
806	9a64fbe4	bellard	gen_op_set_Rc1(); \
807	79aceca5	bellard	}
808	79aceca5	bellard
809	9a64fbe4	bellard	#define GEN_FLOAT_BS(name, op2) \
810	9a64fbe4	bellard	GEN_HANDLER(f##name, 0x3F, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
811	9a64fbe4	bellard	{ \
812	9a64fbe4	bellard	gen_op_reset_scrfx(); \
813	9a64fbe4	bellard	gen_op_load_fpr_FT0(rB(ctx->opcode)); \
814	9a64fbe4	bellard	gen_op_f##name(); \
815	9a64fbe4	bellard	gen_op_store_FT0_fpr(rD(ctx->opcode)); \
816	9a64fbe4	bellard	if (Rc(ctx->opcode)) \
817	9a64fbe4	bellard	gen_op_set_Rc1(); \
818	79aceca5	bellard	}
819	79aceca5	bellard
820	9a64fbe4	bellard	/* fadd - fadds */
821	9a64fbe4	bellard	GEN_FLOAT_AB(add, 0x15, 0x000007C0);
822	79aceca5	bellard	/* fdiv */
823	9a64fbe4	bellard	GEN_FLOAT_AB(div, 0x12, 0x000007C0);
824	79aceca5	bellard	/* fmul */
825	9a64fbe4	bellard	GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
826	79aceca5	bellard
827	79aceca5	bellard	/* fres */
828	9a64fbe4	bellard	GEN_FLOAT_BS(res, 0x18);
829	79aceca5	bellard
830	79aceca5	bellard	/* frsqrte */
831	9a64fbe4	bellard	GEN_FLOAT_BS(rsqrte, 0x1A);
832	79aceca5	bellard
833	79aceca5	bellard	/* fsel */
834	9a64fbe4	bellard	_GEN_FLOAT_ACB(sel, 0x3F, 0x17);
835	79aceca5	bellard	/* fsub */
836	9a64fbe4	bellard	GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
837	79aceca5	bellard	/* Optional: */
838	79aceca5	bellard	/* fsqrt */
839	9a64fbe4	bellard	GEN_FLOAT_BS(sqrt, 0x16);
840	79aceca5	bellard
841	9a64fbe4	bellard	GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
842	79aceca5	bellard	{
843	9a64fbe4	bellard	gen_op_reset_scrfx();
844	9a64fbe4	bellard	gen_op_load_fpr_FT0(rB(ctx->opcode));
845	9a64fbe4	bellard	gen_op_fsqrts();
846	9a64fbe4	bellard	gen_op_store_FT0_fpr(rD(ctx->opcode));
847	9a64fbe4	bellard	if (Rc(ctx->opcode))
848	9a64fbe4	bellard	gen_op_set_Rc1();
849	79aceca5	bellard	}
850	79aceca5	bellard
851	79aceca5	bellard	/* Floating-Point multiply-and-add */
852	79aceca5	bellard	/* fmadd */
853	9a64fbe4	bellard	GEN_FLOAT_ACB(madd, 0x1D);
854	79aceca5	bellard	/* fmsub */
855	9a64fbe4	bellard	GEN_FLOAT_ACB(msub, 0x1C);
856	79aceca5	bellard	/* fnmadd */
857	9a64fbe4	bellard	GEN_FLOAT_ACB(nmadd, 0x1F);
858	79aceca5	bellard	/* fnmsub */
859	9a64fbe4	bellard	GEN_FLOAT_ACB(nmsub, 0x1E);
860	79aceca5	bellard
861	79aceca5	bellard	/* Floating-Point round & convert */
862	79aceca5	bellard	/* fctiw */
863	9a64fbe4	bellard	GEN_FLOAT_B(ctiw, 0x0E, 0x00);
864	79aceca5	bellard	/* fctiwz */
865	9a64fbe4	bellard	GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
866	79aceca5	bellard	/* frsp */
867	9a64fbe4	bellard	GEN_FLOAT_B(rsp, 0x0C, 0x00);
868	79aceca5	bellard
869	79aceca5	bellard	/* Floating-Point compare */
870	79aceca5	bellard	/* fcmpo */
871	79aceca5	bellard	GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
872	79aceca5	bellard	{
873	9a64fbe4	bellard	gen_op_reset_scrfx();
874	9a64fbe4	bellard	gen_op_load_fpr_FT0(rA(ctx->opcode));
875	9a64fbe4	bellard	gen_op_load_fpr_FT1(rB(ctx->opcode));
876	9a64fbe4	bellard	gen_op_fcmpo();
877	9a64fbe4	bellard	gen_op_store_T0_crf(crfD(ctx->opcode));
878	79aceca5	bellard	}
879	79aceca5	bellard
880	79aceca5	bellard	/* fcmpu */
881	79aceca5	bellard	GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
882	79aceca5	bellard	{
883	9a64fbe4	bellard	gen_op_reset_scrfx();
884	9a64fbe4	bellard	gen_op_load_fpr_FT0(rA(ctx->opcode));
885	9a64fbe4	bellard	gen_op_load_fpr_FT1(rB(ctx->opcode));
886	9a64fbe4	bellard	gen_op_fcmpu();
887	9a64fbe4	bellard	gen_op_store_T0_crf(crfD(ctx->opcode));
888	79aceca5	bellard	}
889	79aceca5	bellard
890	9a64fbe4	bellard	/* Floating-point move */
891	9a64fbe4	bellard	/* fabs */
892	9a64fbe4	bellard	GEN_FLOAT_B(abs, 0x08, 0x08);
893	9a64fbe4	bellard
894	9a64fbe4	bellard	/* fmr - fmr. */
895	9a64fbe4	bellard	GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
896	9a64fbe4	bellard	{
897	9a64fbe4	bellard	gen_op_reset_scrfx();
898	9a64fbe4	bellard	gen_op_load_fpr_FT0(rB(ctx->opcode));
899	9a64fbe4	bellard	gen_op_store_FT0_fpr(rD(ctx->opcode));
900	9a64fbe4	bellard	if (Rc(ctx->opcode))
901	9a64fbe4	bellard	gen_op_set_Rc1();
902	9a64fbe4	bellard	}
903	9a64fbe4	bellard
904	9a64fbe4	bellard	/* fnabs */
905	9a64fbe4	bellard	GEN_FLOAT_B(nabs, 0x08, 0x04);
906	9a64fbe4	bellard	/* fneg */
907	9a64fbe4	bellard	GEN_FLOAT_B(neg, 0x08, 0x01);
908	9a64fbe4	bellard
909	79aceca5	bellard	/* Floating-Point status & ctrl register */
910	79aceca5	bellard	/* mcrfs */
911	79aceca5	bellard	GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
912	79aceca5	bellard	{
913	fb0eaffc	bellard	gen_op_load_fpscr_T0(crfS(ctx->opcode));
914	fb0eaffc	bellard	gen_op_store_T0_crf(crfD(ctx->opcode));
915	fb0eaffc	bellard	gen_op_clear_fpscr(crfS(ctx->opcode));
916	79aceca5	bellard	}
917	79aceca5	bellard
918	79aceca5	bellard	/* mffs */
919	79aceca5	bellard	GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
920	79aceca5	bellard	{
921	28b6751f	bellard	gen_op_load_fpscr();
922	fb0eaffc	bellard	gen_op_store_FT0_fpr(rD(ctx->opcode));
923	fb0eaffc	bellard	if (Rc(ctx->opcode))
924	fb0eaffc	bellard	gen_op_set_Rc1();
925	79aceca5	bellard	}
926	79aceca5	bellard
927	79aceca5	bellard	/* mtfsb0 */
928	79aceca5	bellard	GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
929	79aceca5	bellard	{
930	fb0eaffc	bellard	uint8_t crb;
931	fb0eaffc	bellard
932	fb0eaffc	bellard	crb = crbD(ctx->opcode) >> 2;
933	fb0eaffc	bellard	gen_op_load_fpscr_T0(crb);
934	fb0eaffc	bellard	gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
935	fb0eaffc	bellard	gen_op_store_T0_fpscr(crb);
936	fb0eaffc	bellard	if (Rc(ctx->opcode))
937	fb0eaffc	bellard	gen_op_set_Rc1();
938	79aceca5	bellard	}
939	79aceca5	bellard
940	79aceca5	bellard	/* mtfsb1 */
941	79aceca5	bellard	GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
942	79aceca5	bellard	{
943	fb0eaffc	bellard	uint8_t crb;
944	fb0eaffc	bellard
945	fb0eaffc	bellard	crb = crbD(ctx->opcode) >> 2;
946	fb0eaffc	bellard	gen_op_load_fpscr_T0(crb);
947	fb0eaffc	bellard	gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
948	fb0eaffc	bellard	gen_op_store_T0_fpscr(crb);
949	fb0eaffc	bellard	if (Rc(ctx->opcode))
950	fb0eaffc	bellard	gen_op_set_Rc1();
951	79aceca5	bellard	}
952	79aceca5	bellard
953	79aceca5	bellard	/* mtfsf */
954	79aceca5	bellard	GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
955	79aceca5	bellard	{
956	fb0eaffc	bellard	gen_op_load_fpr_FT0(rB(ctx->opcode));
957	28b6751f	bellard	gen_op_store_fpscr(FM(ctx->opcode));
958	fb0eaffc	bellard	if (Rc(ctx->opcode))
959	fb0eaffc	bellard	gen_op_set_Rc1();
960	79aceca5	bellard	}
961	79aceca5	bellard
962	79aceca5	bellard	/* mtfsfi */
963	79aceca5	bellard	GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
964	79aceca5	bellard	{
965	fb0eaffc	bellard	gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
966	fb0eaffc	bellard	if (Rc(ctx->opcode))
967	fb0eaffc	bellard	gen_op_set_Rc1();
968	79aceca5	bellard	}
969	79aceca5	bellard
970	79aceca5	bellard	/* Integer load */
971	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
972	9a64fbe4	bellard	#define op_ldst(name) gen_op_##name##_raw()
973	9a64fbe4	bellard	#define OP_LD_TABLE(width)
974	9a64fbe4	bellard	#define OP_ST_TABLE(width)
975	9a64fbe4	bellard	#else
976	9a64fbe4	bellard	#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
977	9a64fbe4	bellard	#define OP_LD_TABLE(width) \
978	9a64fbe4	bellard	static GenOpFunc *gen_op_l##width[] = { \
979	9a64fbe4	bellard	&gen_op_l##width##_user, \
980	9a64fbe4	bellard	&gen_op_l##width##_kernel, \
981	9a64fbe4	bellard	}
982	9a64fbe4	bellard	#define OP_ST_TABLE(width) \
983	9a64fbe4	bellard	static GenOpFunc *gen_op_st##width[] = { \
984	9a64fbe4	bellard	&gen_op_st##width##_user, \
985	9a64fbe4	bellard	&gen_op_st##width##_kernel, \
986	9a64fbe4	bellard	}
987	9a64fbe4	bellard	#endif
988	9a64fbe4	bellard
989	9a64fbe4	bellard	#define GEN_LD(width, opc) \
990	79aceca5	bellard	GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
991	79aceca5	bellard	{ \
992	79aceca5	bellard	uint32_t simm = SIMM(ctx->opcode); \
993	79aceca5	bellard	if (rA(ctx->opcode) == 0) { \
994	9a64fbe4	bellard	gen_op_set_T0(simm); \
995	79aceca5	bellard	} else { \
996	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
997	9a64fbe4	bellard	if (simm != 0) \
998	9a64fbe4	bellard	gen_op_addi(simm); \
999	79aceca5	bellard	} \
1000	9a64fbe4	bellard	op_ldst(l##width); \
1001	79aceca5	bellard	gen_op_store_T1_gpr(rD(ctx->opcode)); \
1002	79aceca5	bellard	}
1003	79aceca5	bellard
1004	9a64fbe4	bellard	#define GEN_LDU(width, opc) \
1005	79aceca5	bellard	GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1006	79aceca5	bellard	{ \
1007	9a64fbe4	bellard	uint32_t simm = SIMM(ctx->opcode); \
1008	79aceca5	bellard	if (rA(ctx->opcode) == 0 \|\| \
1009	9a64fbe4	bellard	rA(ctx->opcode) == rD(ctx->opcode)) { \
1010	9fddaa0c	bellard	RET_INVAL(ctx); \
1011	9fddaa0c	bellard	return; \
1012	9a64fbe4	bellard	} \
1013	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
1014	9a64fbe4	bellard	if (simm != 0) \
1015	9a64fbe4	bellard	gen_op_addi(simm); \
1016	9a64fbe4	bellard	op_ldst(l##width); \
1017	79aceca5	bellard	gen_op_store_T1_gpr(rD(ctx->opcode)); \
1018	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode)); \
1019	79aceca5	bellard	}
1020	79aceca5	bellard
1021	9a64fbe4	bellard	#define GEN_LDUX(width, opc) \
1022	79aceca5	bellard	GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1023	79aceca5	bellard	{ \
1024	79aceca5	bellard	if (rA(ctx->opcode) == 0 \|\| \
1025	9a64fbe4	bellard	rA(ctx->opcode) == rD(ctx->opcode)) { \
1026	9fddaa0c	bellard	RET_INVAL(ctx); \
1027	9fddaa0c	bellard	return; \
1028	9a64fbe4	bellard	} \
1029	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
1030	79aceca5	bellard	gen_op_load_gpr_T1(rB(ctx->opcode)); \
1031	9a64fbe4	bellard	gen_op_add(); \
1032	9a64fbe4	bellard	op_ldst(l##width); \
1033	79aceca5	bellard	gen_op_store_T1_gpr(rD(ctx->opcode)); \
1034	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode)); \
1035	79aceca5	bellard	}
1036	79aceca5	bellard
1037	9a64fbe4	bellard	#define GEN_LDX(width, opc2, opc3) \
1038	79aceca5	bellard	GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1039	79aceca5	bellard	{ \
1040	79aceca5	bellard	if (rA(ctx->opcode) == 0) { \
1041	79aceca5	bellard	gen_op_load_gpr_T0(rB(ctx->opcode)); \
1042	79aceca5	bellard	} else { \
1043	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
1044	79aceca5	bellard	gen_op_load_gpr_T1(rB(ctx->opcode)); \
1045	9a64fbe4	bellard	gen_op_add(); \
1046	79aceca5	bellard	} \
1047	9a64fbe4	bellard	op_ldst(l##width); \
1048	79aceca5	bellard	gen_op_store_T1_gpr(rD(ctx->opcode)); \
1049	79aceca5	bellard	}
1050	79aceca5	bellard
1051	9a64fbe4	bellard	#define GEN_LDS(width, op) \
1052	9a64fbe4	bellard	OP_LD_TABLE(width); \
1053	9a64fbe4	bellard	GEN_LD(width, op \| 0x20); \
1054	9a64fbe4	bellard	GEN_LDU(width, op \| 0x21); \
1055	9a64fbe4	bellard	GEN_LDUX(width, op \| 0x01); \
1056	9a64fbe4	bellard	GEN_LDX(width, 0x17, op \| 0x00)
1057	79aceca5	bellard
1058	79aceca5	bellard	/* lbz lbzu lbzux lbzx */
1059	9a64fbe4	bellard	GEN_LDS(bz, 0x02);
1060	79aceca5	bellard	/* lha lhau lhaux lhax */
1061	9a64fbe4	bellard	GEN_LDS(ha, 0x0A);
1062	79aceca5	bellard	/* lhz lhzu lhzux lhzx */
1063	9a64fbe4	bellard	GEN_LDS(hz, 0x08);
1064	79aceca5	bellard	/* lwz lwzu lwzux lwzx */
1065	9a64fbe4	bellard	GEN_LDS(wz, 0x00);
1066	79aceca5	bellard
1067	79aceca5	bellard	/* Integer store */
1068	9a64fbe4	bellard	#define GEN_ST(width, opc) \
1069	79aceca5	bellard	GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1070	79aceca5	bellard	{ \
1071	79aceca5	bellard	uint32_t simm = SIMM(ctx->opcode); \
1072	79aceca5	bellard	if (rA(ctx->opcode) == 0) { \
1073	9a64fbe4	bellard	gen_op_set_T0(simm); \
1074	79aceca5	bellard	} else { \
1075	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
1076	9a64fbe4	bellard	if (simm != 0) \
1077	9a64fbe4	bellard	gen_op_addi(simm); \
1078	79aceca5	bellard	} \
1079	9a64fbe4	bellard	gen_op_load_gpr_T1(rS(ctx->opcode)); \
1080	9a64fbe4	bellard	op_ldst(st##width); \
1081	79aceca5	bellard	}
1082	79aceca5	bellard
1083	9a64fbe4	bellard	#define GEN_STU(width, opc) \
1084	79aceca5	bellard	GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1085	79aceca5	bellard	{ \
1086	9a64fbe4	bellard	uint32_t simm = SIMM(ctx->opcode); \
1087	9a64fbe4	bellard	if (rA(ctx->opcode) == 0) { \
1088	9fddaa0c	bellard	RET_INVAL(ctx); \
1089	9fddaa0c	bellard	return; \
1090	9a64fbe4	bellard	} \
1091	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
1092	9a64fbe4	bellard	if (simm != 0) \
1093	9a64fbe4	bellard	gen_op_addi(simm); \
1094	79aceca5	bellard	gen_op_load_gpr_T1(rS(ctx->opcode)); \
1095	9a64fbe4	bellard	op_ldst(st##width); \
1096	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode)); \
1097	79aceca5	bellard	}
1098	79aceca5	bellard
1099	9a64fbe4	bellard	#define GEN_STUX(width, opc) \
1100	79aceca5	bellard	GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1101	79aceca5	bellard	{ \
1102	9a64fbe4	bellard	if (rA(ctx->opcode) == 0) { \
1103	9fddaa0c	bellard	RET_INVAL(ctx); \
1104	9fddaa0c	bellard	return; \
1105	9a64fbe4	bellard	} \
1106	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
1107	79aceca5	bellard	gen_op_load_gpr_T1(rB(ctx->opcode)); \
1108	9a64fbe4	bellard	gen_op_add(); \
1109	9a64fbe4	bellard	gen_op_load_gpr_T1(rS(ctx->opcode)); \
1110	9a64fbe4	bellard	op_ldst(st##width); \
1111	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode)); \
1112	79aceca5	bellard	}
1113	79aceca5	bellard
1114	9a64fbe4	bellard	#define GEN_STX(width, opc2, opc3) \
1115	79aceca5	bellard	GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1116	79aceca5	bellard	{ \
1117	79aceca5	bellard	if (rA(ctx->opcode) == 0) { \
1118	79aceca5	bellard	gen_op_load_gpr_T0(rB(ctx->opcode)); \
1119	79aceca5	bellard	} else { \
1120	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
1121	79aceca5	bellard	gen_op_load_gpr_T1(rB(ctx->opcode)); \
1122	9a64fbe4	bellard	gen_op_add(); \
1123	79aceca5	bellard	} \
1124	9a64fbe4	bellard	gen_op_load_gpr_T1(rS(ctx->opcode)); \
1125	9a64fbe4	bellard	op_ldst(st##width); \
1126	79aceca5	bellard	}
1127	79aceca5	bellard
1128	9a64fbe4	bellard	#define GEN_STS(width, op) \
1129	9a64fbe4	bellard	OP_ST_TABLE(width); \
1130	9a64fbe4	bellard	GEN_ST(width, op \| 0x20); \
1131	9a64fbe4	bellard	GEN_STU(width, op \| 0x21); \
1132	9a64fbe4	bellard	GEN_STUX(width, op \| 0x01); \
1133	9a64fbe4	bellard	GEN_STX(width, 0x17, op \| 0x00)
1134	79aceca5	bellard
1135	79aceca5	bellard	/* stb stbu stbux stbx */
1136	9a64fbe4	bellard	GEN_STS(b, 0x06);
1137	79aceca5	bellard	/* sth sthu sthux sthx */
1138	9a64fbe4	bellard	GEN_STS(h, 0x0C);
1139	79aceca5	bellard	/* stw stwu stwux stwx */
1140	9a64fbe4	bellard	GEN_STS(w, 0x04);
1141	79aceca5	bellard
1142	79aceca5	bellard	/* Integer load and store with byte reverse */
1143	79aceca5	bellard	/* lhbrx */
1144	9a64fbe4	bellard	OP_LD_TABLE(hbr);
1145	9a64fbe4	bellard	GEN_LDX(hbr, 0x16, 0x18);
1146	79aceca5	bellard	/* lwbrx */
1147	9a64fbe4	bellard	OP_LD_TABLE(wbr);
1148	9a64fbe4	bellard	GEN_LDX(wbr, 0x16, 0x10);
1149	79aceca5	bellard	/* sthbrx */
1150	9a64fbe4	bellard	OP_ST_TABLE(hbr);
1151	9a64fbe4	bellard	GEN_STX(hbr, 0x16, 0x1C);
1152	79aceca5	bellard	/* stwbrx */
1153	9a64fbe4	bellard	OP_ST_TABLE(wbr);
1154	9a64fbe4	bellard	GEN_STX(wbr, 0x16, 0x14);
1155	79aceca5	bellard
1156	79aceca5	bellard	/* Integer load and store multiple */
1157	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
1158	9a64fbe4	bellard	#define op_ldstm(name, reg) gen_op_##name##_raw(reg)
1159	9a64fbe4	bellard	#else
1160	9a64fbe4	bellard	#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1161	9a64fbe4	bellard	static GenOpFunc1 *gen_op_lmw[] = {
1162	9a64fbe4	bellard	&gen_op_lmw_user,
1163	9a64fbe4	bellard	&gen_op_lmw_kernel,
1164	9a64fbe4	bellard	};
1165	9a64fbe4	bellard	static GenOpFunc1 *gen_op_stmw[] = {
1166	9a64fbe4	bellard	&gen_op_stmw_user,
1167	9a64fbe4	bellard	&gen_op_stmw_kernel,
1168	9a64fbe4	bellard	};
1169	9a64fbe4	bellard	#endif
1170	9a64fbe4	bellard
1171	79aceca5	bellard	/* lmw */
1172	79aceca5	bellard	GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1173	79aceca5	bellard	{
1174	9a64fbe4	bellard	int simm = SIMM(ctx->opcode);
1175	9a64fbe4	bellard
1176	79aceca5	bellard	if (rA(ctx->opcode) == 0) {
1177	9a64fbe4	bellard	gen_op_set_T0(simm);
1178	79aceca5	bellard	} else {
1179	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
1180	9a64fbe4	bellard	if (simm != 0)
1181	9a64fbe4	bellard	gen_op_addi(simm);
1182	79aceca5	bellard	}
1183	9a64fbe4	bellard	op_ldstm(lmw, rD(ctx->opcode));
1184	79aceca5	bellard	}
1185	79aceca5	bellard
1186	79aceca5	bellard	/* stmw */
1187	79aceca5	bellard	GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1188	79aceca5	bellard	{
1189	9a64fbe4	bellard	int simm = SIMM(ctx->opcode);
1190	9a64fbe4	bellard
1191	79aceca5	bellard	if (rA(ctx->opcode) == 0) {
1192	9a64fbe4	bellard	gen_op_set_T0(simm);
1193	79aceca5	bellard	} else {
1194	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
1195	9a64fbe4	bellard	if (simm != 0)
1196	9a64fbe4	bellard	gen_op_addi(simm);
1197	79aceca5	bellard	}
1198	9a64fbe4	bellard	op_ldstm(stmw, rS(ctx->opcode));
1199	79aceca5	bellard	}
1200	79aceca5	bellard
1201	79aceca5	bellard	/* Integer load and store strings */
1202	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
1203	9a64fbe4	bellard	#define op_ldsts(name, start) gen_op_##name##_raw(start)
1204	9a64fbe4	bellard	#define op_ldstsx(name, rd, ra, rb) gen_op_##name##_raw(rd, ra, rb)
1205	9a64fbe4	bellard	#else
1206	9a64fbe4	bellard	#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1207	9a64fbe4	bellard	#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1208	9a64fbe4	bellard	static GenOpFunc1 *gen_op_lswi[] = {
1209	9a64fbe4	bellard	&gen_op_lswi_user,
1210	9a64fbe4	bellard	&gen_op_lswi_kernel,
1211	9a64fbe4	bellard	};
1212	9a64fbe4	bellard	static GenOpFunc3 *gen_op_lswx[] = {
1213	9a64fbe4	bellard	&gen_op_lswx_user,
1214	9a64fbe4	bellard	&gen_op_lswx_kernel,
1215	9a64fbe4	bellard	};
1216	9a64fbe4	bellard	static GenOpFunc1 *gen_op_stsw[] = {
1217	9a64fbe4	bellard	&gen_op_stsw_user,
1218	9a64fbe4	bellard	&gen_op_stsw_kernel,
1219	9a64fbe4	bellard	};
1220	9a64fbe4	bellard	#endif
1221	9a64fbe4	bellard
1222	79aceca5	bellard	/* lswi */
1223	9a64fbe4	bellard	/* PPC32 specification says we must generate an exception if
1224	9a64fbe4	bellard	* rA is in the range of registers to be loaded.
1225	9a64fbe4	bellard	* In an other hand, IBM says this is valid, but rA won't be loaded.
1226	9a64fbe4	bellard	* For now, I'll follow the spec...
1227	9a64fbe4	bellard	*/
1228	79aceca5	bellard	GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1229	79aceca5	bellard	{
1230	79aceca5	bellard	int nb = NB(ctx->opcode);
1231	79aceca5	bellard	int start = rD(ctx->opcode);
1232	9a64fbe4	bellard	int ra = rA(ctx->opcode);
1233	79aceca5	bellard	int nr;
1234	79aceca5	bellard
1235	79aceca5	bellard	if (nb == 0)
1236	79aceca5	bellard	nb = 32;
1237	79aceca5	bellard	nr = nb / 4;
1238	297d8e62	bellard	if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) \|\|
1239	297d8e62	bellard	((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
1240	9fddaa0c	bellard	RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL \| EXCP_INVAL_LSWX);
1241	9fddaa0c	bellard	return;
1242	297d8e62	bellard	}
1243	9a64fbe4	bellard	if (ra == 0) {
1244	79aceca5	bellard	gen_op_set_T0(0);
1245	79aceca5	bellard	} else {
1246	9a64fbe4	bellard	gen_op_load_gpr_T0(ra);
1247	79aceca5	bellard	}
1248	9a64fbe4	bellard	gen_op_set_T1(nb);
1249	9a64fbe4	bellard	op_ldsts(lswi, start);
1250	79aceca5	bellard	}
1251	79aceca5	bellard
1252	79aceca5	bellard	/* lswx */
1253	79aceca5	bellard	GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1254	79aceca5	bellard	{
1255	9a64fbe4	bellard	int ra = rA(ctx->opcode);
1256	9a64fbe4	bellard	int rb = rB(ctx->opcode);
1257	9a64fbe4	bellard
1258	9a64fbe4	bellard	if (ra == 0) {
1259	9a64fbe4	bellard	gen_op_load_gpr_T0(rb);
1260	9a64fbe4	bellard	ra = rb;
1261	79aceca5	bellard	} else {
1262	9a64fbe4	bellard	gen_op_load_gpr_T0(ra);
1263	9a64fbe4	bellard	gen_op_load_gpr_T1(rb);
1264	9a64fbe4	bellard	gen_op_add();
1265	79aceca5	bellard	}
1266	9a64fbe4	bellard	gen_op_load_xer_bc();
1267	9a64fbe4	bellard	op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
1268	79aceca5	bellard	}
1269	79aceca5	bellard
1270	79aceca5	bellard	/* stswi */
1271	79aceca5	bellard	GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1272	79aceca5	bellard	{
1273	4b3686fa	bellard	int nb = NB(ctx->opcode);
1274	4b3686fa	bellard
1275	79aceca5	bellard	if (rA(ctx->opcode) == 0) {
1276	79aceca5	bellard	gen_op_set_T0(0);
1277	79aceca5	bellard	} else {
1278	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
1279	79aceca5	bellard	}
1280	4b3686fa	bellard	if (nb == 0)
1281	4b3686fa	bellard	nb = 32;
1282	4b3686fa	bellard	gen_op_set_T1(nb);
1283	9a64fbe4	bellard	op_ldsts(stsw, rS(ctx->opcode));
1284	79aceca5	bellard	}
1285	79aceca5	bellard
1286	79aceca5	bellard	/* stswx */
1287	79aceca5	bellard	GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1288	79aceca5	bellard	{
1289	9a64fbe4	bellard	int ra = rA(ctx->opcode);
1290	9a64fbe4	bellard
1291	9a64fbe4	bellard	if (ra == 0) {
1292	9a64fbe4	bellard	gen_op_load_gpr_T0(rB(ctx->opcode));
1293	9a64fbe4	bellard	ra = rB(ctx->opcode);
1294	79aceca5	bellard	} else {
1295	9a64fbe4	bellard	gen_op_load_gpr_T0(ra);
1296	9a64fbe4	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
1297	9a64fbe4	bellard	gen_op_add();
1298	79aceca5	bellard	}
1299	9a64fbe4	bellard	gen_op_load_xer_bc();
1300	9a64fbe4	bellard	op_ldsts(stsw, rS(ctx->opcode));
1301	79aceca5	bellard	}
1302	79aceca5	bellard
1303	79aceca5	bellard	/* Memory synchronisation */
1304	79aceca5	bellard	/* eieio */
1305	79aceca5	bellard	GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1306	79aceca5	bellard	{
1307	79aceca5	bellard	}
1308	79aceca5	bellard
1309	79aceca5	bellard	/* isync */
1310	79aceca5	bellard	GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1311	79aceca5	bellard	{
1312	79aceca5	bellard	}
1313	79aceca5	bellard
1314	79aceca5	bellard	/* lwarx */
1315	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
1316	985a19d6	bellard	#define op_lwarx() gen_op_lwarx_raw()
1317	9a64fbe4	bellard	#define op_stwcx() gen_op_stwcx_raw()
1318	9a64fbe4	bellard	#else
1319	985a19d6	bellard	#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1320	985a19d6	bellard	static GenOpFunc *gen_op_lwarx[] = {
1321	985a19d6	bellard	&gen_op_lwarx_user,
1322	985a19d6	bellard	&gen_op_lwarx_kernel,
1323	985a19d6	bellard	};
1324	9a64fbe4	bellard	#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1325	9a64fbe4	bellard	static GenOpFunc *gen_op_stwcx[] = {
1326	9a64fbe4	bellard	&gen_op_stwcx_user,
1327	9a64fbe4	bellard	&gen_op_stwcx_kernel,
1328	9a64fbe4	bellard	};
1329	9a64fbe4	bellard	#endif
1330	9a64fbe4	bellard
1331	9a64fbe4	bellard	GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
1332	79aceca5	bellard	{
1333	79aceca5	bellard	if (rA(ctx->opcode) == 0) {
1334	79aceca5	bellard	gen_op_load_gpr_T0(rB(ctx->opcode));
1335	79aceca5	bellard	} else {
1336	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
1337	79aceca5	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
1338	9a64fbe4	bellard	gen_op_add();
1339	79aceca5	bellard	}
1340	985a19d6	bellard	op_lwarx();
1341	79aceca5	bellard	gen_op_store_T1_gpr(rD(ctx->opcode));
1342	79aceca5	bellard	}
1343	79aceca5	bellard
1344	79aceca5	bellard	/* stwcx. */
1345	9a64fbe4	bellard	GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
1346	79aceca5	bellard	{
1347	79aceca5	bellard	if (rA(ctx->opcode) == 0) {
1348	79aceca5	bellard	gen_op_load_gpr_T0(rB(ctx->opcode));
1349	79aceca5	bellard	} else {
1350	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
1351	79aceca5	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
1352	9a64fbe4	bellard	gen_op_add();
1353	79aceca5	bellard	}
1354	9a64fbe4	bellard	gen_op_load_gpr_T1(rS(ctx->opcode));
1355	9a64fbe4	bellard	op_stwcx();
1356	79aceca5	bellard	}
1357	79aceca5	bellard
1358	79aceca5	bellard	/* sync */
1359	79aceca5	bellard	GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1360	79aceca5	bellard	{
1361	79aceca5	bellard	}
1362	79aceca5	bellard
1363	79aceca5	bellard	/* Floating-point load */
1364	9a64fbe4	bellard	#define GEN_LDF(width, opc) \
1365	9a64fbe4	bellard	GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1366	79aceca5	bellard	{ \
1367	79aceca5	bellard	uint32_t simm = SIMM(ctx->opcode); \
1368	79aceca5	bellard	if (rA(ctx->opcode) == 0) { \
1369	9a64fbe4	bellard	gen_op_set_T0(simm); \
1370	79aceca5	bellard	} else { \
1371	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
1372	9a64fbe4	bellard	if (simm != 0) \
1373	9a64fbe4	bellard	gen_op_addi(simm); \
1374	79aceca5	bellard	} \
1375	9a64fbe4	bellard	op_ldst(l##width); \
1376	9a64fbe4	bellard	gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1377	79aceca5	bellard	}
1378	79aceca5	bellard
1379	9a64fbe4	bellard	#define GEN_LDUF(width, opc) \
1380	9a64fbe4	bellard	GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1381	79aceca5	bellard	{ \
1382	9a64fbe4	bellard	uint32_t simm = SIMM(ctx->opcode); \
1383	79aceca5	bellard	if (rA(ctx->opcode) == 0 \|\| \
1384	9a64fbe4	bellard	rA(ctx->opcode) == rD(ctx->opcode)) { \
1385	9fddaa0c	bellard	RET_INVAL(ctx); \
1386	9fddaa0c	bellard	return; \
1387	9a64fbe4	bellard	} \
1388	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
1389	9a64fbe4	bellard	if (simm != 0) \
1390	9a64fbe4	bellard	gen_op_addi(simm); \
1391	9a64fbe4	bellard	op_ldst(l##width); \
1392	9a64fbe4	bellard	gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1393	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode)); \
1394	79aceca5	bellard	}
1395	79aceca5	bellard
1396	9a64fbe4	bellard	#define GEN_LDUXF(width, opc) \
1397	9a64fbe4	bellard	GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1398	79aceca5	bellard	{ \
1399	79aceca5	bellard	if (rA(ctx->opcode) == 0 \|\| \
1400	9a64fbe4	bellard	rA(ctx->opcode) == rD(ctx->opcode)) { \
1401	9fddaa0c	bellard	RET_INVAL(ctx); \
1402	9fddaa0c	bellard	return; \
1403	9a64fbe4	bellard	} \
1404	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
1405	79aceca5	bellard	gen_op_load_gpr_T1(rB(ctx->opcode)); \
1406	9a64fbe4	bellard	gen_op_add(); \
1407	9a64fbe4	bellard	op_ldst(l##width); \
1408	9a64fbe4	bellard	gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1409	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode)); \
1410	79aceca5	bellard	}
1411	79aceca5	bellard
1412	9a64fbe4	bellard	#define GEN_LDXF(width, opc2, opc3) \
1413	9a64fbe4	bellard	GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1414	79aceca5	bellard	{ \
1415	79aceca5	bellard	if (rA(ctx->opcode) == 0) { \
1416	79aceca5	bellard	gen_op_load_gpr_T0(rB(ctx->opcode)); \
1417	79aceca5	bellard	} else { \
1418	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
1419	79aceca5	bellard	gen_op_load_gpr_T1(rB(ctx->opcode)); \
1420	9a64fbe4	bellard	gen_op_add(); \
1421	79aceca5	bellard	} \
1422	9a64fbe4	bellard	op_ldst(l##width); \
1423	9a64fbe4	bellard	gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1424	79aceca5	bellard	}
1425	79aceca5	bellard
1426	9a64fbe4	bellard	#define GEN_LDFS(width, op) \
1427	9a64fbe4	bellard	OP_LD_TABLE(width); \
1428	9a64fbe4	bellard	GEN_LDF(width, op \| 0x20); \
1429	9a64fbe4	bellard	GEN_LDUF(width, op \| 0x21); \
1430	9a64fbe4	bellard	GEN_LDUXF(width, op \| 0x01); \
1431	9a64fbe4	bellard	GEN_LDXF(width, 0x17, op \| 0x00)
1432	79aceca5	bellard
1433	79aceca5	bellard	/* lfd lfdu lfdux lfdx */
1434	9a64fbe4	bellard	GEN_LDFS(fd, 0x12);
1435	79aceca5	bellard	/* lfs lfsu lfsux lfsx */
1436	9a64fbe4	bellard	GEN_LDFS(fs, 0x10);
1437	79aceca5	bellard
1438	79aceca5	bellard	/* Floating-point store */
1439	79aceca5	bellard	#define GEN_STF(width, opc) \
1440	9a64fbe4	bellard	GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1441	79aceca5	bellard	{ \
1442	79aceca5	bellard	uint32_t simm = SIMM(ctx->opcode); \
1443	79aceca5	bellard	if (rA(ctx->opcode) == 0) { \
1444	9a64fbe4	bellard	gen_op_set_T0(simm); \
1445	79aceca5	bellard	} else { \
1446	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
1447	9a64fbe4	bellard	if (simm != 0) \
1448	9a64fbe4	bellard	gen_op_addi(simm); \
1449	79aceca5	bellard	} \
1450	9a64fbe4	bellard	gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1451	9a64fbe4	bellard	op_ldst(st##width); \
1452	79aceca5	bellard	}
1453	79aceca5	bellard
1454	9a64fbe4	bellard	#define GEN_STUF(width, opc) \
1455	9a64fbe4	bellard	GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1456	79aceca5	bellard	{ \
1457	9a64fbe4	bellard	uint32_t simm = SIMM(ctx->opcode); \
1458	9a64fbe4	bellard	if (rA(ctx->opcode) == 0) { \
1459	9fddaa0c	bellard	RET_INVAL(ctx); \
1460	9fddaa0c	bellard	return; \
1461	9a64fbe4	bellard	} \
1462	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
1463	9a64fbe4	bellard	if (simm != 0) \
1464	9a64fbe4	bellard	gen_op_addi(simm); \
1465	9a64fbe4	bellard	gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1466	9a64fbe4	bellard	op_ldst(st##width); \
1467	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode)); \
1468	79aceca5	bellard	}
1469	79aceca5	bellard
1470	9a64fbe4	bellard	#define GEN_STUXF(width, opc) \
1471	9a64fbe4	bellard	GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1472	79aceca5	bellard	{ \
1473	9a64fbe4	bellard	if (rA(ctx->opcode) == 0) { \
1474	9fddaa0c	bellard	RET_INVAL(ctx); \
1475	9fddaa0c	bellard	return; \
1476	9a64fbe4	bellard	} \
1477	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
1478	79aceca5	bellard	gen_op_load_gpr_T1(rB(ctx->opcode)); \
1479	9a64fbe4	bellard	gen_op_add(); \
1480	9a64fbe4	bellard	gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1481	9a64fbe4	bellard	op_ldst(st##width); \
1482	79aceca5	bellard	gen_op_store_T0_gpr(rA(ctx->opcode)); \
1483	79aceca5	bellard	}
1484	79aceca5	bellard
1485	9a64fbe4	bellard	#define GEN_STXF(width, opc2, opc3) \
1486	9a64fbe4	bellard	GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1487	79aceca5	bellard	{ \
1488	79aceca5	bellard	if (rA(ctx->opcode) == 0) { \
1489	79aceca5	bellard	gen_op_load_gpr_T0(rB(ctx->opcode)); \
1490	79aceca5	bellard	} else { \
1491	79aceca5	bellard	gen_op_load_gpr_T0(rA(ctx->opcode)); \
1492	79aceca5	bellard	gen_op_load_gpr_T1(rB(ctx->opcode)); \
1493	9a64fbe4	bellard	gen_op_add(); \
1494	79aceca5	bellard	} \
1495	9a64fbe4	bellard	gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1496	9a64fbe4	bellard	op_ldst(st##width); \
1497	79aceca5	bellard	}
1498	79aceca5	bellard
1499	9a64fbe4	bellard	#define GEN_STFS(width, op) \
1500	9a64fbe4	bellard	OP_ST_TABLE(width); \
1501	9a64fbe4	bellard	GEN_STF(width, op \| 0x20); \
1502	9a64fbe4	bellard	GEN_STUF(width, op \| 0x21); \
1503	9a64fbe4	bellard	GEN_STUXF(width, op \| 0x01); \
1504	9a64fbe4	bellard	GEN_STXF(width, 0x17, op \| 0x00)
1505	79aceca5	bellard
1506	79aceca5	bellard	/* stfd stfdu stfdux stfdx */
1507	9a64fbe4	bellard	GEN_STFS(fd, 0x16);
1508	79aceca5	bellard	/* stfs stfsu stfsux stfsx */
1509	9a64fbe4	bellard	GEN_STFS(fs, 0x14);
1510	79aceca5	bellard
1511	79aceca5	bellard	/* Optional: */
1512	79aceca5	bellard	/* stfiwx */
1513	79aceca5	bellard	GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1514	79aceca5	bellard	{
1515	9fddaa0c	bellard	RET_INVAL(ctx);
1516	79aceca5	bellard	}
1517	79aceca5	bellard
1518	79aceca5	bellard	/* Branch */
1519	79aceca5	bellard
1520	79aceca5	bellard	/* b ba bl bla */
1521	79aceca5	bellard	GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1522	79aceca5	bellard	{
1523	79aceca5	bellard	uint32_t li = s_ext24(LI(ctx->opcode)), target;
1524	79aceca5	bellard
1525	79aceca5	bellard	if (AA(ctx->opcode) == 0)
1526	046d6672	bellard	target = ctx->nip + li - 4;
1527	79aceca5	bellard	else
1528	9a64fbe4	bellard	target = li;
1529	9a64fbe4	bellard	if (LK(ctx->opcode)) {
1530	046d6672	bellard	gen_op_setlr(ctx->nip);
1531	9a64fbe4	bellard	}
1532	e98a6e40	bellard	gen_op_b((long)ctx->tb, target);
1533	9a64fbe4	bellard	ctx->exception = EXCP_BRANCH;
1534	79aceca5	bellard	}
1535	79aceca5	bellard
1536	e98a6e40	bellard	#define BCOND_IM 0
1537	e98a6e40	bellard	#define BCOND_LR 1
1538	e98a6e40	bellard	#define BCOND_CTR 2
1539	e98a6e40	bellard
1540	e98a6e40	bellard	static inline void gen_bcond(DisasContext *ctx, int type)
1541	e98a6e40	bellard	{
1542	e98a6e40	bellard	uint32_t target = 0;
1543	e98a6e40	bellard	uint32_t bo = BO(ctx->opcode);
1544	e98a6e40	bellard	uint32_t bi = BI(ctx->opcode);
1545	e98a6e40	bellard	uint32_t mask;
1546	e98a6e40	bellard	uint32_t li;
1547	e98a6e40	bellard
1548	e98a6e40	bellard	if ((bo & 0x4) == 0)
1549	e98a6e40	bellard	gen_op_dec_ctr();
1550	e98a6e40	bellard	switch(type) {
1551	e98a6e40	bellard	case BCOND_IM:
1552	e98a6e40	bellard	li = s_ext16(BD(ctx->opcode));
1553	e98a6e40	bellard	if (AA(ctx->opcode) == 0) {
1554	046d6672	bellard	target = ctx->nip + li - 4;
1555	e98a6e40	bellard	} else {
1556	e98a6e40	bellard	target = li;
1557	e98a6e40	bellard	}
1558	e98a6e40	bellard	break;
1559	e98a6e40	bellard	case BCOND_CTR:
1560	e98a6e40	bellard	gen_op_movl_T1_ctr();
1561	e98a6e40	bellard	break;
1562	e98a6e40	bellard	default:
1563	e98a6e40	bellard	case BCOND_LR:
1564	e98a6e40	bellard	gen_op_movl_T1_lr();
1565	e98a6e40	bellard	break;
1566	e98a6e40	bellard	}
1567	e98a6e40	bellard	if (LK(ctx->opcode)) {
1568	046d6672	bellard	gen_op_setlr(ctx->nip);
1569	e98a6e40	bellard	}
1570	e98a6e40	bellard	if (bo & 0x10) {
1571	e98a6e40	bellard	/* No CR condition */
1572	e98a6e40	bellard	switch (bo & 0x6) {
1573	e98a6e40	bellard	case 0:
1574	e98a6e40	bellard	gen_op_test_ctr();
1575	e98a6e40	bellard	break;
1576	e98a6e40	bellard	case 2:
1577	e98a6e40	bellard	gen_op_test_ctrz();
1578	e98a6e40	bellard	break;
1579	e98a6e40	bellard	default:
1580	e98a6e40	bellard	case 4:
1581	e98a6e40	bellard	case 6:
1582	e98a6e40	bellard	if (type == BCOND_IM) {
1583	e98a6e40	bellard	gen_op_b((long)ctx->tb, target);
1584	e98a6e40	bellard	} else {
1585	e98a6e40	bellard	gen_op_b_T1();
1586	e98a6e40	bellard	}
1587	e98a6e40	bellard	goto no_test;
1588	e98a6e40	bellard	}
1589	e98a6e40	bellard	} else {
1590	e98a6e40	bellard	mask = 1 << (3 - (bi & 0x03));
1591	e98a6e40	bellard	gen_op_load_crf_T0(bi >> 2);
1592	e98a6e40	bellard	if (bo & 0x8) {
1593	e98a6e40	bellard	switch (bo & 0x6) {
1594	e98a6e40	bellard	case 0:
1595	e98a6e40	bellard	gen_op_test_ctr_true(mask);
1596	e98a6e40	bellard	break;
1597	e98a6e40	bellard	case 2:
1598	e98a6e40	bellard	gen_op_test_ctrz_true(mask);
1599	e98a6e40	bellard	break;
1600	e98a6e40	bellard	default:
1601	e98a6e40	bellard	case 4:
1602	e98a6e40	bellard	case 6:
1603	e98a6e40	bellard	gen_op_test_true(mask);
1604	e98a6e40	bellard	break;
1605	e98a6e40	bellard	}
1606	e98a6e40	bellard	} else {
1607	e98a6e40	bellard	switch (bo & 0x6) {
1608	e98a6e40	bellard	case 0:
1609	e98a6e40	bellard	gen_op_test_ctr_false(mask);
1610	e98a6e40	bellard	break;
1611	e98a6e40	bellard	case 2:
1612	e98a6e40	bellard	gen_op_test_ctrz_false(mask);
1613	e98a6e40	bellard	break;
1614	e98a6e40	bellard	default:
1615	e98a6e40	bellard	case 4:
1616	e98a6e40	bellard	case 6:
1617	e98a6e40	bellard	gen_op_test_false(mask);
1618	e98a6e40	bellard	break;
1619	e98a6e40	bellard	}
1620	e98a6e40	bellard	}
1621	e98a6e40	bellard	}
1622	e98a6e40	bellard	if (type == BCOND_IM) {
1623	046d6672	bellard	gen_op_btest((long)ctx->tb, target, ctx->nip);
1624	e98a6e40	bellard	} else {
1625	046d6672	bellard	gen_op_btest_T1(ctx->nip);
1626	e98a6e40	bellard	}
1627	e98a6e40	bellard	no_test:
1628	e98a6e40	bellard	ctx->exception = EXCP_BRANCH;
1629	e98a6e40	bellard	}
1630	e98a6e40	bellard
1631	e98a6e40	bellard	GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1632	e98a6e40	bellard	{
1633	e98a6e40	bellard	gen_bcond(ctx, BCOND_IM);
1634	e98a6e40	bellard	}
1635	e98a6e40	bellard
1636	e98a6e40	bellard	GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1637	e98a6e40	bellard	{
1638	e98a6e40	bellard	gen_bcond(ctx, BCOND_CTR);
1639	e98a6e40	bellard	}
1640	e98a6e40	bellard
1641	e98a6e40	bellard	GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1642	e98a6e40	bellard	{
1643	e98a6e40	bellard	gen_bcond(ctx, BCOND_LR);
1644	e98a6e40	bellard	}
1645	79aceca5	bellard
1646	79aceca5	bellard	/* Condition register logical */
1647	79aceca5	bellard	#define GEN_CRLOGIC(op, opc) \
1648	79aceca5	bellard	GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1649	79aceca5	bellard	{ \
1650	79aceca5	bellard	gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1651	79aceca5	bellard	gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1652	79aceca5	bellard	gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1653	79aceca5	bellard	gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1654	79aceca5	bellard	gen_op_##op(); \
1655	79aceca5	bellard	gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1656	79aceca5	bellard	gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1657	79aceca5	bellard	3 - (crbD(ctx->opcode) & 0x03)); \
1658	79aceca5	bellard	gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
1659	79aceca5	bellard	}
1660	79aceca5	bellard
1661	79aceca5	bellard	/* crand */
1662	79aceca5	bellard	GEN_CRLOGIC(and, 0x08)
1663	79aceca5	bellard	/* crandc */
1664	79aceca5	bellard	GEN_CRLOGIC(andc, 0x04)
1665	79aceca5	bellard	/* creqv */
1666	79aceca5	bellard	GEN_CRLOGIC(eqv, 0x09)
1667	79aceca5	bellard	/* crnand */
1668	79aceca5	bellard	GEN_CRLOGIC(nand, 0x07)
1669	79aceca5	bellard	/* crnor */
1670	79aceca5	bellard	GEN_CRLOGIC(nor, 0x01)
1671	79aceca5	bellard	/* cror */
1672	79aceca5	bellard	GEN_CRLOGIC(or, 0x0E)
1673	79aceca5	bellard	/* crorc */
1674	79aceca5	bellard	GEN_CRLOGIC(orc, 0x0D)
1675	79aceca5	bellard	/* crxor */
1676	79aceca5	bellard	GEN_CRLOGIC(xor, 0x06)
1677	79aceca5	bellard	/* mcrf */
1678	79aceca5	bellard	GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1679	79aceca5	bellard	{
1680	79aceca5	bellard	gen_op_load_crf_T0(crfS(ctx->opcode));
1681	79aceca5	bellard	gen_op_store_T0_crf(crfD(ctx->opcode));
1682	79aceca5	bellard	}
1683	79aceca5	bellard
1684	79aceca5	bellard	/* System linkage */
1685	79aceca5	bellard	/* rfi (supervisor only) */
1686	79aceca5	bellard	GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1687	79aceca5	bellard	{
1688	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
1689	9fddaa0c	bellard	RET_PRIVOPC(ctx);
1690	9a64fbe4	bellard	#else
1691	9a64fbe4	bellard	/* Restore CPU state */
1692	9a64fbe4	bellard	if (!ctx->supervisor) {
1693	9fddaa0c	bellard	RET_PRIVOPC(ctx);
1694	9fddaa0c	bellard	return;
1695	9a64fbe4	bellard	}
1696	9a64fbe4	bellard	gen_op_rfi();
1697	9fddaa0c	bellard	RET_EXCP(ctx, EXCP_RFI, 0);
1698	9a64fbe4	bellard	#endif
1699	79aceca5	bellard	}
1700	79aceca5	bellard
1701	79aceca5	bellard	/* sc */
1702	79aceca5	bellard	GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1703	79aceca5	bellard	{
1704	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
1705	9fddaa0c	bellard	RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
1706	9a64fbe4	bellard	#else
1707	9fddaa0c	bellard	RET_EXCP(ctx, EXCP_SYSCALL, 0);
1708	9a64fbe4	bellard	#endif
1709	79aceca5	bellard	}
1710	79aceca5	bellard
1711	79aceca5	bellard	/* Trap */
1712	79aceca5	bellard	/* tw */
1713	79aceca5	bellard	GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1714	79aceca5	bellard	{
1715	9a64fbe4	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
1716	9a64fbe4	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
1717	9a64fbe4	bellard	gen_op_tw(TO(ctx->opcode));
1718	79aceca5	bellard	}
1719	79aceca5	bellard
1720	79aceca5	bellard	/* twi */
1721	79aceca5	bellard	GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1722	79aceca5	bellard	{
1723	9a64fbe4	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
1724	9a64fbe4	bellard	#if 0
1725	9a64fbe4	bellard	printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1726	9a64fbe4	bellard	SIMM(ctx->opcode), TO(ctx->opcode));
1727	9a64fbe4	bellard	#endif
1728	9a64fbe4	bellard	gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
1729	79aceca5	bellard	}
1730	79aceca5	bellard
1731	79aceca5	bellard	/* Processor control */
1732	79aceca5	bellard	static inline int check_spr_access (int spr, int rw, int supervisor)
1733	79aceca5	bellard	{
1734	79aceca5	bellard	uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1735	79aceca5	bellard
1736	9a64fbe4	bellard	#if 0
1737	9a64fbe4	bellard	if (spr != LR && spr != CTR) {
1738	9a64fbe4	bellard	if (loglevel > 0) {
1739	9a64fbe4	bellard	fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1740	9a64fbe4	bellard	SPR_ENCODE(spr), supervisor, rw, rights,
1741	9a64fbe4	bellard	(rights >> ((2 * supervisor) + rw)) & 1);
1742	9a64fbe4	bellard	} else {
1743	9a64fbe4	bellard	printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1744	9a64fbe4	bellard	SPR_ENCODE(spr), supervisor, rw, rights,
1745	9a64fbe4	bellard	(rights >> ((2 * supervisor) + rw)) & 1);
1746	9a64fbe4	bellard	}
1747	9a64fbe4	bellard	}
1748	9a64fbe4	bellard	#endif
1749	9a64fbe4	bellard	if (rights == 0)
1750	9a64fbe4	bellard	return -1;
1751	79aceca5	bellard	rights = rights >> (2 * supervisor);
1752	79aceca5	bellard	rights = rights >> rw;
1753	79aceca5	bellard
1754	79aceca5	bellard	return rights & 1;
1755	79aceca5	bellard	}
1756	79aceca5	bellard
1757	79aceca5	bellard	/* mcrxr */
1758	79aceca5	bellard	GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
1759	79aceca5	bellard	{
1760	79aceca5	bellard	gen_op_load_xer_cr();
1761	79aceca5	bellard	gen_op_store_T0_crf(crfD(ctx->opcode));
1762	79aceca5	bellard	gen_op_clear_xer_cr();
1763	79aceca5	bellard	}
1764	79aceca5	bellard
1765	79aceca5	bellard	/* mfcr */
1766	79aceca5	bellard	GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
1767	79aceca5	bellard	{
1768	79aceca5	bellard	gen_op_load_cr();
1769	79aceca5	bellard	gen_op_store_T0_gpr(rD(ctx->opcode));
1770	79aceca5	bellard	}
1771	79aceca5	bellard
1772	79aceca5	bellard	/* mfmsr */
1773	79aceca5	bellard	GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
1774	79aceca5	bellard	{
1775	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
1776	9fddaa0c	bellard	RET_PRIVREG(ctx);
1777	9a64fbe4	bellard	#else
1778	9a64fbe4	bellard	if (!ctx->supervisor) {
1779	9fddaa0c	bellard	RET_PRIVREG(ctx);
1780	9fddaa0c	bellard	return;
1781	9a64fbe4	bellard	}
1782	79aceca5	bellard	gen_op_load_msr();
1783	79aceca5	bellard	gen_op_store_T0_gpr(rD(ctx->opcode));
1784	9a64fbe4	bellard	#endif
1785	79aceca5	bellard	}
1786	79aceca5	bellard
1787	79aceca5	bellard	/* mfspr */
1788	79aceca5	bellard	GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
1789	79aceca5	bellard	{
1790	79aceca5	bellard	uint32_t sprn = SPR(ctx->opcode);
1791	79aceca5	bellard
1792	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
1793	9a64fbe4	bellard	switch (check_spr_access(sprn, 0, 0))
1794	9a64fbe4	bellard	#else
1795	9a64fbe4	bellard	switch (check_spr_access(sprn, 0, ctx->supervisor))
1796	9a64fbe4	bellard	#endif
1797	9a64fbe4	bellard	{
1798	9a64fbe4	bellard	case -1:
1799	9fddaa0c	bellard	RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL \| EXCP_INVAL_SPR);
1800	9fddaa0c	bellard	return;
1801	9a64fbe4	bellard	case 0:
1802	9fddaa0c	bellard	RET_PRIVREG(ctx);
1803	9fddaa0c	bellard	return;
1804	9a64fbe4	bellard	default:
1805	9a64fbe4	bellard	break;
1806	79aceca5	bellard	}
1807	9a64fbe4	bellard	switch (sprn) {
1808	9a64fbe4	bellard	case XER:
1809	79aceca5	bellard	gen_op_load_xer();
1810	79aceca5	bellard	break;
1811	9a64fbe4	bellard	case LR:
1812	9a64fbe4	bellard	gen_op_load_lr();
1813	9a64fbe4	bellard	break;
1814	9a64fbe4	bellard	case CTR:
1815	9a64fbe4	bellard	gen_op_load_ctr();
1816	9a64fbe4	bellard	break;
1817	9a64fbe4	bellard	case IBAT0U:
1818	9a64fbe4	bellard	gen_op_load_ibat(0, 0);
1819	9a64fbe4	bellard	break;
1820	9a64fbe4	bellard	case IBAT1U:
1821	9a64fbe4	bellard	gen_op_load_ibat(0, 1);
1822	9a64fbe4	bellard	break;
1823	9a64fbe4	bellard	case IBAT2U:
1824	9a64fbe4	bellard	gen_op_load_ibat(0, 2);
1825	9a64fbe4	bellard	break;
1826	9a64fbe4	bellard	case IBAT3U:
1827	9a64fbe4	bellard	gen_op_load_ibat(0, 3);
1828	9a64fbe4	bellard	break;
1829	9a64fbe4	bellard	case IBAT4U:
1830	9a64fbe4	bellard	gen_op_load_ibat(0, 4);
1831	9a64fbe4	bellard	break;
1832	9a64fbe4	bellard	case IBAT5U:
1833	9a64fbe4	bellard	gen_op_load_ibat(0, 5);
1834	9a64fbe4	bellard	break;
1835	9a64fbe4	bellard	case IBAT6U:
1836	9a64fbe4	bellard	gen_op_load_ibat(0, 6);
1837	9a64fbe4	bellard	break;
1838	9a64fbe4	bellard	case IBAT7U:
1839	9a64fbe4	bellard	gen_op_load_ibat(0, 7);
1840	9a64fbe4	bellard	break;
1841	9a64fbe4	bellard	case IBAT0L:
1842	9a64fbe4	bellard	gen_op_load_ibat(1, 0);
1843	9a64fbe4	bellard	break;
1844	9a64fbe4	bellard	case IBAT1L:
1845	9a64fbe4	bellard	gen_op_load_ibat(1, 1);
1846	9a64fbe4	bellard	break;
1847	9a64fbe4	bellard	case IBAT2L:
1848	9a64fbe4	bellard	gen_op_load_ibat(1, 2);
1849	9a64fbe4	bellard	break;
1850	9a64fbe4	bellard	case IBAT3L:
1851	9a64fbe4	bellard	gen_op_load_ibat(1, 3);
1852	9a64fbe4	bellard	break;
1853	9a64fbe4	bellard	case IBAT4L:
1854	9a64fbe4	bellard	gen_op_load_ibat(1, 4);
1855	9a64fbe4	bellard	break;
1856	9a64fbe4	bellard	case IBAT5L:
1857	9a64fbe4	bellard	gen_op_load_ibat(1, 5);
1858	9a64fbe4	bellard	break;
1859	9a64fbe4	bellard	case IBAT6L:
1860	9a64fbe4	bellard	gen_op_load_ibat(1, 6);
1861	9a64fbe4	bellard	break;
1862	9a64fbe4	bellard	case IBAT7L:
1863	9a64fbe4	bellard	gen_op_load_ibat(1, 7);
1864	9a64fbe4	bellard	break;
1865	9a64fbe4	bellard	case DBAT0U:
1866	9a64fbe4	bellard	gen_op_load_dbat(0, 0);
1867	9a64fbe4	bellard	break;
1868	9a64fbe4	bellard	case DBAT1U:
1869	9a64fbe4	bellard	gen_op_load_dbat(0, 1);
1870	9a64fbe4	bellard	break;
1871	9a64fbe4	bellard	case DBAT2U:
1872	9a64fbe4	bellard	gen_op_load_dbat(0, 2);
1873	9a64fbe4	bellard	break;
1874	9a64fbe4	bellard	case DBAT3U:
1875	9a64fbe4	bellard	gen_op_load_dbat(0, 3);
1876	9a64fbe4	bellard	break;
1877	9a64fbe4	bellard	case DBAT4U:
1878	9a64fbe4	bellard	gen_op_load_dbat(0, 4);
1879	9a64fbe4	bellard	break;
1880	9a64fbe4	bellard	case DBAT5U:
1881	9a64fbe4	bellard	gen_op_load_dbat(0, 5);
1882	9a64fbe4	bellard	break;
1883	9a64fbe4	bellard	case DBAT6U:
1884	9a64fbe4	bellard	gen_op_load_dbat(0, 6);
1885	9a64fbe4	bellard	break;
1886	9a64fbe4	bellard	case DBAT7U:
1887	9a64fbe4	bellard	gen_op_load_dbat(0, 7);
1888	9a64fbe4	bellard	break;
1889	9a64fbe4	bellard	case DBAT0L:
1890	9a64fbe4	bellard	gen_op_load_dbat(1, 0);
1891	9a64fbe4	bellard	break;
1892	9a64fbe4	bellard	case DBAT1L:
1893	9a64fbe4	bellard	gen_op_load_dbat(1, 1);
1894	9a64fbe4	bellard	break;
1895	9a64fbe4	bellard	case DBAT2L:
1896	9a64fbe4	bellard	gen_op_load_dbat(1, 2);
1897	9a64fbe4	bellard	break;
1898	9a64fbe4	bellard	case DBAT3L:
1899	9a64fbe4	bellard	gen_op_load_dbat(1, 3);
1900	9a64fbe4	bellard	break;
1901	9a64fbe4	bellard	case DBAT4L:
1902	9a64fbe4	bellard	gen_op_load_dbat(1, 4);
1903	9a64fbe4	bellard	break;
1904	9a64fbe4	bellard	case DBAT5L:
1905	9a64fbe4	bellard	gen_op_load_dbat(1, 5);
1906	9a64fbe4	bellard	break;
1907	9a64fbe4	bellard	case DBAT6L:
1908	9a64fbe4	bellard	gen_op_load_dbat(1, 6);
1909	9a64fbe4	bellard	break;
1910	9a64fbe4	bellard	case DBAT7L:
1911	9a64fbe4	bellard	gen_op_load_dbat(1, 7);
1912	9a64fbe4	bellard	break;
1913	9a64fbe4	bellard	case SDR1:
1914	9a64fbe4	bellard	gen_op_load_sdr1();
1915	9a64fbe4	bellard	break;
1916	9a64fbe4	bellard	case V_TBL:
1917	9fddaa0c	bellard	gen_op_load_tbl();
1918	79aceca5	bellard	break;
1919	9a64fbe4	bellard	case V_TBU:
1920	9fddaa0c	bellard	gen_op_load_tbu();
1921	9a64fbe4	bellard	break;
1922	9a64fbe4	bellard	case DECR:
1923	9fddaa0c	bellard	gen_op_load_decr();
1924	79aceca5	bellard	break;
1925	79aceca5	bellard	default:
1926	79aceca5	bellard	gen_op_load_spr(sprn);
1927	79aceca5	bellard	break;
1928	79aceca5	bellard	}
1929	9a64fbe4	bellard	gen_op_store_T0_gpr(rD(ctx->opcode));
1930	79aceca5	bellard	}
1931	79aceca5	bellard
1932	79aceca5	bellard	/* mftb */
1933	79aceca5	bellard	GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC)
1934	79aceca5	bellard	{
1935	79aceca5	bellard	uint32_t sprn = SPR(ctx->opcode);
1936	79aceca5	bellard
1937	79aceca5	bellard	/* We need to update the time base before reading it */
1938	9a64fbe4	bellard	switch (sprn) {
1939	9a64fbe4	bellard	case V_TBL:
1940	9fddaa0c	bellard	gen_op_load_tbl();
1941	79aceca5	bellard	break;
1942	9a64fbe4	bellard	case V_TBU:
1943	9fddaa0c	bellard	gen_op_load_tbu();
1944	79aceca5	bellard	break;
1945	79aceca5	bellard	default:
1946	9fddaa0c	bellard	RET_INVAL(ctx);
1947	9fddaa0c	bellard	return;
1948	79aceca5	bellard	}
1949	9a64fbe4	bellard	gen_op_store_T0_gpr(rD(ctx->opcode));
1950	79aceca5	bellard	}
1951	79aceca5	bellard
1952	79aceca5	bellard	/* mtcrf */
1953	79aceca5	bellard	GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC)
1954	79aceca5	bellard	{
1955	79aceca5	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
1956	79aceca5	bellard	gen_op_store_cr(CRM(ctx->opcode));
1957	79aceca5	bellard	}
1958	79aceca5	bellard
1959	79aceca5	bellard	/* mtmsr */
1960	79aceca5	bellard	GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
1961	79aceca5	bellard	{
1962	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
1963	9fddaa0c	bellard	RET_PRIVREG(ctx);
1964	9a64fbe4	bellard	#else
1965	9a64fbe4	bellard	if (!ctx->supervisor) {
1966	9fddaa0c	bellard	RET_PRIVREG(ctx);
1967	9fddaa0c	bellard	return;
1968	9a64fbe4	bellard	}
1969	79aceca5	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
1970	79aceca5	bellard	gen_op_store_msr();
1971	79aceca5	bellard	/* Must stop the translation as machine state (may have) changed */
1972	9fddaa0c	bellard	RET_MTMSR(ctx);
1973	9a64fbe4	bellard	#endif
1974	79aceca5	bellard	}
1975	79aceca5	bellard
1976	79aceca5	bellard	/* mtspr */
1977	79aceca5	bellard	GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
1978	79aceca5	bellard	{
1979	79aceca5	bellard	uint32_t sprn = SPR(ctx->opcode);
1980	79aceca5	bellard
1981	9a64fbe4	bellard	#if 0
1982	9a64fbe4	bellard	if (loglevel > 0) {
1983	9a64fbe4	bellard	fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
1984	9a64fbe4	bellard	rS(ctx->opcode), sprn);
1985	9a64fbe4	bellard	}
1986	9a64fbe4	bellard	#endif
1987	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
1988	9a64fbe4	bellard	switch (check_spr_access(sprn, 1, 0))
1989	9a64fbe4	bellard	#else
1990	9a64fbe4	bellard	switch (check_spr_access(sprn, 1, ctx->supervisor))
1991	9a64fbe4	bellard	#endif
1992	9a64fbe4	bellard	{
1993	9a64fbe4	bellard	case -1:
1994	9fddaa0c	bellard	RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL \| EXCP_INVAL_SPR);
1995	9a64fbe4	bellard	break;
1996	9a64fbe4	bellard	case 0:
1997	9fddaa0c	bellard	RET_PRIVREG(ctx);
1998	9a64fbe4	bellard	break;
1999	9a64fbe4	bellard	default:
2000	9a64fbe4	bellard	break;
2001	9a64fbe4	bellard	}
2002	79aceca5	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
2003	9a64fbe4	bellard	switch (sprn) {
2004	9a64fbe4	bellard	case XER:
2005	79aceca5	bellard	gen_op_store_xer();
2006	9a64fbe4	bellard	break;
2007	9a64fbe4	bellard	case LR:
2008	9a64fbe4	bellard	gen_op_store_lr();
2009	9a64fbe4	bellard	break;
2010	9a64fbe4	bellard	case CTR:
2011	9a64fbe4	bellard	gen_op_store_ctr();
2012	9a64fbe4	bellard	break;
2013	9a64fbe4	bellard	case IBAT0U:
2014	9a64fbe4	bellard	gen_op_store_ibat(0, 0);
2015	4b3686fa	bellard	RET_MTMSR(ctx);
2016	9a64fbe4	bellard	break;
2017	9a64fbe4	bellard	case IBAT1U:
2018	9a64fbe4	bellard	gen_op_store_ibat(0, 1);
2019	4b3686fa	bellard	RET_MTMSR(ctx);
2020	9a64fbe4	bellard	break;
2021	9a64fbe4	bellard	case IBAT2U:
2022	9a64fbe4	bellard	gen_op_store_ibat(0, 2);
2023	4b3686fa	bellard	RET_MTMSR(ctx);
2024	9a64fbe4	bellard	break;
2025	9a64fbe4	bellard	case IBAT3U:
2026	9a64fbe4	bellard	gen_op_store_ibat(0, 3);
2027	4b3686fa	bellard	RET_MTMSR(ctx);
2028	9a64fbe4	bellard	break;
2029	9a64fbe4	bellard	case IBAT4U:
2030	9a64fbe4	bellard	gen_op_store_ibat(0, 4);
2031	4b3686fa	bellard	RET_MTMSR(ctx);
2032	9a64fbe4	bellard	break;
2033	9a64fbe4	bellard	case IBAT5U:
2034	9a64fbe4	bellard	gen_op_store_ibat(0, 5);
2035	4b3686fa	bellard	RET_MTMSR(ctx);
2036	9a64fbe4	bellard	break;
2037	9a64fbe4	bellard	case IBAT6U:
2038	9a64fbe4	bellard	gen_op_store_ibat(0, 6);
2039	4b3686fa	bellard	RET_MTMSR(ctx);
2040	9a64fbe4	bellard	break;
2041	9a64fbe4	bellard	case IBAT7U:
2042	9a64fbe4	bellard	gen_op_store_ibat(0, 7);
2043	4b3686fa	bellard	RET_MTMSR(ctx);
2044	9a64fbe4	bellard	break;
2045	9a64fbe4	bellard	case IBAT0L:
2046	9a64fbe4	bellard	gen_op_store_ibat(1, 0);
2047	4b3686fa	bellard	RET_MTMSR(ctx);
2048	9a64fbe4	bellard	break;
2049	9a64fbe4	bellard	case IBAT1L:
2050	9a64fbe4	bellard	gen_op_store_ibat(1, 1);
2051	4b3686fa	bellard	RET_MTMSR(ctx);
2052	9a64fbe4	bellard	break;
2053	9a64fbe4	bellard	case IBAT2L:
2054	9a64fbe4	bellard	gen_op_store_ibat(1, 2);
2055	4b3686fa	bellard	RET_MTMSR(ctx);
2056	9a64fbe4	bellard	break;
2057	9a64fbe4	bellard	case IBAT3L:
2058	9a64fbe4	bellard	gen_op_store_ibat(1, 3);
2059	4b3686fa	bellard	RET_MTMSR(ctx);
2060	9a64fbe4	bellard	break;
2061	9a64fbe4	bellard	case IBAT4L:
2062	9a64fbe4	bellard	gen_op_store_ibat(1, 4);
2063	4b3686fa	bellard	RET_MTMSR(ctx);
2064	9a64fbe4	bellard	break;
2065	9a64fbe4	bellard	case IBAT5L:
2066	9a64fbe4	bellard	gen_op_store_ibat(1, 5);
2067	4b3686fa	bellard	RET_MTMSR(ctx);
2068	9a64fbe4	bellard	break;
2069	9a64fbe4	bellard	case IBAT6L:
2070	9a64fbe4	bellard	gen_op_store_ibat(1, 6);
2071	4b3686fa	bellard	RET_MTMSR(ctx);
2072	9a64fbe4	bellard	break;
2073	9a64fbe4	bellard	case IBAT7L:
2074	9a64fbe4	bellard	gen_op_store_ibat(1, 7);
2075	4b3686fa	bellard	RET_MTMSR(ctx);
2076	9a64fbe4	bellard	break;
2077	9a64fbe4	bellard	case DBAT0U:
2078	9a64fbe4	bellard	gen_op_store_dbat(0, 0);
2079	4b3686fa	bellard	RET_MTMSR(ctx);
2080	9a64fbe4	bellard	break;
2081	9a64fbe4	bellard	case DBAT1U:
2082	9a64fbe4	bellard	gen_op_store_dbat(0, 1);
2083	4b3686fa	bellard	RET_MTMSR(ctx);
2084	9a64fbe4	bellard	break;
2085	9a64fbe4	bellard	case DBAT2U:
2086	9a64fbe4	bellard	gen_op_store_dbat(0, 2);
2087	4b3686fa	bellard	RET_MTMSR(ctx);
2088	9a64fbe4	bellard	break;
2089	9a64fbe4	bellard	case DBAT3U:
2090	9a64fbe4	bellard	gen_op_store_dbat(0, 3);
2091	4b3686fa	bellard	RET_MTMSR(ctx);
2092	9a64fbe4	bellard	break;
2093	9a64fbe4	bellard	case DBAT4U:
2094	9a64fbe4	bellard	gen_op_store_dbat(0, 4);
2095	4b3686fa	bellard	RET_MTMSR(ctx);
2096	9a64fbe4	bellard	break;
2097	9a64fbe4	bellard	case DBAT5U:
2098	9a64fbe4	bellard	gen_op_store_dbat(0, 5);
2099	4b3686fa	bellard	RET_MTMSR(ctx);
2100	9a64fbe4	bellard	break;
2101	9a64fbe4	bellard	case DBAT6U:
2102	9a64fbe4	bellard	gen_op_store_dbat(0, 6);
2103	4b3686fa	bellard	RET_MTMSR(ctx);
2104	9a64fbe4	bellard	break;
2105	9a64fbe4	bellard	case DBAT7U:
2106	9a64fbe4	bellard	gen_op_store_dbat(0, 7);
2107	4b3686fa	bellard	RET_MTMSR(ctx);
2108	9a64fbe4	bellard	break;
2109	9a64fbe4	bellard	case DBAT0L:
2110	9a64fbe4	bellard	gen_op_store_dbat(1, 0);
2111	4b3686fa	bellard	RET_MTMSR(ctx);
2112	9a64fbe4	bellard	break;
2113	9a64fbe4	bellard	case DBAT1L:
2114	9a64fbe4	bellard	gen_op_store_dbat(1, 1);
2115	4b3686fa	bellard	RET_MTMSR(ctx);
2116	9a64fbe4	bellard	break;
2117	9a64fbe4	bellard	case DBAT2L:
2118	9a64fbe4	bellard	gen_op_store_dbat(1, 2);
2119	4b3686fa	bellard	RET_MTMSR(ctx);
2120	9a64fbe4	bellard	break;
2121	9a64fbe4	bellard	case DBAT3L:
2122	9a64fbe4	bellard	gen_op_store_dbat(1, 3);
2123	4b3686fa	bellard	RET_MTMSR(ctx);
2124	9a64fbe4	bellard	break;
2125	9a64fbe4	bellard	case DBAT4L:
2126	9a64fbe4	bellard	gen_op_store_dbat(1, 4);
2127	4b3686fa	bellard	RET_MTMSR(ctx);
2128	9a64fbe4	bellard	break;
2129	9a64fbe4	bellard	case DBAT5L:
2130	9a64fbe4	bellard	gen_op_store_dbat(1, 5);
2131	4b3686fa	bellard	RET_MTMSR(ctx);
2132	9a64fbe4	bellard	break;
2133	9a64fbe4	bellard	case DBAT6L:
2134	9a64fbe4	bellard	gen_op_store_dbat(1, 6);
2135	4b3686fa	bellard	RET_MTMSR(ctx);
2136	9a64fbe4	bellard	break;
2137	9a64fbe4	bellard	case DBAT7L:
2138	9a64fbe4	bellard	gen_op_store_dbat(1, 7);
2139	4b3686fa	bellard	RET_MTMSR(ctx);
2140	9a64fbe4	bellard	break;
2141	9a64fbe4	bellard	case SDR1:
2142	9a64fbe4	bellard	gen_op_store_sdr1();
2143	4b3686fa	bellard	RET_MTMSR(ctx);
2144	9a64fbe4	bellard	break;
2145	9a64fbe4	bellard	case O_TBL:
2146	9fddaa0c	bellard	gen_op_store_tbl();
2147	9a64fbe4	bellard	break;
2148	9a64fbe4	bellard	case O_TBU:
2149	9fddaa0c	bellard	gen_op_store_tbu();
2150	9a64fbe4	bellard	break;
2151	9a64fbe4	bellard	case DECR:
2152	9a64fbe4	bellard	gen_op_store_decr();
2153	9a64fbe4	bellard	break;
2154	4b3686fa	bellard	#if 0
2155	4b3686fa	bellard	case HID0:
2156	4b3686fa	bellard	gen_op_store_hid0();
2157	4b3686fa	bellard	break;
2158	4b3686fa	bellard	#endif
2159	9a64fbe4	bellard	default:
2160	79aceca5	bellard	gen_op_store_spr(sprn);
2161	9a64fbe4	bellard	break;
2162	79aceca5	bellard	}
2163	79aceca5	bellard	}
2164	79aceca5	bellard
2165	79aceca5	bellard	/* Cache management */
2166	79aceca5	bellard	/* For now, all those will be implemented as nop:
2167	79aceca5	bellard	* this is valid, regarding the PowerPC specs...
2168	9a64fbe4	bellard	* We just have to flush tb while invalidating instruction cache lines...
2169	79aceca5	bellard	*/
2170	79aceca5	bellard	/* dcbf */
2171	9a64fbe4	bellard	GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
2172	79aceca5	bellard	{
2173	a541f297	bellard	if (rA(ctx->opcode) == 0) {
2174	a541f297	bellard	gen_op_load_gpr_T0(rB(ctx->opcode));
2175	a541f297	bellard	} else {
2176	a541f297	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
2177	a541f297	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
2178	a541f297	bellard	gen_op_add();
2179	a541f297	bellard	}
2180	a541f297	bellard	op_ldst(lbz);
2181	79aceca5	bellard	}
2182	79aceca5	bellard
2183	79aceca5	bellard	/* dcbi (Supervisor only) */
2184	9a64fbe4	bellard	GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
2185	79aceca5	bellard	{
2186	a541f297	bellard	#if defined(CONFIG_USER_ONLY)
2187	9fddaa0c	bellard	RET_PRIVOPC(ctx);
2188	a541f297	bellard	#else
2189	a541f297	bellard	if (!ctx->supervisor) {
2190	9fddaa0c	bellard	RET_PRIVOPC(ctx);
2191	9fddaa0c	bellard	return;
2192	9a64fbe4	bellard	}
2193	a541f297	bellard	if (rA(ctx->opcode) == 0) {
2194	a541f297	bellard	gen_op_load_gpr_T0(rB(ctx->opcode));
2195	a541f297	bellard	} else {
2196	a541f297	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
2197	a541f297	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
2198	a541f297	bellard	gen_op_add();
2199	a541f297	bellard	}
2200	a541f297	bellard	op_ldst(lbz);
2201	a541f297	bellard	op_ldst(stb);
2202	a541f297	bellard	#endif
2203	79aceca5	bellard	}
2204	79aceca5	bellard
2205	79aceca5	bellard	/* dcdst */
2206	9a64fbe4	bellard	GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
2207	79aceca5	bellard	{
2208	a541f297	bellard	if (rA(ctx->opcode) == 0) {
2209	a541f297	bellard	gen_op_load_gpr_T0(rB(ctx->opcode));
2210	a541f297	bellard	} else {
2211	a541f297	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
2212	a541f297	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
2213	a541f297	bellard	gen_op_add();
2214	a541f297	bellard	}
2215	a541f297	bellard	op_ldst(lbz);
2216	79aceca5	bellard	}
2217	79aceca5	bellard
2218	79aceca5	bellard	/* dcbt */
2219	9a64fbe4	bellard	GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
2220	79aceca5	bellard	{
2221	79aceca5	bellard	}
2222	79aceca5	bellard
2223	79aceca5	bellard	/* dcbtst */
2224	9a64fbe4	bellard	GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
2225	79aceca5	bellard	{
2226	79aceca5	bellard	}
2227	79aceca5	bellard
2228	79aceca5	bellard	/* dcbz */
2229	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
2230	9a64fbe4	bellard	#define op_dcbz() gen_op_dcbz_raw()
2231	9a64fbe4	bellard	#else
2232	9a64fbe4	bellard	#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2233	9a64fbe4	bellard	static GenOpFunc *gen_op_dcbz[] = {
2234	9a64fbe4	bellard	&gen_op_dcbz_user,
2235	9a64fbe4	bellard	&gen_op_dcbz_kernel,
2236	9a64fbe4	bellard	};
2237	9a64fbe4	bellard	#endif
2238	9a64fbe4	bellard
2239	9a64fbe4	bellard	GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
2240	79aceca5	bellard	{
2241	fb0eaffc	bellard	if (rA(ctx->opcode) == 0) {
2242	fb0eaffc	bellard	gen_op_load_gpr_T0(rB(ctx->opcode));
2243	fb0eaffc	bellard	} else {
2244	fb0eaffc	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
2245	fb0eaffc	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
2246	9a64fbe4	bellard	gen_op_add();
2247	fb0eaffc	bellard	}
2248	9a64fbe4	bellard	op_dcbz();
2249	4b3686fa	bellard	gen_op_check_reservation();
2250	79aceca5	bellard	}
2251	79aceca5	bellard
2252	79aceca5	bellard	/* icbi */
2253	9a64fbe4	bellard	GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
2254	79aceca5	bellard	{
2255	fb0eaffc	bellard	if (rA(ctx->opcode) == 0) {
2256	fb0eaffc	bellard	gen_op_load_gpr_T0(rB(ctx->opcode));
2257	fb0eaffc	bellard	} else {
2258	fb0eaffc	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
2259	fb0eaffc	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
2260	9a64fbe4	bellard	gen_op_add();
2261	fb0eaffc	bellard	}
2262	9a64fbe4	bellard	gen_op_icbi();
2263	79aceca5	bellard	}
2264	79aceca5	bellard
2265	79aceca5	bellard	/* Optional: */
2266	79aceca5	bellard	/* dcba */
2267	9a64fbe4	bellard	GEN_HANDLER(dcba, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE_OPT)
2268	79aceca5	bellard	{
2269	79aceca5	bellard	}
2270	79aceca5	bellard
2271	79aceca5	bellard	/* Segment register manipulation */
2272	79aceca5	bellard	/* Supervisor only: */
2273	79aceca5	bellard	/* mfsr */
2274	79aceca5	bellard	GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2275	79aceca5	bellard	{
2276	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
2277	9fddaa0c	bellard	RET_PRIVREG(ctx);
2278	9a64fbe4	bellard	#else
2279	9a64fbe4	bellard	if (!ctx->supervisor) {
2280	9fddaa0c	bellard	RET_PRIVREG(ctx);
2281	9fddaa0c	bellard	return;
2282	9a64fbe4	bellard	}
2283	9a64fbe4	bellard	gen_op_load_sr(SR(ctx->opcode));
2284	9a64fbe4	bellard	gen_op_store_T0_gpr(rD(ctx->opcode));
2285	9a64fbe4	bellard	#endif
2286	79aceca5	bellard	}
2287	79aceca5	bellard
2288	79aceca5	bellard	/* mfsrin */
2289	9a64fbe4	bellard	GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
2290	79aceca5	bellard	{
2291	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
2292	9fddaa0c	bellard	RET_PRIVREG(ctx);
2293	9a64fbe4	bellard	#else
2294	9a64fbe4	bellard	if (!ctx->supervisor) {
2295	9fddaa0c	bellard	RET_PRIVREG(ctx);
2296	9fddaa0c	bellard	return;
2297	9a64fbe4	bellard	}
2298	9a64fbe4	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
2299	9a64fbe4	bellard	gen_op_load_srin();
2300	9a64fbe4	bellard	gen_op_store_T0_gpr(rD(ctx->opcode));
2301	9a64fbe4	bellard	#endif
2302	79aceca5	bellard	}
2303	79aceca5	bellard
2304	79aceca5	bellard	/* mtsr */
2305	e63c59cb	bellard	GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
2306	79aceca5	bellard	{
2307	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
2308	9fddaa0c	bellard	RET_PRIVREG(ctx);
2309	9a64fbe4	bellard	#else
2310	9a64fbe4	bellard	if (!ctx->supervisor) {
2311	9fddaa0c	bellard	RET_PRIVREG(ctx);
2312	9fddaa0c	bellard	return;
2313	9a64fbe4	bellard	}
2314	9a64fbe4	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
2315	9a64fbe4	bellard	gen_op_store_sr(SR(ctx->opcode));
2316	9a64fbe4	bellard	#endif
2317	79aceca5	bellard	}
2318	79aceca5	bellard
2319	79aceca5	bellard	/* mtsrin */
2320	9a64fbe4	bellard	GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
2321	79aceca5	bellard	{
2322	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
2323	9fddaa0c	bellard	RET_PRIVREG(ctx);
2324	9a64fbe4	bellard	#else
2325	9a64fbe4	bellard	if (!ctx->supervisor) {
2326	9fddaa0c	bellard	RET_PRIVREG(ctx);
2327	9fddaa0c	bellard	return;
2328	9a64fbe4	bellard	}
2329	9a64fbe4	bellard	gen_op_load_gpr_T0(rS(ctx->opcode));
2330	9a64fbe4	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
2331	9a64fbe4	bellard	gen_op_store_srin();
2332	9a64fbe4	bellard	#endif
2333	79aceca5	bellard	}
2334	79aceca5	bellard
2335	79aceca5	bellard	/* Lookaside buffer management */
2336	79aceca5	bellard	/* Optional & supervisor only: */
2337	79aceca5	bellard	/* tlbia */
2338	9a64fbe4	bellard	GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT)
2339	79aceca5	bellard	{
2340	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
2341	9fddaa0c	bellard	RET_PRIVOPC(ctx);
2342	9a64fbe4	bellard	#else
2343	9a64fbe4	bellard	if (!ctx->supervisor) {
2344	9fddaa0c	bellard	if (loglevel)
2345	9fddaa0c	bellard	fprintf(logfile, "%s: ! supervisor\n", __func__);
2346	9fddaa0c	bellard	RET_PRIVOPC(ctx);
2347	9fddaa0c	bellard	return;
2348	9a64fbe4	bellard	}
2349	9a64fbe4	bellard	gen_op_tlbia();
2350	4b3686fa	bellard	RET_MTMSR(ctx);
2351	9a64fbe4	bellard	#endif
2352	79aceca5	bellard	}
2353	79aceca5	bellard
2354	79aceca5	bellard	/* tlbie */
2355	9a64fbe4	bellard	GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
2356	79aceca5	bellard	{
2357	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
2358	9fddaa0c	bellard	RET_PRIVOPC(ctx);
2359	9a64fbe4	bellard	#else
2360	9a64fbe4	bellard	if (!ctx->supervisor) {
2361	9fddaa0c	bellard	RET_PRIVOPC(ctx);
2362	9fddaa0c	bellard	return;
2363	9a64fbe4	bellard	}
2364	9a64fbe4	bellard	gen_op_load_gpr_T0(rB(ctx->opcode));
2365	9a64fbe4	bellard	gen_op_tlbie();
2366	4b3686fa	bellard	RET_MTMSR(ctx);
2367	9a64fbe4	bellard	#endif
2368	79aceca5	bellard	}
2369	79aceca5	bellard
2370	79aceca5	bellard	/* tlbsync */
2371	e63c59cb	bellard	GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM)
2372	79aceca5	bellard	{
2373	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
2374	9fddaa0c	bellard	RET_PRIVOPC(ctx);
2375	9a64fbe4	bellard	#else
2376	9a64fbe4	bellard	if (!ctx->supervisor) {
2377	9fddaa0c	bellard	RET_PRIVOPC(ctx);
2378	9fddaa0c	bellard	return;
2379	9a64fbe4	bellard	}
2380	9a64fbe4	bellard	/* This has no effect: it should ensure that all previous
2381	9a64fbe4	bellard	* tlbie have completed
2382	9a64fbe4	bellard	*/
2383	4b3686fa	bellard	RET_MTMSR(ctx);
2384	9a64fbe4	bellard	#endif
2385	79aceca5	bellard	}
2386	79aceca5	bellard
2387	79aceca5	bellard	/* External control */
2388	79aceca5	bellard	/* Optional: */
2389	79aceca5	bellard	/* eciwx */
2390	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
2391	9a64fbe4	bellard	#define op_eciwx() gen_op_eciwx_raw()
2392	9a64fbe4	bellard	#define op_ecowx() gen_op_ecowx_raw()
2393	9a64fbe4	bellard	#else
2394	9a64fbe4	bellard	#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2395	9a64fbe4	bellard	#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
2396	9a64fbe4	bellard	static GenOpFunc *gen_op_eciwx[] = {
2397	9a64fbe4	bellard	&gen_op_eciwx_user,
2398	9a64fbe4	bellard	&gen_op_eciwx_kernel,
2399	9a64fbe4	bellard	};
2400	9a64fbe4	bellard	static GenOpFunc *gen_op_ecowx[] = {
2401	9a64fbe4	bellard	&gen_op_ecowx_user,
2402	9a64fbe4	bellard	&gen_op_ecowx_kernel,
2403	9a64fbe4	bellard	};
2404	9a64fbe4	bellard	#endif
2405	9a64fbe4	bellard
2406	79aceca5	bellard	GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2407	79aceca5	bellard	{
2408	9a64fbe4	bellard	/* Should check EAR[E] & alignment ! */
2409	9a64fbe4	bellard	if (rA(ctx->opcode) == 0) {
2410	9a64fbe4	bellard	gen_op_load_gpr_T0(rB(ctx->opcode));
2411	9a64fbe4	bellard	} else {
2412	9a64fbe4	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
2413	9a64fbe4	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
2414	9a64fbe4	bellard	gen_op_add();
2415	9a64fbe4	bellard	}
2416	9a64fbe4	bellard	op_eciwx();
2417	9a64fbe4	bellard	gen_op_store_T0_gpr(rD(ctx->opcode));
2418	79aceca5	bellard	}
2419	79aceca5	bellard
2420	79aceca5	bellard	/* ecowx */
2421	79aceca5	bellard	GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2422	79aceca5	bellard	{
2423	9a64fbe4	bellard	/* Should check EAR[E] & alignment ! */
2424	9a64fbe4	bellard	if (rA(ctx->opcode) == 0) {
2425	9a64fbe4	bellard	gen_op_load_gpr_T0(rB(ctx->opcode));
2426	9a64fbe4	bellard	} else {
2427	9a64fbe4	bellard	gen_op_load_gpr_T0(rA(ctx->opcode));
2428	9a64fbe4	bellard	gen_op_load_gpr_T1(rB(ctx->opcode));
2429	9a64fbe4	bellard	gen_op_add();
2430	9a64fbe4	bellard	}
2431	9a64fbe4	bellard	gen_op_load_gpr_T2(rS(ctx->opcode));
2432	9a64fbe4	bellard	op_ecowx();
2433	79aceca5	bellard	}
2434	79aceca5	bellard
2435	79aceca5	bellard	/* End opcode list */
2436	79aceca5	bellard	GEN_OPCODE_MARK(end);
2437	79aceca5	bellard
2438	79aceca5	bellard	/*****************************************************************************/
2439	9a64fbe4	bellard	#include <stdlib.h>
2440	79aceca5	bellard	#include <string.h>
2441	9a64fbe4	bellard
2442	9a64fbe4	bellard	int fflush (FILE *stream);
2443	79aceca5	bellard
2444	79aceca5	bellard	/* Main ppc opcodes table:
2445	79aceca5	bellard	* at init, all opcodes are invalids
2446	79aceca5	bellard	*/
2447	79aceca5	bellard	static opc_handler_t *ppc_opcodes[0x40];
2448	79aceca5	bellard
2449	79aceca5	bellard	/* Opcode types */
2450	79aceca5	bellard	enum {
2451	79aceca5	bellard	PPC_DIRECT = 0, /* Opcode routine */
2452	79aceca5	bellard	PPC_INDIRECT = 1, /* Indirect opcode table */
2453	79aceca5	bellard	};
2454	79aceca5	bellard
2455	79aceca5	bellard	static inline int is_indirect_opcode (void *handler)
2456	79aceca5	bellard	{
2457	79aceca5	bellard	return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2458	79aceca5	bellard	}
2459	79aceca5	bellard
2460	79aceca5	bellard	static inline opc_handler_t *ind_table(void handler)
2461	79aceca5	bellard	{
2462	79aceca5	bellard	return (opc_handler_t **)((unsigned long)handler & ~3);
2463	79aceca5	bellard	}
2464	79aceca5	bellard
2465	9a64fbe4	bellard	/* Instruction table creation */
2466	79aceca5	bellard	/* Opcodes tables creation */
2467	79aceca5	bellard	static void fill_new_table (opc_handler_t **table, int len)
2468	79aceca5	bellard	{
2469	79aceca5	bellard	int i;
2470	79aceca5	bellard
2471	79aceca5	bellard	for (i = 0; i < len; i++)
2472	79aceca5	bellard	table[i] = &invalid_handler;
2473	79aceca5	bellard	}
2474	79aceca5	bellard
2475	79aceca5	bellard	static int create_new_table (opc_handler_t **table, unsigned char idx)
2476	79aceca5	bellard	{
2477	79aceca5	bellard	opc_handler_t **tmp;
2478	79aceca5	bellard
2479	79aceca5	bellard	tmp = malloc(0x20 * sizeof(opc_handler_t));
2480	79aceca5	bellard	if (tmp == NULL)
2481	79aceca5	bellard	return -1;
2482	79aceca5	bellard	fill_new_table(tmp, 0x20);
2483	79aceca5	bellard	table[idx] = (opc_handler_t *)((unsigned long)tmp \| PPC_INDIRECT);
2484	79aceca5	bellard
2485	79aceca5	bellard	return 0;
2486	79aceca5	bellard	}
2487	79aceca5	bellard
2488	79aceca5	bellard	static int insert_in_table (opc_handler_t **table, unsigned char idx,
2489	79aceca5	bellard	opc_handler_t *handler)
2490	79aceca5	bellard	{
2491	79aceca5	bellard	if (table[idx] != &invalid_handler)
2492	79aceca5	bellard	return -1;
2493	79aceca5	bellard	table[idx] = handler;
2494	79aceca5	bellard
2495	79aceca5	bellard	return 0;
2496	79aceca5	bellard	}
2497	79aceca5	bellard
2498	9a64fbe4	bellard	static int register_direct_insn (opc_handler_t **ppc_opcodes,
2499	9a64fbe4	bellard	unsigned char idx, opc_handler_t *handler)
2500	79aceca5	bellard	{
2501	79aceca5	bellard	if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
2502	9a64fbe4	bellard	printf("*** ERROR: opcode %02x already assigned in main "
2503	79aceca5	bellard	"opcode table\n", idx);
2504	79aceca5	bellard	return -1;
2505	79aceca5	bellard	}
2506	79aceca5	bellard
2507	79aceca5	bellard	return 0;
2508	79aceca5	bellard	}
2509	79aceca5	bellard
2510	79aceca5	bellard	static int register_ind_in_table (opc_handler_t **table,
2511	79aceca5	bellard	unsigned char idx1, unsigned char idx2,
2512	79aceca5	bellard	opc_handler_t *handler)
2513	79aceca5	bellard	{
2514	79aceca5	bellard	if (table[idx1] == &invalid_handler) {
2515	79aceca5	bellard	if (create_new_table(table, idx1) < 0) {
2516	9a64fbe4	bellard	printf("*** ERROR: unable to create indirect table "
2517	79aceca5	bellard	"idx=%02x\n", idx1);
2518	79aceca5	bellard	return -1;
2519	79aceca5	bellard	}
2520	79aceca5	bellard	} else {
2521	79aceca5	bellard	if (!is_indirect_opcode(table[idx1])) {
2522	9a64fbe4	bellard	printf("*** ERROR: idx %02x already assigned to a direct "
2523	79aceca5	bellard	"opcode\n", idx1);
2524	79aceca5	bellard	return -1;
2525	79aceca5	bellard	}
2526	79aceca5	bellard	}
2527	79aceca5	bellard	if (handler != NULL &&
2528	79aceca5	bellard	insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
2529	9a64fbe4	bellard	printf("*** ERROR: opcode %02x already assigned in "
2530	79aceca5	bellard	"opcode table %02x\n", idx2, idx1);
2531	79aceca5	bellard	return -1;
2532	79aceca5	bellard	}
2533	79aceca5	bellard
2534	79aceca5	bellard	return 0;
2535	79aceca5	bellard	}
2536	79aceca5	bellard
2537	9a64fbe4	bellard	static int register_ind_insn (opc_handler_t **ppc_opcodes,
2538	9a64fbe4	bellard	unsigned char idx1, unsigned char idx2,
2539	79aceca5	bellard	opc_handler_t *handler)
2540	79aceca5	bellard	{
2541	79aceca5	bellard	int ret;
2542	79aceca5	bellard
2543	79aceca5	bellard	ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2544	79aceca5	bellard
2545	79aceca5	bellard	return ret;
2546	79aceca5	bellard	}
2547	79aceca5	bellard
2548	9a64fbe4	bellard	static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2549	9a64fbe4	bellard	unsigned char idx1, unsigned char idx2,
2550	79aceca5	bellard	unsigned char idx3, opc_handler_t *handler)
2551	79aceca5	bellard	{
2552	79aceca5	bellard	if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
2553	9a64fbe4	bellard	printf("*** ERROR: unable to join indirect table idx "
2554	79aceca5	bellard	"[%02x-%02x]\n", idx1, idx2);
2555	79aceca5	bellard	return -1;
2556	79aceca5	bellard	}
2557	79aceca5	bellard	if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2558	79aceca5	bellard	handler) < 0) {
2559	9a64fbe4	bellard	printf("*** ERROR: unable to insert opcode "
2560	79aceca5	bellard	"[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2561	79aceca5	bellard	return -1;
2562	79aceca5	bellard	}
2563	79aceca5	bellard
2564	79aceca5	bellard	return 0;
2565	79aceca5	bellard	}
2566	79aceca5	bellard
2567	9a64fbe4	bellard	static int register_insn (opc_handler_t *ppc_opcodes, opcode_t insn)
2568	79aceca5	bellard	{
2569	79aceca5	bellard	if (insn->opc2 != 0xFF) {
2570	79aceca5	bellard	if (insn->opc3 != 0xFF) {
2571	9a64fbe4	bellard	if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2572	9a64fbe4	bellard	insn->opc3, &insn->handler) < 0)
2573	79aceca5	bellard	return -1;
2574	79aceca5	bellard	} else {
2575	9a64fbe4	bellard	if (register_ind_insn(ppc_opcodes, insn->opc1,
2576	9a64fbe4	bellard	insn->opc2, &insn->handler) < 0)
2577	79aceca5	bellard	return -1;
2578	79aceca5	bellard	}
2579	79aceca5	bellard	} else {
2580	9a64fbe4	bellard	if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
2581	79aceca5	bellard	return -1;
2582	79aceca5	bellard	}
2583	79aceca5	bellard
2584	79aceca5	bellard	return 0;
2585	79aceca5	bellard	}
2586	79aceca5	bellard
2587	79aceca5	bellard	static int test_opcode_table (opc_handler_t **table, int len)
2588	79aceca5	bellard	{
2589	79aceca5	bellard	int i, count, tmp;
2590	79aceca5	bellard
2591	79aceca5	bellard	for (i = 0, count = 0; i < len; i++) {
2592	79aceca5	bellard	/* Consistency fixup */
2593	79aceca5	bellard	if (table[i] == NULL)
2594	79aceca5	bellard	table[i] = &invalid_handler;
2595	79aceca5	bellard	if (table[i] != &invalid_handler) {
2596	79aceca5	bellard	if (is_indirect_opcode(table[i])) {
2597	79aceca5	bellard	tmp = test_opcode_table(ind_table(table[i]), 0x20);
2598	79aceca5	bellard	if (tmp == 0) {
2599	79aceca5	bellard	free(table[i]);
2600	79aceca5	bellard	table[i] = &invalid_handler;
2601	79aceca5	bellard	} else {
2602	79aceca5	bellard	count++;
2603	79aceca5	bellard	}
2604	79aceca5	bellard	} else {
2605	79aceca5	bellard	count++;
2606	79aceca5	bellard	}
2607	79aceca5	bellard	}
2608	79aceca5	bellard	}
2609	79aceca5	bellard
2610	79aceca5	bellard	return count;
2611	79aceca5	bellard	}
2612	79aceca5	bellard
2613	9a64fbe4	bellard	static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
2614	79aceca5	bellard	{
2615	79aceca5	bellard	if (test_opcode_table(ppc_opcodes, 0x40) == 0)
2616	9a64fbe4	bellard	printf("*** WARNING: no opcode defined !\n");
2617	79aceca5	bellard	}
2618	79aceca5	bellard
2619	9a64fbe4	bellard	#define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw)))
2620	79aceca5	bellard	#define SPR_UR SPR_RIGHTS(0, 0)
2621	79aceca5	bellard	#define SPR_UW SPR_RIGHTS(1, 0)
2622	79aceca5	bellard	#define SPR_SR SPR_RIGHTS(0, 1)
2623	79aceca5	bellard	#define SPR_SW SPR_RIGHTS(1, 1)
2624	79aceca5	bellard
2625	79aceca5	bellard	#define spr_set_rights(spr, rights) \
2626	79aceca5	bellard	do { \
2627	79aceca5	bellard	spr_access[(spr) >> 1] \|= ((rights) << (4 * ((spr) & 1))); \
2628	79aceca5	bellard	} while (0)
2629	79aceca5	bellard
2630	9a64fbe4	bellard	static void init_spr_rights (uint32_t pvr)
2631	79aceca5	bellard	{
2632	79aceca5	bellard	/* XER (SPR 1) */
2633	9a64fbe4	bellard	spr_set_rights(XER, SPR_UR \| SPR_UW \| SPR_SR \| SPR_SW);
2634	79aceca5	bellard	/* LR (SPR 8) */
2635	9a64fbe4	bellard	spr_set_rights(LR, SPR_UR \| SPR_UW \| SPR_SR \| SPR_SW);
2636	79aceca5	bellard	/* CTR (SPR 9) */
2637	9a64fbe4	bellard	spr_set_rights(CTR, SPR_UR \| SPR_UW \| SPR_SR \| SPR_SW);
2638	79aceca5	bellard	/* TBL (SPR 268) */
2639	9a64fbe4	bellard	spr_set_rights(V_TBL, SPR_UR \| SPR_SR);
2640	79aceca5	bellard	/* TBU (SPR 269) */
2641	9a64fbe4	bellard	spr_set_rights(V_TBU, SPR_UR \| SPR_SR);
2642	79aceca5	bellard	/* DSISR (SPR 18) */
2643	9a64fbe4	bellard	spr_set_rights(DSISR, SPR_SR \| SPR_SW);
2644	79aceca5	bellard	/* DAR (SPR 19) */
2645	9a64fbe4	bellard	spr_set_rights(DAR, SPR_SR \| SPR_SW);
2646	79aceca5	bellard	/* DEC (SPR 22) */
2647	9a64fbe4	bellard	spr_set_rights(DECR, SPR_SR \| SPR_SW);
2648	79aceca5	bellard	/* SDR1 (SPR 25) */
2649	9a64fbe4	bellard	spr_set_rights(SDR1, SPR_SR \| SPR_SW);
2650	9a64fbe4	bellard	/* SRR0 (SPR 26) */
2651	9a64fbe4	bellard	spr_set_rights(SRR0, SPR_SR \| SPR_SW);
2652	9a64fbe4	bellard	/* SRR1 (SPR 27) */
2653	9a64fbe4	bellard	spr_set_rights(SRR1, SPR_SR \| SPR_SW);
2654	79aceca5	bellard	/* SPRG0 (SPR 272) */
2655	9a64fbe4	bellard	spr_set_rights(SPRG0, SPR_SR \| SPR_SW);
2656	79aceca5	bellard	/* SPRG1 (SPR 273) */
2657	9a64fbe4	bellard	spr_set_rights(SPRG1, SPR_SR \| SPR_SW);
2658	79aceca5	bellard	/* SPRG2 (SPR 274) */
2659	9a64fbe4	bellard	spr_set_rights(SPRG2, SPR_SR \| SPR_SW);
2660	79aceca5	bellard	/* SPRG3 (SPR 275) */
2661	9a64fbe4	bellard	spr_set_rights(SPRG3, SPR_SR \| SPR_SW);
2662	79aceca5	bellard	/* ASR (SPR 280) */
2663	9a64fbe4	bellard	spr_set_rights(ASR, SPR_SR \| SPR_SW);
2664	79aceca5	bellard	/* EAR (SPR 282) */
2665	9a64fbe4	bellard	spr_set_rights(EAR, SPR_SR \| SPR_SW);
2666	9a64fbe4	bellard	/* TBL (SPR 284) */
2667	9a64fbe4	bellard	spr_set_rights(O_TBL, SPR_SW);
2668	9a64fbe4	bellard	/* TBU (SPR 285) */
2669	9a64fbe4	bellard	spr_set_rights(O_TBU, SPR_SW);
2670	9a64fbe4	bellard	/* PVR (SPR 287) */
2671	9a64fbe4	bellard	spr_set_rights(PVR, SPR_SR);
2672	79aceca5	bellard	/* IBAT0U (SPR 528) */
2673	9a64fbe4	bellard	spr_set_rights(IBAT0U, SPR_SR \| SPR_SW);
2674	79aceca5	bellard	/* IBAT0L (SPR 529) */
2675	9a64fbe4	bellard	spr_set_rights(IBAT0L, SPR_SR \| SPR_SW);
2676	79aceca5	bellard	/* IBAT1U (SPR 530) */
2677	9a64fbe4	bellard	spr_set_rights(IBAT1U, SPR_SR \| SPR_SW);
2678	79aceca5	bellard	/* IBAT1L (SPR 531) */
2679	9a64fbe4	bellard	spr_set_rights(IBAT1L, SPR_SR \| SPR_SW);
2680	79aceca5	bellard	/* IBAT2U (SPR 532) */
2681	9a64fbe4	bellard	spr_set_rights(IBAT2U, SPR_SR \| SPR_SW);
2682	79aceca5	bellard	/* IBAT2L (SPR 533) */
2683	9a64fbe4	bellard	spr_set_rights(IBAT2L, SPR_SR \| SPR_SW);
2684	79aceca5	bellard	/* IBAT3U (SPR 534) */
2685	9a64fbe4	bellard	spr_set_rights(IBAT3U, SPR_SR \| SPR_SW);
2686	79aceca5	bellard	/* IBAT3L (SPR 535) */
2687	9a64fbe4	bellard	spr_set_rights(IBAT3L, SPR_SR \| SPR_SW);
2688	79aceca5	bellard	/* DBAT0U (SPR 536) */
2689	9a64fbe4	bellard	spr_set_rights(DBAT0U, SPR_SR \| SPR_SW);
2690	79aceca5	bellard	/* DBAT0L (SPR 537) */
2691	9a64fbe4	bellard	spr_set_rights(DBAT0L, SPR_SR \| SPR_SW);
2692	79aceca5	bellard	/* DBAT1U (SPR 538) */
2693	9a64fbe4	bellard	spr_set_rights(DBAT1U, SPR_SR \| SPR_SW);
2694	79aceca5	bellard	/* DBAT1L (SPR 539) */
2695	9a64fbe4	bellard	spr_set_rights(DBAT1L, SPR_SR \| SPR_SW);
2696	79aceca5	bellard	/* DBAT2U (SPR 540) */
2697	9a64fbe4	bellard	spr_set_rights(DBAT2U, SPR_SR \| SPR_SW);
2698	79aceca5	bellard	/* DBAT2L (SPR 541) */
2699	9a64fbe4	bellard	spr_set_rights(DBAT2L, SPR_SR \| SPR_SW);
2700	79aceca5	bellard	/* DBAT3U (SPR 542) */
2701	9a64fbe4	bellard	spr_set_rights(DBAT3U, SPR_SR \| SPR_SW);
2702	79aceca5	bellard	/* DBAT3L (SPR 543) */
2703	9a64fbe4	bellard	spr_set_rights(DBAT3L, SPR_SR \| SPR_SW);
2704	79aceca5	bellard	/* FPECR (SPR 1022) */
2705	9a64fbe4	bellard	spr_set_rights(FPECR, SPR_SR \| SPR_SW);
2706	4b3686fa	bellard	/* Special registers for PPC 604 */
2707	4b3686fa	bellard	if ((pvr & 0xFFFF0000) == 0x00040000) {
2708	4b3686fa	bellard	/* IABR */
2709	4b3686fa	bellard	spr_set_rights(IABR , SPR_SR \| SPR_SW);
2710	4b3686fa	bellard	/* DABR (SPR 1013) */
2711	4b3686fa	bellard	spr_set_rights(DABR, SPR_SR \| SPR_SW);
2712	4b3686fa	bellard	/* HID0 */
2713	4b3686fa	bellard	spr_set_rights(HID0, SPR_SR \| SPR_SW);
2714	4b3686fa	bellard	/* PIR */
2715	9a64fbe4	bellard	spr_set_rights(PIR, SPR_SR \| SPR_SW);
2716	4b3686fa	bellard	/* PMC1 */
2717	4b3686fa	bellard	spr_set_rights(PMC1, SPR_SR \| SPR_SW);
2718	4b3686fa	bellard	/* PMC2 */
2719	4b3686fa	bellard	spr_set_rights(PMC2, SPR_SR \| SPR_SW);
2720	4b3686fa	bellard	/* MMCR0 */
2721	4b3686fa	bellard	spr_set_rights(MMCR0, SPR_SR \| SPR_SW);
2722	4b3686fa	bellard	/* SIA */
2723	4b3686fa	bellard	spr_set_rights(SIA, SPR_SR \| SPR_SW);
2724	4b3686fa	bellard	/* SDA */
2725	4b3686fa	bellard	spr_set_rights(SDA, SPR_SR \| SPR_SW);
2726	4b3686fa	bellard	}
2727	9a64fbe4	bellard	/* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */
2728	9a64fbe4	bellard	if ((pvr & 0xFFFF0000) == 0x00080000 \|\|
2729	9a64fbe4	bellard	(pvr & 0xFFFF0000) == 0x70000000) {
2730	9a64fbe4	bellard	/* HID0 */
2731	4b3686fa	bellard	spr_set_rights(HID0, SPR_SR \| SPR_SW);
2732	9a64fbe4	bellard	/* HID1 */
2733	4b3686fa	bellard	spr_set_rights(HID1, SPR_SR \| SPR_SW);
2734	9a64fbe4	bellard	/* IABR */
2735	4b3686fa	bellard	spr_set_rights(IABR, SPR_SR \| SPR_SW);
2736	9a64fbe4	bellard	/* ICTC */
2737	4b3686fa	bellard	spr_set_rights(ICTC, SPR_SR \| SPR_SW);
2738	9a64fbe4	bellard	/* L2CR */
2739	4b3686fa	bellard	spr_set_rights(L2CR, SPR_SR \| SPR_SW);
2740	9a64fbe4	bellard	/* MMCR0 */
2741	4b3686fa	bellard	spr_set_rights(MMCR0, SPR_SR \| SPR_SW);
2742	9a64fbe4	bellard	/* MMCR1 */
2743	4b3686fa	bellard	spr_set_rights(MMCR1, SPR_SR \| SPR_SW);
2744	9a64fbe4	bellard	/* PMC1 */
2745	4b3686fa	bellard	spr_set_rights(PMC1, SPR_SR \| SPR_SW);
2746	9a64fbe4	bellard	/* PMC2 */
2747	4b3686fa	bellard	spr_set_rights(PMC2, SPR_SR \| SPR_SW);
2748	9a64fbe4	bellard	/* PMC3 */
2749	4b3686fa	bellard	spr_set_rights(PMC3, SPR_SR \| SPR_SW);
2750	9a64fbe4	bellard	/* PMC4 */
2751	4b3686fa	bellard	spr_set_rights(PMC4, SPR_SR \| SPR_SW);
2752	9a64fbe4	bellard	/* SIA */
2753	4b3686fa	bellard	spr_set_rights(SIA, SPR_SR \| SPR_SW);
2754	4b3686fa	bellard	/* SDA */
2755	4b3686fa	bellard	spr_set_rights(SDA, SPR_SR \| SPR_SW);
2756	9a64fbe4	bellard	/* THRM1 */
2757	4b3686fa	bellard	spr_set_rights(THRM1, SPR_SR \| SPR_SW);
2758	9a64fbe4	bellard	/* THRM2 */
2759	4b3686fa	bellard	spr_set_rights(THRM2, SPR_SR \| SPR_SW);
2760	9a64fbe4	bellard	/* THRM3 */
2761	4b3686fa	bellard	spr_set_rights(THRM3, SPR_SR \| SPR_SW);
2762	9a64fbe4	bellard	/* UMMCR0 */
2763	4b3686fa	bellard	spr_set_rights(UMMCR0, SPR_UR \| SPR_UW);
2764	9a64fbe4	bellard	/* UMMCR1 */
2765	4b3686fa	bellard	spr_set_rights(UMMCR1, SPR_UR \| SPR_UW);
2766	9a64fbe4	bellard	/* UPMC1 */
2767	4b3686fa	bellard	spr_set_rights(UPMC1, SPR_UR \| SPR_UW);
2768	9a64fbe4	bellard	/* UPMC2 */
2769	4b3686fa	bellard	spr_set_rights(UPMC2, SPR_UR \| SPR_UW);
2770	9a64fbe4	bellard	/* UPMC3 */
2771	4b3686fa	bellard	spr_set_rights(UPMC3, SPR_UR \| SPR_UW);
2772	9a64fbe4	bellard	/* UPMC4 */
2773	4b3686fa	bellard	spr_set_rights(UPMC4, SPR_UR \| SPR_UW);
2774	9a64fbe4	bellard	/* USIA */
2775	4b3686fa	bellard	spr_set_rights(USIA, SPR_UR \| SPR_UW);
2776	9a64fbe4	bellard	}
2777	9a64fbe4	bellard	/* MPC755 has special registers */
2778	9a64fbe4	bellard	if (pvr == 0x00083100) {
2779	9a64fbe4	bellard	/* SPRG4 */
2780	9a64fbe4	bellard	spr_set_rights(SPRG4, SPR_SR \| SPR_SW);
2781	9a64fbe4	bellard	/* SPRG5 */
2782	9a64fbe4	bellard	spr_set_rights(SPRG5, SPR_SR \| SPR_SW);
2783	9a64fbe4	bellard	/* SPRG6 */
2784	9a64fbe4	bellard	spr_set_rights(SPRG6, SPR_SR \| SPR_SW);
2785	9a64fbe4	bellard	/* SPRG7 */
2786	9a64fbe4	bellard	spr_set_rights(SPRG7, SPR_SR \| SPR_SW);
2787	9a64fbe4	bellard	/* IBAT4U */
2788	9a64fbe4	bellard	spr_set_rights(IBAT4U, SPR_SR \| SPR_SW);
2789	9a64fbe4	bellard	/* IBAT4L */
2790	9a64fbe4	bellard	spr_set_rights(IBAT4L, SPR_SR \| SPR_SW);
2791	9a64fbe4	bellard	/* IBAT5U */
2792	9a64fbe4	bellard	spr_set_rights(IBAT5U, SPR_SR \| SPR_SW);
2793	9a64fbe4	bellard	/* IBAT5L */
2794	9a64fbe4	bellard	spr_set_rights(IBAT5L, SPR_SR \| SPR_SW);
2795	9a64fbe4	bellard	/* IBAT6U */
2796	9a64fbe4	bellard	spr_set_rights(IBAT6U, SPR_SR \| SPR_SW);
2797	9a64fbe4	bellard	/* IBAT6L */
2798	9a64fbe4	bellard	spr_set_rights(IBAT6L, SPR_SR \| SPR_SW);
2799	9a64fbe4	bellard	/* IBAT7U */
2800	9a64fbe4	bellard	spr_set_rights(IBAT7U, SPR_SR \| SPR_SW);
2801	9a64fbe4	bellard	/* IBAT7L */
2802	9a64fbe4	bellard	spr_set_rights(IBAT7L, SPR_SR \| SPR_SW);
2803	9a64fbe4	bellard	/* DBAT4U */
2804	9a64fbe4	bellard	spr_set_rights(DBAT4U, SPR_SR \| SPR_SW);
2805	9a64fbe4	bellard	/* DBAT4L */
2806	9a64fbe4	bellard	spr_set_rights(DBAT4L, SPR_SR \| SPR_SW);
2807	9a64fbe4	bellard	/* DBAT5U */
2808	9a64fbe4	bellard	spr_set_rights(DBAT5U, SPR_SR \| SPR_SW);
2809	9a64fbe4	bellard	/* DBAT5L */
2810	9a64fbe4	bellard	spr_set_rights(DBAT5L, SPR_SR \| SPR_SW);
2811	9a64fbe4	bellard	/* DBAT6U */
2812	9a64fbe4	bellard	spr_set_rights(DBAT6U, SPR_SR \| SPR_SW);
2813	9a64fbe4	bellard	/* DBAT6L */
2814	9a64fbe4	bellard	spr_set_rights(DBAT6L, SPR_SR \| SPR_SW);
2815	9a64fbe4	bellard	/* DBAT7U */
2816	9a64fbe4	bellard	spr_set_rights(DBAT7U, SPR_SR \| SPR_SW);
2817	9a64fbe4	bellard	/* DBAT7L */
2818	9a64fbe4	bellard	spr_set_rights(DBAT7L, SPR_SR \| SPR_SW);
2819	9a64fbe4	bellard	/* DMISS */
2820	4b3686fa	bellard	spr_set_rights(DMISS, SPR_SR \| SPR_SW);
2821	9a64fbe4	bellard	/* DCMP */
2822	4b3686fa	bellard	spr_set_rights(DCMP, SPR_SR \| SPR_SW);
2823	9a64fbe4	bellard	/* DHASH1 */
2824	4b3686fa	bellard	spr_set_rights(DHASH1, SPR_SR \| SPR_SW);
2825	9a64fbe4	bellard	/* DHASH2 */
2826	4b3686fa	bellard	spr_set_rights(DHASH2, SPR_SR \| SPR_SW);
2827	9a64fbe4	bellard	/* IMISS */
2828	4b3686fa	bellard	spr_set_rights(IMISS, SPR_SR \| SPR_SW);
2829	9a64fbe4	bellard	/* ICMP */
2830	4b3686fa	bellard	spr_set_rights(ICMP, SPR_SR \| SPR_SW);
2831	9a64fbe4	bellard	/* RPA */
2832	4b3686fa	bellard	spr_set_rights(RPA, SPR_SR \| SPR_SW);
2833	9a64fbe4	bellard	/* HID2 */
2834	4b3686fa	bellard	spr_set_rights(HID2, SPR_SR \| SPR_SW);
2835	9a64fbe4	bellard	/* L2PM */
2836	4b3686fa	bellard	spr_set_rights(L2PM, SPR_SR \| SPR_SW);
2837	9a64fbe4	bellard	}
2838	79aceca5	bellard	}
2839	79aceca5	bellard
2840	9a64fbe4	bellard	/*****************************************************************************/
2841	9a64fbe4	bellard	/* PPC "main stream" common instructions (no optional ones) */
2842	79aceca5	bellard
2843	79aceca5	bellard	typedef struct ppc_proc_t {
2844	79aceca5	bellard	int flags;
2845	79aceca5	bellard	void *specific;
2846	79aceca5	bellard	} ppc_proc_t;
2847	79aceca5	bellard
2848	79aceca5	bellard	typedef struct ppc_def_t {
2849	79aceca5	bellard	unsigned long pvr;
2850	79aceca5	bellard	unsigned long pvr_mask;
2851	79aceca5	bellard	ppc_proc_t *proc;
2852	79aceca5	bellard	} ppc_def_t;
2853	79aceca5	bellard
2854	79aceca5	bellard	static ppc_proc_t ppc_proc_common = {
2855	79aceca5	bellard	.flags = PPC_COMMON,
2856	79aceca5	bellard	.specific = NULL,
2857	79aceca5	bellard	};
2858	79aceca5	bellard
2859	9a64fbe4	bellard	static ppc_proc_t ppc_proc_G3 = {
2860	9a64fbe4	bellard	.flags = PPC_750,
2861	9a64fbe4	bellard	.specific = NULL,
2862	9a64fbe4	bellard	};
2863	9a64fbe4	bellard
2864	79aceca5	bellard	static ppc_def_t ppc_defs[] =
2865	79aceca5	bellard	{
2866	9a64fbe4	bellard	/* MPC740/745/750/755 (G3) */
2867	9a64fbe4	bellard	{
2868	9a64fbe4	bellard	.pvr = 0x00080000,
2869	9a64fbe4	bellard	.pvr_mask = 0xFFFF0000,
2870	9a64fbe4	bellard	.proc = &ppc_proc_G3,
2871	9a64fbe4	bellard	},
2872	9a64fbe4	bellard	/* IBM 750FX (G3 embedded) */
2873	9a64fbe4	bellard	{
2874	9a64fbe4	bellard	.pvr = 0x70000000,
2875	9a64fbe4	bellard	.pvr_mask = 0xFFFF0000,
2876	9a64fbe4	bellard	.proc = &ppc_proc_G3,
2877	9a64fbe4	bellard	},
2878	9a64fbe4	bellard	/* Fallback (generic PPC) */
2879	79aceca5	bellard	{
2880	79aceca5	bellard	.pvr = 0x00000000,
2881	79aceca5	bellard	.pvr_mask = 0x00000000,
2882	79aceca5	bellard	.proc = &ppc_proc_common,
2883	79aceca5	bellard	},
2884	79aceca5	bellard	};
2885	79aceca5	bellard
2886	9a64fbe4	bellard	static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr)
2887	79aceca5	bellard	{
2888	79aceca5	bellard	opcode_t *opc;
2889	79aceca5	bellard	int i, flags;
2890	79aceca5	bellard
2891	79aceca5	bellard	fill_new_table(ppc_opcodes, 0x40);
2892	79aceca5	bellard	for (i = 0; ; i++) {
2893	79aceca5	bellard	if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) ==
2894	79aceca5	bellard	(pvr & ppc_defs[i].pvr_mask)) {
2895	79aceca5	bellard	flags = ppc_defs[i].proc->flags;
2896	79aceca5	bellard	break;
2897	79aceca5	bellard	}
2898	79aceca5	bellard	}
2899	79aceca5	bellard
2900	79aceca5	bellard	for (opc = &opc_start + 1; opc != &opc_end; opc++) {
2901	9a64fbe4	bellard	if ((opc->handler.type & flags) != 0)
2902	9a64fbe4	bellard	if (register_insn(ppc_opcodes, opc) < 0) {
2903	9a64fbe4	bellard	printf("*** ERROR initializing PPC instruction "
2904	79aceca5	bellard	"0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2905	79aceca5	bellard	opc->opc3);
2906	79aceca5	bellard	return -1;
2907	79aceca5	bellard	}
2908	79aceca5	bellard	}
2909	9a64fbe4	bellard	fix_opcode_tables(ppc_opcodes);
2910	79aceca5	bellard
2911	79aceca5	bellard	return 0;
2912	79aceca5	bellard	}
2913	79aceca5	bellard
2914	9a64fbe4	bellard
2915	79aceca5	bellard	/*****************************************************************************/
2916	9a64fbe4	bellard	/* Misc PPC helpers */
2917	79aceca5	bellard
2918	79aceca5	bellard	void cpu_ppc_dump_state(CPUPPCState env, FILE f, int flags)
2919	79aceca5	bellard	{
2920	79aceca5	bellard	int i;
2921	79aceca5	bellard
2922	9a64fbe4	bellard	fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x "
2923	9a64fbe4	bellard	"MSR=0x%08x\n", env->nip, env->lr, env->ctr,
2924	a541f297	bellard	_load_xer(env), _load_msr(env));
2925	79aceca5	bellard	for (i = 0; i < 32; i++) {
2926	79aceca5	bellard	if ((i & 7) == 0)
2927	9a64fbe4	bellard	fprintf(f, "GPR%02d:", i);
2928	9a64fbe4	bellard	fprintf(f, " %08x", env->gpr[i]);
2929	79aceca5	bellard	if ((i & 7) == 7)
2930	9a64fbe4	bellard	fprintf(f, "\n");
2931	79aceca5	bellard	}
2932	9a64fbe4	bellard	fprintf(f, "CR: 0x");
2933	79aceca5	bellard	for (i = 0; i < 8; i++)
2934	9a64fbe4	bellard	fprintf(f, "%01x", env->crf[i]);
2935	9a64fbe4	bellard	fprintf(f, " [");
2936	79aceca5	bellard	for (i = 0; i < 8; i++) {
2937	79aceca5	bellard	char a = '-';
2938	79aceca5	bellard	if (env->crf[i] & 0x08)
2939	79aceca5	bellard	a = 'L';
2940	79aceca5	bellard	else if (env->crf[i] & 0x04)
2941	79aceca5	bellard	a = 'G';
2942	79aceca5	bellard	else if (env->crf[i] & 0x02)
2943	79aceca5	bellard	a = 'E';
2944	9a64fbe4	bellard	fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
2945	79aceca5	bellard	}
2946	9a64fbe4	bellard	fprintf(f, " ] ");
2947	9fddaa0c	bellard	fprintf(f, "TB: 0x%08x %08x\n", cpu_ppc_load_tbu(env),
2948	9fddaa0c	bellard	cpu_ppc_load_tbl(env));
2949	79aceca5	bellard	for (i = 0; i < 16; i++) {
2950	79aceca5	bellard	if ((i & 3) == 0)
2951	9a64fbe4	bellard	fprintf(f, "FPR%02d:", i);
2952	9a64fbe4	bellard	fprintf(f, " %016llx", ((uint64_t )&env->fpr[i]));
2953	79aceca5	bellard	if ((i & 3) == 3)
2954	9a64fbe4	bellard	fprintf(f, "\n");
2955	79aceca5	bellard	}
2956	9fddaa0c	bellard	fprintf(f, "SRR0 0x%08x SRR1 0x%08x DECR=0x%08x\n",
2957	9fddaa0c	bellard	env->spr[SRR0], env->spr[SRR1], cpu_ppc_load_decr(env));
2958	9a64fbe4	bellard	fprintf(f, "reservation 0x%08x\n", env->reserve);
2959	9a64fbe4	bellard	fflush(f);
2960	79aceca5	bellard	}
2961	79aceca5	bellard
2962	9a64fbe4	bellard	#if !defined(CONFIG_USER_ONLY) && defined (USE_OPENFIRMWARE)
2963	9a64fbe4	bellard	int setup_machine (CPUPPCState *env, uint32_t mid);
2964	9a64fbe4	bellard	#endif
2965	9a64fbe4	bellard
2966	79aceca5	bellard	CPUPPCState *cpu_ppc_init(void)
2967	79aceca5	bellard	{
2968	79aceca5	bellard	CPUPPCState *env;
2969	79aceca5	bellard
2970	79aceca5	bellard	cpu_exec_init();
2971	79aceca5	bellard
2972	4b3686fa	bellard	env = qemu_mallocz(sizeof(CPUPPCState));
2973	79aceca5	bellard	if (!env)
2974	79aceca5	bellard	return NULL;
2975	9a64fbe4	bellard	#if !defined(CONFIG_USER_ONLY) && defined (USE_OPEN_FIRMWARE)
2976	9a64fbe4	bellard	setup_machine(env, 0);
2977	9a64fbe4	bellard	#else
2978	9a64fbe4	bellard	// env->spr[PVR] = 0; /* Basic PPC */
2979	9a64fbe4	bellard	env->spr[PVR] = 0x00080100; /* G3 CPU */
2980	9a64fbe4	bellard	// env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */
2981	9a64fbe4	bellard	// env->spr[PVR] = 0x00070100; /* IBM 750FX */
2982	9a64fbe4	bellard	#endif
2983	ad081323	bellard	tlb_flush(env, 1);
2984	9a64fbe4	bellard	#if defined (DO_SINGLE_STEP)
2985	9a64fbe4	bellard	/* Single step trace mode */
2986	9a64fbe4	bellard	msr_se = 1;
2987	9a64fbe4	bellard	#endif
2988	4b3686fa	bellard	msr_fp = 1; /* Allow floating point exceptions */
2989	4b3686fa	bellard	msr_me = 1; /* Allow machine check exceptions */
2990	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
2991	9a64fbe4	bellard	msr_pr = 1;
2992	4b3686fa	bellard	cpu_ppc_register(env, 0x00080000);
2993	4b3686fa	bellard	#else
2994	4b3686fa	bellard	env->nip = 0xFFFFFFFC;
2995	9a64fbe4	bellard	#endif
2996	a541f297	bellard	env->access_type = ACCESS_INT;
2997	79aceca5	bellard
2998	79aceca5	bellard	return env;
2999	79aceca5	bellard	}
3000	79aceca5	bellard
3001	4b3686fa	bellard	int cpu_ppc_register (CPUPPCState *env, uint32_t pvr)
3002	4b3686fa	bellard	{
3003	4b3686fa	bellard	env->spr[PVR] = pvr;
3004	4b3686fa	bellard	if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0)
3005	4b3686fa	bellard	return -1;
3006	4b3686fa	bellard	init_spr_rights(env->spr[PVR]);
3007	4b3686fa	bellard
3008	4b3686fa	bellard	return 0;
3009	4b3686fa	bellard	}
3010	4b3686fa	bellard
3011	79aceca5	bellard	void cpu_ppc_close(CPUPPCState *env)
3012	79aceca5	bellard	{
3013	79aceca5	bellard	/* Should also remove all opcode tables... */
3014	79aceca5	bellard	free(env);
3015	79aceca5	bellard	}
3016	79aceca5	bellard
3017	9a64fbe4	bellard	/*****************************************************************************/
3018	9a64fbe4	bellard	int print_insn_powerpc (FILE *out, unsigned long insn, unsigned memaddr,
3019	9a64fbe4	bellard	int dialect);
3020	9a64fbe4	bellard
3021	79aceca5	bellard	int gen_intermediate_code_internal (CPUState env, TranslationBlock tb,
3022	79aceca5	bellard	int search_pc)
3023	79aceca5	bellard	{
3024	9fddaa0c	bellard	DisasContext ctx, *ctxp = &ctx;
3025	79aceca5	bellard	opc_handler_t *table, handler;
3026	79aceca5	bellard	uint32_t pc_start;
3027	79aceca5	bellard	uint16_t *gen_opc_end;
3028	79aceca5	bellard	int j, lj = -1;
3029	79aceca5	bellard
3030	79aceca5	bellard	pc_start = tb->pc;
3031	79aceca5	bellard	gen_opc_ptr = gen_opc_buf;
3032	79aceca5	bellard	gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3033	79aceca5	bellard	gen_opparam_ptr = gen_opparam_buf;
3034	046d6672	bellard	ctx.nip = pc_start;
3035	79aceca5	bellard	ctx.tb = tb;
3036	9a64fbe4	bellard	ctx.exception = EXCP_NONE;
3037	9a64fbe4	bellard	#if defined(CONFIG_USER_ONLY)
3038	9a64fbe4	bellard	ctx.mem_idx = 0;
3039	9a64fbe4	bellard	#else
3040	9a64fbe4	bellard	ctx.supervisor = 1 - msr_pr;
3041	9a64fbe4	bellard	ctx.mem_idx = (1 - msr_pr);
3042	9a64fbe4	bellard	#endif
3043	9a64fbe4	bellard	#if defined (DO_SINGLE_STEP)
3044	9a64fbe4	bellard	/* Single step trace mode */
3045	9a64fbe4	bellard	msr_se = 1;
3046	9a64fbe4	bellard	#endif
3047	a541f297	bellard	env->access_type = ACCESS_CODE;
3048	9a64fbe4	bellard	/* Set env in case of segfault during code fetch */
3049	9a64fbe4	bellard	while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
3050	79aceca5	bellard	if (search_pc) {
3051	79aceca5	bellard	if (loglevel > 0)
3052	79aceca5	bellard	fprintf(logfile, "Search PC...\n");
3053	79aceca5	bellard	j = gen_opc_ptr - gen_opc_buf;
3054	79aceca5	bellard	if (lj < j) {
3055	79aceca5	bellard	lj++;
3056	79aceca5	bellard	while (lj < j)
3057	79aceca5	bellard	gen_opc_instr_start[lj++] = 0;
3058	046d6672	bellard	gen_opc_pc[lj] = ctx.nip;
3059	79aceca5	bellard	gen_opc_instr_start[lj] = 1;
3060	79aceca5	bellard	}
3061	79aceca5	bellard	}
3062	9fddaa0c	bellard	#if defined PPC_DEBUG_DISAS
3063	9fddaa0c	bellard	if (loglevel & CPU_LOG_TB_IN_ASM) {
3064	79aceca5	bellard	fprintf(logfile, "----------------\n");
3065	046d6672	bellard	fprintf(logfile, "nip=%08x super=%d ir=%d\n",
3066	9a64fbe4	bellard	ctx.nip, 1 - msr_pr, msr_ir);
3067	9a64fbe4	bellard	}
3068	9a64fbe4	bellard	#endif
3069	046d6672	bellard	ctx.opcode = ldl_code((void *)ctx.nip);
3070	9fddaa0c	bellard	#if defined PPC_DEBUG_DISAS
3071	9fddaa0c	bellard	if (loglevel & CPU_LOG_TB_IN_ASM) {
3072	9a64fbe4	bellard	fprintf(logfile, "translate opcode %08x (%02x %02x %02x)\n",
3073	9a64fbe4	bellard	ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
3074	9a64fbe4	bellard	opc3(ctx.opcode));
3075	79aceca5	bellard	}
3076	79aceca5	bellard	#endif
3077	046d6672	bellard	ctx.nip += 4;
3078	79aceca5	bellard	table = ppc_opcodes;
3079	79aceca5	bellard	handler = table[opc1(ctx.opcode)];
3080	79aceca5	bellard	if (is_indirect_opcode(handler)) {
3081	79aceca5	bellard	table = ind_table(handler);
3082	79aceca5	bellard	handler = table[opc2(ctx.opcode)];
3083	79aceca5	bellard	if (is_indirect_opcode(handler)) {
3084	79aceca5	bellard	table = ind_table(handler);
3085	79aceca5	bellard	handler = table[opc3(ctx.opcode)];
3086	79aceca5	bellard	}
3087	79aceca5	bellard	}
3088	79aceca5	bellard	/* Is opcode REALLY valid ? */
3089	79aceca5	bellard	if (handler->handler == &gen_invalid) {
3090	4b3686fa	bellard	if (loglevel > 0) {
3091	79aceca5	bellard	fprintf(logfile, "invalid/unsupported opcode: "
3092	4b3686fa	bellard	"%02x - %02x - %02x (%08x) 0x%08x %d\n",
3093	9a64fbe4	bellard	opc1(ctx.opcode), opc2(ctx.opcode),
3094	4b3686fa	bellard	opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3095	4b3686fa	bellard	} else {
3096	4b3686fa	bellard	printf("invalid/unsupported opcode: "
3097	4b3686fa	bellard	"%02x - %02x - %02x (%08x) 0x%08x %d\n",
3098	4b3686fa	bellard	opc1(ctx.opcode), opc2(ctx.opcode),
3099	4b3686fa	bellard	opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3100	4b3686fa	bellard	}
3101	79aceca5	bellard	} else {
3102	4b3686fa	bellard	if ((ctx.opcode & handler->inval) != 0) {
3103	4b3686fa	bellard	if (loglevel > 0) {
3104	79aceca5	bellard	fprintf(logfile, "invalid bits: %08x for opcode: "
3105	046d6672	bellard	"%02x -%02x - %02x (0x%08x) (0x%08x)\n",
3106	79aceca5	bellard	ctx.opcode & handler->inval, opc1(ctx.opcode),
3107	79aceca5	bellard	opc2(ctx.opcode), opc3(ctx.opcode),
3108	046d6672	bellard	ctx.opcode, ctx.nip - 4);
3109	9a64fbe4	bellard	} else {
3110	9a64fbe4	bellard	printf("invalid bits: %08x for opcode: "
3111	046d6672	bellard	"%02x -%02x - %02x (0x%08x) (0x%08x)\n",
3112	9a64fbe4	bellard	ctx.opcode & handler->inval, opc1(ctx.opcode),
3113	9a64fbe4	bellard	opc2(ctx.opcode), opc3(ctx.opcode),
3114	046d6672	bellard	ctx.opcode, ctx.nip - 4);
3115	9a64fbe4	bellard	}
3116	4b3686fa	bellard	RET_INVAL(ctxp);
3117	4b3686fa	bellard	break;
3118	79aceca5	bellard	}
3119	79aceca5	bellard	}
3120	4b3686fa	bellard	(*(handler->handler))(&ctx);
3121	9a64fbe4	bellard	/* Check trace mode exceptions */
3122	9a64fbe4	bellard	if ((msr_be && ctx.exception == EXCP_BRANCH) \|\|
3123	9a64fbe4	bellard	/* Check in single step trace mode
3124	9a64fbe4	bellard	* we need to stop except if:
3125	9a64fbe4	bellard	* - rfi, trap or syscall
3126	9a64fbe4	bellard	* - first instruction of an exception handler
3127	9a64fbe4	bellard	*/
3128	046d6672	bellard	(msr_se && (ctx.nip < 0x100 \|\|
3129	046d6672	bellard	ctx.nip > 0xF00 \|\|
3130	046d6672	bellard	(ctx.nip & 0xFC) != 0x04) &&
3131	9a64fbe4	bellard	ctx.exception != EXCP_SYSCALL && ctx.exception != EXCP_RFI &&
3132	9a64fbe4	bellard	ctx.exception != EXCP_TRAP)) {
3133	9fddaa0c	bellard	RET_EXCP(ctxp, EXCP_TRACE, 0);
3134	9a64fbe4	bellard	}
3135	a541f297	bellard	/* if we reach a page boundary, stop generation */
3136	046d6672	bellard	if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) {
3137	9fddaa0c	bellard	RET_EXCP(ctxp, EXCP_BRANCH, 0);
3138	79aceca5	bellard	}
3139	9a64fbe4	bellard	}
3140	9fddaa0c	bellard	if (ctx.exception == EXCP_NONE) {
3141	9fddaa0c	bellard	gen_op_b((unsigned long)ctx.tb, ctx.nip);
3142	9fddaa0c	bellard	} else if (ctx.exception != EXCP_BRANCH) {
3143	9fddaa0c	bellard	gen_op_set_T0(0);
3144	9a64fbe4	bellard	}
3145	9a64fbe4	bellard	#if 1
3146	79aceca5	bellard	/* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
3147	79aceca5	bellard	* do bad business and then qemu crashes !
3148	79aceca5	bellard	*/
3149	79aceca5	bellard	gen_op_set_T0(0);
3150	9a64fbe4	bellard	#endif
3151	79aceca5	bellard	/* Generate the return instruction */
3152	79aceca5	bellard	gen_op_exit_tb();
3153	79aceca5	bellard	*gen_opc_ptr = INDEX_op_end;
3154	9a64fbe4	bellard	if (search_pc) {
3155	9a64fbe4	bellard	j = gen_opc_ptr - gen_opc_buf;
3156	9a64fbe4	bellard	lj++;
3157	9a64fbe4	bellard	while (lj <= j)
3158	9a64fbe4	bellard	gen_opc_instr_start[lj++] = 0;
3159	79aceca5	bellard	tb->size = 0;
3160	985a19d6	bellard	#if 0
3161	9a64fbe4	bellard	if (loglevel > 0) {
3162	9a64fbe4	bellard	page_dump(logfile);
3163	9a64fbe4	bellard	}
3164	985a19d6	bellard	#endif
3165	9a64fbe4	bellard	} else {
3166	046d6672	bellard	tb->size = ctx.nip - pc_start;
3167	9a64fbe4	bellard	}
3168	79aceca5	bellard	#ifdef DEBUG_DISAS
3169	9fddaa0c	bellard	if (loglevel & CPU_LOG_TB_CPU) {
3170	9a64fbe4	bellard	fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
3171	9a64fbe4	bellard	cpu_ppc_dump_state(env, logfile, 0);
3172	9fddaa0c	bellard	}
3173	9fddaa0c	bellard	if (loglevel & CPU_LOG_TB_IN_ASM) {
3174	79aceca5	bellard	fprintf(logfile, "IN: %s\n", lookup_symbol((void *)pc_start));
3175	046d6672	bellard	disas(logfile, (void *)pc_start, ctx.nip - pc_start, 0, 0);
3176	79aceca5	bellard	fprintf(logfile, "\n");
3177	9fddaa0c	bellard	}
3178	9fddaa0c	bellard	if (loglevel & CPU_LOG_TB_OP) {
3179	79aceca5	bellard	fprintf(logfile, "OP:\n");
3180	79aceca5	bellard	dump_ops(gen_opc_buf, gen_opparam_buf);
3181	79aceca5	bellard	fprintf(logfile, "\n");
3182	79aceca5	bellard	}
3183	79aceca5	bellard	#endif
3184	4b3686fa	bellard	env->access_type = ACCESS_INT;
3185	79aceca5	bellard
3186	79aceca5	bellard	return 0;
3187	79aceca5	bellard	}
3188	79aceca5	bellard
3189	9a64fbe4	bellard	int gen_intermediate_code (CPUState env, struct TranslationBlock tb)
3190	79aceca5	bellard	{
3191	79aceca5	bellard	return gen_intermediate_code_internal(env, tb, 0);
3192	79aceca5	bellard	}
3193	79aceca5	bellard
3194	9a64fbe4	bellard	int gen_intermediate_code_pc (CPUState env, struct TranslationBlock tb)
3195	79aceca5	bellard	{
3196	79aceca5	bellard	return gen_intermediate_code_internal(env, tb, 1);
3197	79aceca5	bellard	}

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