root / hw / milkymist-uart.c @ 025b168c
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/*
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* QEMU model of the Milkymist UART block.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Specification available at:
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* http://www.milkymist.org/socdoc/uart.pdf
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*/
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#include "hw.h" |
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#include "sysbus.h" |
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#include "trace.h" |
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#include "qemu-char.h" |
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#include "qemu-error.h" |
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enum {
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R_RXTX = 0,
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R_DIV, |
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R_MAX |
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}; |
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struct MilkymistUartState {
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SysBusDevice busdev; |
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CharDriverState *chr; |
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qemu_irq rx_irq; |
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qemu_irq tx_irq; |
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uint32_t regs[R_MAX]; |
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}; |
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typedef struct MilkymistUartState MilkymistUartState; |
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static uint32_t uart_read(void *opaque, target_phys_addr_t addr) |
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{ |
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MilkymistUartState *s = opaque; |
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_RXTX:
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case R_DIV:
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r = s->regs[addr]; |
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break;
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default:
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error_report("milkymist_uart: read access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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} |
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trace_milkymist_uart_memory_read(addr << 2, r);
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return r;
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} |
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static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value) |
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{ |
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MilkymistUartState *s = opaque; |
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unsigned char ch = value; |
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trace_milkymist_uart_memory_write(addr, value); |
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addr >>= 2;
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switch (addr) {
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case R_RXTX:
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if (s->chr) {
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qemu_chr_write(s->chr, &ch, 1);
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} |
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trace_milkymist_uart_pulse_irq_tx(); |
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qemu_irq_pulse(s->tx_irq); |
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break;
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case R_DIV:
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s->regs[addr] = value; |
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break;
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default:
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error_report("milkymist_uart: write access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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} |
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} |
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static CPUReadMemoryFunc * const uart_read_fn[] = { |
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NULL,
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NULL,
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&uart_read, |
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}; |
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static CPUWriteMemoryFunc * const uart_write_fn[] = { |
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NULL,
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NULL,
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&uart_write, |
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}; |
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static void uart_rx(void *opaque, const uint8_t *buf, int size) |
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{ |
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MilkymistUartState *s = opaque; |
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s->regs[R_RXTX] = *buf; |
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trace_milkymist_uart_pulse_irq_rx(); |
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qemu_irq_pulse(s->rx_irq); |
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} |
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static int uart_can_rx(void *opaque) |
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{ |
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return 1; |
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} |
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static void uart_event(void *opaque, int event) |
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{ |
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} |
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static void milkymist_uart_reset(DeviceState *d) |
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{ |
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MilkymistUartState *s = container_of(d, MilkymistUartState, busdev.qdev); |
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int i;
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for (i = 0; i < R_MAX; i++) { |
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s->regs[i] = 0;
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} |
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} |
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static int milkymist_uart_init(SysBusDevice *dev) |
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{ |
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MilkymistUartState *s = FROM_SYSBUS(typeof(*s), dev); |
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int uart_regs;
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sysbus_init_irq(dev, &s->rx_irq); |
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sysbus_init_irq(dev, &s->tx_irq); |
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uart_regs = cpu_register_io_memory(uart_read_fn, uart_write_fn, s, |
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DEVICE_NATIVE_ENDIAN); |
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sysbus_init_mmio(dev, R_MAX * 4, uart_regs);
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s->chr = qdev_init_chardev(&dev->qdev); |
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if (s->chr) {
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qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s); |
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} |
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return 0; |
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} |
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static const VMStateDescription vmstate_milkymist_uart = { |
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.name = "milkymist-uart",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) { |
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VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static SysBusDeviceInfo milkymist_uart_info = {
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.init = milkymist_uart_init, |
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.qdev.name = "milkymist-uart",
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.qdev.size = sizeof(MilkymistUartState),
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.qdev.vmsd = &vmstate_milkymist_uart, |
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.qdev.reset = milkymist_uart_reset, |
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}; |
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static void milkymist_uart_register(void) |
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{ |
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sysbus_register_withprop(&milkymist_uart_info); |
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} |
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device_init(milkymist_uart_register) |