Revision 02765534
| b/target-ppc/translate.c | ||
|---|---|---|
| 632 | 632 |
tcg_temp_free(t0); |
| 633 | 633 |
} |
| 634 | 634 |
|
| 635 |
#if defined(TARGET_PPC64) |
|
| 636 | 635 |
static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
| 637 | 636 |
{
|
| 638 | 637 |
TCGv t0, t1; |
| ... | ... | |
| 656 | 655 |
gen_op_cmp32(arg0, t0, s, crf); |
| 657 | 656 |
tcg_temp_free(t0); |
| 658 | 657 |
} |
| 659 |
#endif |
|
| 660 | 658 |
|
| 661 | 659 |
static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
| 662 | 660 |
{
|
| 663 |
#if defined(TARGET_PPC64) |
|
| 664 |
if (!(ctx->sf_mode)) |
|
| 661 |
if (NARROW_MODE(ctx)) {
|
|
| 665 | 662 |
gen_op_cmpi32(reg, 0, 1, 0); |
| 666 |
else |
|
| 667 |
#endif |
|
| 663 |
} else {
|
|
| 668 | 664 |
gen_op_cmpi(reg, 0, 1, 0); |
| 665 |
} |
|
| 669 | 666 |
} |
| 670 | 667 |
|
| 671 | 668 |
/* cmp */ |
| 672 | 669 |
static void gen_cmp(DisasContext *ctx) |
| 673 | 670 |
{
|
| 674 |
#if defined(TARGET_PPC64) |
|
| 675 |
if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
|
| 671 |
if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
|
|
| 676 | 672 |
gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
| 677 | 673 |
1, crfD(ctx->opcode)); |
| 678 |
else |
|
| 679 |
#endif |
|
| 674 |
} else {
|
|
| 680 | 675 |
gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
| 681 | 676 |
1, crfD(ctx->opcode)); |
| 677 |
} |
|
| 682 | 678 |
} |
| 683 | 679 |
|
| 684 | 680 |
/* cmpi */ |
| 685 | 681 |
static void gen_cmpi(DisasContext *ctx) |
| 686 | 682 |
{
|
| 687 |
#if defined(TARGET_PPC64) |
|
| 688 |
if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
|
| 683 |
if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
|
|
| 689 | 684 |
gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
| 690 | 685 |
1, crfD(ctx->opcode)); |
| 691 |
else |
|
| 692 |
#endif |
|
| 686 |
} else {
|
|
| 693 | 687 |
gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
| 694 | 688 |
1, crfD(ctx->opcode)); |
| 689 |
} |
|
| 695 | 690 |
} |
| 696 | 691 |
|
| 697 | 692 |
/* cmpl */ |
| 698 | 693 |
static void gen_cmpl(DisasContext *ctx) |
| 699 | 694 |
{
|
| 700 |
#if defined(TARGET_PPC64) |
|
| 701 |
if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
|
| 695 |
if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
|
|
| 702 | 696 |
gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
| 703 | 697 |
0, crfD(ctx->opcode)); |
| 704 |
else |
|
| 705 |
#endif |
|
| 698 |
} else {
|
|
| 706 | 699 |
gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
| 707 | 700 |
0, crfD(ctx->opcode)); |
| 701 |
} |
|
| 708 | 702 |
} |
| 709 | 703 |
|
| 710 | 704 |
/* cmpli */ |
| 711 | 705 |
static void gen_cmpli(DisasContext *ctx) |
| 712 | 706 |
{
|
| 713 |
#if defined(TARGET_PPC64) |
|
| 714 |
if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
|
| 707 |
if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
|
|
| 715 | 708 |
gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
| 716 | 709 |
0, crfD(ctx->opcode)); |
| 717 |
else |
|
| 718 |
#endif |
|
| 710 |
} else {
|
|
| 719 | 711 |
gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
| 720 | 712 |
0, crfD(ctx->opcode)); |
| 713 |
} |
|
| 721 | 714 |
} |
| 722 | 715 |
|
| 723 | 716 |
/* isel (PowerPC 2.03 specification) */ |
| ... | ... | |
| 761 | 754 |
tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); |
| 762 | 755 |
} |
| 763 | 756 |
tcg_temp_free(t0); |
| 764 |
#if defined(TARGET_PPC64) |
|
| 765 |
if (!ctx->sf_mode) {
|
|
| 757 |
if (NARROW_MODE(ctx)) {
|
|
| 766 | 758 |
tcg_gen_ext32s_tl(cpu_ov, cpu_ov); |
| 767 | 759 |
} |
| 768 |
#endif |
|
| 769 | 760 |
tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1); |
| 770 | 761 |
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
| 771 | 762 |
} |
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