root / hw / pl080.c @ 02fa69b6
History | View | Annotate | Download (11.2 kB)
1 | 5fafdf24 | ths | /*
|
---|---|---|---|
2 | e69954b9 | pbrook | * Arm PrimeCell PL080/PL081 DMA controller
|
3 | cdbdb648 | pbrook | *
|
4 | cdbdb648 | pbrook | * Copyright (c) 2006 CodeSourcery.
|
5 | cdbdb648 | pbrook | * Written by Paul Brook
|
6 | cdbdb648 | pbrook | *
|
7 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GPL.
|
8 | cdbdb648 | pbrook | */
|
9 | cdbdb648 | pbrook | |
10 | b4496b13 | Paul Brook | #include "sysbus.h" |
11 | cdbdb648 | pbrook | |
12 | e69954b9 | pbrook | #define PL080_MAX_CHANNELS 8 |
13 | cdbdb648 | pbrook | #define PL080_CONF_E 0x1 |
14 | cdbdb648 | pbrook | #define PL080_CONF_M1 0x2 |
15 | cdbdb648 | pbrook | #define PL080_CONF_M2 0x4 |
16 | cdbdb648 | pbrook | |
17 | cdbdb648 | pbrook | #define PL080_CCONF_H 0x40000 |
18 | cdbdb648 | pbrook | #define PL080_CCONF_A 0x20000 |
19 | cdbdb648 | pbrook | #define PL080_CCONF_L 0x10000 |
20 | cdbdb648 | pbrook | #define PL080_CCONF_ITC 0x08000 |
21 | cdbdb648 | pbrook | #define PL080_CCONF_IE 0x04000 |
22 | cdbdb648 | pbrook | #define PL080_CCONF_E 0x00001 |
23 | cdbdb648 | pbrook | |
24 | cdbdb648 | pbrook | #define PL080_CCTRL_I 0x80000000 |
25 | cdbdb648 | pbrook | #define PL080_CCTRL_DI 0x08000000 |
26 | cdbdb648 | pbrook | #define PL080_CCTRL_SI 0x04000000 |
27 | cdbdb648 | pbrook | #define PL080_CCTRL_D 0x02000000 |
28 | cdbdb648 | pbrook | #define PL080_CCTRL_S 0x01000000 |
29 | cdbdb648 | pbrook | |
30 | cdbdb648 | pbrook | typedef struct { |
31 | cdbdb648 | pbrook | uint32_t src; |
32 | cdbdb648 | pbrook | uint32_t dest; |
33 | cdbdb648 | pbrook | uint32_t lli; |
34 | cdbdb648 | pbrook | uint32_t ctrl; |
35 | cdbdb648 | pbrook | uint32_t conf; |
36 | cdbdb648 | pbrook | } pl080_channel; |
37 | cdbdb648 | pbrook | |
38 | cdbdb648 | pbrook | typedef struct { |
39 | b4496b13 | Paul Brook | SysBusDevice busdev; |
40 | cdbdb648 | pbrook | uint8_t tc_int; |
41 | cdbdb648 | pbrook | uint8_t tc_mask; |
42 | cdbdb648 | pbrook | uint8_t err_int; |
43 | cdbdb648 | pbrook | uint8_t err_mask; |
44 | cdbdb648 | pbrook | uint32_t conf; |
45 | cdbdb648 | pbrook | uint32_t sync; |
46 | cdbdb648 | pbrook | uint32_t req_single; |
47 | cdbdb648 | pbrook | uint32_t req_burst; |
48 | e69954b9 | pbrook | pl080_channel chan[PL080_MAX_CHANNELS]; |
49 | e69954b9 | pbrook | int nchannels;
|
50 | cdbdb648 | pbrook | /* Flag to avoid recursive DMA invocations. */
|
51 | cdbdb648 | pbrook | int running;
|
52 | d537cf6c | pbrook | qemu_irq irq; |
53 | cdbdb648 | pbrook | } pl080_state; |
54 | cdbdb648 | pbrook | |
55 | ff175853 | Peter Maydell | static const VMStateDescription vmstate_pl080_channel = { |
56 | ff175853 | Peter Maydell | .name = "pl080_channel",
|
57 | ff175853 | Peter Maydell | .version_id = 1,
|
58 | ff175853 | Peter Maydell | .minimum_version_id = 1,
|
59 | ff175853 | Peter Maydell | .fields = (VMStateField[]) { |
60 | ff175853 | Peter Maydell | VMSTATE_UINT32(src, pl080_channel), |
61 | ff175853 | Peter Maydell | VMSTATE_UINT32(dest, pl080_channel), |
62 | ff175853 | Peter Maydell | VMSTATE_UINT32(lli, pl080_channel), |
63 | ff175853 | Peter Maydell | VMSTATE_UINT32(ctrl, pl080_channel), |
64 | ff175853 | Peter Maydell | VMSTATE_UINT32(conf, pl080_channel), |
65 | ff175853 | Peter Maydell | VMSTATE_END_OF_LIST() |
66 | ff175853 | Peter Maydell | } |
67 | ff175853 | Peter Maydell | }; |
68 | ff175853 | Peter Maydell | |
69 | ff175853 | Peter Maydell | static const VMStateDescription vmstate_pl080 = { |
70 | ff175853 | Peter Maydell | .name = "pl080",
|
71 | ff175853 | Peter Maydell | .version_id = 1,
|
72 | ff175853 | Peter Maydell | .minimum_version_id = 1,
|
73 | ff175853 | Peter Maydell | .fields = (VMStateField[]) { |
74 | ff175853 | Peter Maydell | VMSTATE_UINT8(tc_int, pl080_state), |
75 | ff175853 | Peter Maydell | VMSTATE_UINT8(tc_mask, pl080_state), |
76 | ff175853 | Peter Maydell | VMSTATE_UINT8(err_int, pl080_state), |
77 | ff175853 | Peter Maydell | VMSTATE_UINT8(err_mask, pl080_state), |
78 | ff175853 | Peter Maydell | VMSTATE_UINT32(conf, pl080_state), |
79 | ff175853 | Peter Maydell | VMSTATE_UINT32(sync, pl080_state), |
80 | ff175853 | Peter Maydell | VMSTATE_UINT32(req_single, pl080_state), |
81 | ff175853 | Peter Maydell | VMSTATE_UINT32(req_burst, pl080_state), |
82 | ff175853 | Peter Maydell | VMSTATE_UINT8(tc_int, pl080_state), |
83 | ff175853 | Peter Maydell | VMSTATE_UINT8(tc_int, pl080_state), |
84 | ff175853 | Peter Maydell | VMSTATE_UINT8(tc_int, pl080_state), |
85 | ff175853 | Peter Maydell | VMSTATE_STRUCT_ARRAY(chan, pl080_state, PL080_MAX_CHANNELS, |
86 | ff175853 | Peter Maydell | 1, vmstate_pl080_channel, pl080_channel),
|
87 | ff175853 | Peter Maydell | VMSTATE_INT32(running, pl080_state), |
88 | ff175853 | Peter Maydell | VMSTATE_END_OF_LIST() |
89 | ff175853 | Peter Maydell | } |
90 | ff175853 | Peter Maydell | }; |
91 | ff175853 | Peter Maydell | |
92 | cdbdb648 | pbrook | static const unsigned char pl080_id[] = |
93 | cdbdb648 | pbrook | { 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 }; |
94 | cdbdb648 | pbrook | |
95 | e69954b9 | pbrook | static const unsigned char pl081_id[] = |
96 | e69954b9 | pbrook | { 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 }; |
97 | e69954b9 | pbrook | |
98 | cdbdb648 | pbrook | static void pl080_update(pl080_state *s) |
99 | cdbdb648 | pbrook | { |
100 | cdbdb648 | pbrook | if ((s->tc_int & s->tc_mask)
|
101 | cdbdb648 | pbrook | || (s->err_int & s->err_mask)) |
102 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
103 | cdbdb648 | pbrook | else
|
104 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
105 | cdbdb648 | pbrook | } |
106 | cdbdb648 | pbrook | |
107 | cdbdb648 | pbrook | static void pl080_run(pl080_state *s) |
108 | cdbdb648 | pbrook | { |
109 | cdbdb648 | pbrook | int c;
|
110 | cdbdb648 | pbrook | int flow;
|
111 | cdbdb648 | pbrook | pl080_channel *ch; |
112 | cdbdb648 | pbrook | int swidth;
|
113 | cdbdb648 | pbrook | int dwidth;
|
114 | cdbdb648 | pbrook | int xsize;
|
115 | cdbdb648 | pbrook | int n;
|
116 | cdbdb648 | pbrook | int src_id;
|
117 | cdbdb648 | pbrook | int dest_id;
|
118 | cdbdb648 | pbrook | int size;
|
119 | b55266b5 | blueswir1 | uint8_t buff[4];
|
120 | cdbdb648 | pbrook | uint32_t req; |
121 | cdbdb648 | pbrook | |
122 | cdbdb648 | pbrook | s->tc_mask = 0;
|
123 | e69954b9 | pbrook | for (c = 0; c < s->nchannels; c++) { |
124 | cdbdb648 | pbrook | if (s->chan[c].conf & PL080_CCONF_ITC)
|
125 | cdbdb648 | pbrook | s->tc_mask |= 1 << c;
|
126 | cdbdb648 | pbrook | if (s->chan[c].conf & PL080_CCONF_IE)
|
127 | cdbdb648 | pbrook | s->err_mask |= 1 << c;
|
128 | cdbdb648 | pbrook | } |
129 | cdbdb648 | pbrook | |
130 | cdbdb648 | pbrook | if ((s->conf & PL080_CONF_E) == 0) |
131 | cdbdb648 | pbrook | return;
|
132 | cdbdb648 | pbrook | |
133 | 2ac71179 | Paul Brook | hw_error("DMA active\n");
|
134 | cdbdb648 | pbrook | /* If we are already in the middle of a DMA operation then indicate that
|
135 | cdbdb648 | pbrook | there may be new DMA requests and return immediately. */
|
136 | cdbdb648 | pbrook | if (s->running) {
|
137 | cdbdb648 | pbrook | s->running++; |
138 | cdbdb648 | pbrook | return;
|
139 | cdbdb648 | pbrook | } |
140 | cdbdb648 | pbrook | s->running = 1;
|
141 | cdbdb648 | pbrook | while (s->running) {
|
142 | e69954b9 | pbrook | for (c = 0; c < s->nchannels; c++) { |
143 | cdbdb648 | pbrook | ch = &s->chan[c]; |
144 | cdbdb648 | pbrook | again:
|
145 | cdbdb648 | pbrook | /* Test if thiws channel has any pending DMA requests. */
|
146 | cdbdb648 | pbrook | if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E))
|
147 | cdbdb648 | pbrook | != PL080_CCONF_E) |
148 | cdbdb648 | pbrook | continue;
|
149 | cdbdb648 | pbrook | flow = (ch->conf >> 11) & 7; |
150 | cdbdb648 | pbrook | if (flow >= 4) { |
151 | 2ac71179 | Paul Brook | hw_error( |
152 | cdbdb648 | pbrook | "pl080_run: Peripheral flow control not implemented\n");
|
153 | cdbdb648 | pbrook | } |
154 | cdbdb648 | pbrook | src_id = (ch->conf >> 1) & 0x1f; |
155 | cdbdb648 | pbrook | dest_id = (ch->conf >> 6) & 0x1f; |
156 | cdbdb648 | pbrook | size = ch->ctrl & 0xfff;
|
157 | cdbdb648 | pbrook | req = s->req_single | s->req_burst; |
158 | cdbdb648 | pbrook | switch (flow) {
|
159 | cdbdb648 | pbrook | case 0: |
160 | cdbdb648 | pbrook | break;
|
161 | cdbdb648 | pbrook | case 1: |
162 | cdbdb648 | pbrook | if ((req & (1u << dest_id)) == 0) |
163 | cdbdb648 | pbrook | size = 0;
|
164 | cdbdb648 | pbrook | break;
|
165 | cdbdb648 | pbrook | case 2: |
166 | cdbdb648 | pbrook | if ((req & (1u << src_id)) == 0) |
167 | cdbdb648 | pbrook | size = 0;
|
168 | cdbdb648 | pbrook | break;
|
169 | cdbdb648 | pbrook | case 3: |
170 | cdbdb648 | pbrook | if ((req & (1u << src_id)) == 0 |
171 | cdbdb648 | pbrook | || (req & (1u << dest_id)) == 0) |
172 | cdbdb648 | pbrook | size = 0;
|
173 | cdbdb648 | pbrook | break;
|
174 | cdbdb648 | pbrook | } |
175 | cdbdb648 | pbrook | if (!size)
|
176 | cdbdb648 | pbrook | continue;
|
177 | cdbdb648 | pbrook | |
178 | cdbdb648 | pbrook | /* Transfer one element. */
|
179 | cdbdb648 | pbrook | /* ??? Should transfer multiple elements for a burst request. */
|
180 | cdbdb648 | pbrook | /* ??? Unclear what the proper behavior is when source and
|
181 | cdbdb648 | pbrook | destination widths are different. */
|
182 | cdbdb648 | pbrook | swidth = 1 << ((ch->ctrl >> 18) & 7); |
183 | cdbdb648 | pbrook | dwidth = 1 << ((ch->ctrl >> 21) & 7); |
184 | cdbdb648 | pbrook | for (n = 0; n < dwidth; n+= swidth) { |
185 | cdbdb648 | pbrook | cpu_physical_memory_read(ch->src, buff + n, swidth); |
186 | cdbdb648 | pbrook | if (ch->ctrl & PL080_CCTRL_SI)
|
187 | cdbdb648 | pbrook | ch->src += swidth; |
188 | cdbdb648 | pbrook | } |
189 | cdbdb648 | pbrook | xsize = (dwidth < swidth) ? swidth : dwidth; |
190 | cdbdb648 | pbrook | /* ??? This may pad the value incorrectly for dwidth < 32. */
|
191 | cdbdb648 | pbrook | for (n = 0; n < xsize; n += dwidth) { |
192 | cdbdb648 | pbrook | cpu_physical_memory_write(ch->dest + n, buff + n, dwidth); |
193 | cdbdb648 | pbrook | if (ch->ctrl & PL080_CCTRL_DI)
|
194 | cdbdb648 | pbrook | ch->dest += swidth; |
195 | cdbdb648 | pbrook | } |
196 | cdbdb648 | pbrook | |
197 | cdbdb648 | pbrook | size--; |
198 | cdbdb648 | pbrook | ch->ctrl = (ch->ctrl & 0xfffff000) | size;
|
199 | cdbdb648 | pbrook | if (size == 0) { |
200 | cdbdb648 | pbrook | /* Transfer complete. */
|
201 | cdbdb648 | pbrook | if (ch->lli) {
|
202 | 75b0646f | Alexander Graf | ch->src = ldl_le_phys(ch->lli); |
203 | 75b0646f | Alexander Graf | ch->dest = ldl_le_phys(ch->lli + 4);
|
204 | 75b0646f | Alexander Graf | ch->ctrl = ldl_le_phys(ch->lli + 12);
|
205 | 75b0646f | Alexander Graf | ch->lli = ldl_le_phys(ch->lli + 8);
|
206 | cdbdb648 | pbrook | } else {
|
207 | cdbdb648 | pbrook | ch->conf &= ~PL080_CCONF_E; |
208 | cdbdb648 | pbrook | } |
209 | cdbdb648 | pbrook | if (ch->ctrl & PL080_CCTRL_I) {
|
210 | cdbdb648 | pbrook | s->tc_int |= 1 << c;
|
211 | cdbdb648 | pbrook | } |
212 | cdbdb648 | pbrook | } |
213 | cdbdb648 | pbrook | goto again;
|
214 | cdbdb648 | pbrook | } |
215 | cdbdb648 | pbrook | if (--s->running)
|
216 | cdbdb648 | pbrook | s->running = 1;
|
217 | cdbdb648 | pbrook | } |
218 | cdbdb648 | pbrook | } |
219 | cdbdb648 | pbrook | |
220 | c227f099 | Anthony Liguori | static uint32_t pl080_read(void *opaque, target_phys_addr_t offset) |
221 | cdbdb648 | pbrook | { |
222 | cdbdb648 | pbrook | pl080_state *s = (pl080_state *)opaque; |
223 | cdbdb648 | pbrook | uint32_t i; |
224 | cdbdb648 | pbrook | uint32_t mask; |
225 | cdbdb648 | pbrook | |
226 | cdbdb648 | pbrook | if (offset >= 0xfe0 && offset < 0x1000) { |
227 | e69954b9 | pbrook | if (s->nchannels == 8) { |
228 | e69954b9 | pbrook | return pl080_id[(offset - 0xfe0) >> 2]; |
229 | e69954b9 | pbrook | } else {
|
230 | e69954b9 | pbrook | return pl081_id[(offset - 0xfe0) >> 2]; |
231 | e69954b9 | pbrook | } |
232 | cdbdb648 | pbrook | } |
233 | cdbdb648 | pbrook | if (offset >= 0x100 && offset < 0x200) { |
234 | cdbdb648 | pbrook | i = (offset & 0xe0) >> 5; |
235 | e69954b9 | pbrook | if (i >= s->nchannels)
|
236 | e69954b9 | pbrook | goto bad_offset;
|
237 | cdbdb648 | pbrook | switch (offset >> 2) { |
238 | cdbdb648 | pbrook | case 0: /* SrcAddr */ |
239 | cdbdb648 | pbrook | return s->chan[i].src;
|
240 | cdbdb648 | pbrook | case 1: /* DestAddr */ |
241 | cdbdb648 | pbrook | return s->chan[i].dest;
|
242 | cdbdb648 | pbrook | case 2: /* LLI */ |
243 | cdbdb648 | pbrook | return s->chan[i].lli;
|
244 | cdbdb648 | pbrook | case 3: /* Control */ |
245 | cdbdb648 | pbrook | return s->chan[i].ctrl;
|
246 | cdbdb648 | pbrook | case 4: /* Configuration */ |
247 | cdbdb648 | pbrook | return s->chan[i].conf;
|
248 | cdbdb648 | pbrook | default:
|
249 | cdbdb648 | pbrook | goto bad_offset;
|
250 | cdbdb648 | pbrook | } |
251 | cdbdb648 | pbrook | } |
252 | cdbdb648 | pbrook | switch (offset >> 2) { |
253 | cdbdb648 | pbrook | case 0: /* IntStatus */ |
254 | cdbdb648 | pbrook | return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask);
|
255 | cdbdb648 | pbrook | case 1: /* IntTCStatus */ |
256 | cdbdb648 | pbrook | return (s->tc_int & s->tc_mask);
|
257 | cdbdb648 | pbrook | case 3: /* IntErrorStatus */ |
258 | cdbdb648 | pbrook | return (s->err_int & s->err_mask);
|
259 | cdbdb648 | pbrook | case 5: /* RawIntTCStatus */ |
260 | cdbdb648 | pbrook | return s->tc_int;
|
261 | cdbdb648 | pbrook | case 6: /* RawIntErrorStatus */ |
262 | cdbdb648 | pbrook | return s->err_int;
|
263 | cdbdb648 | pbrook | case 7: /* EnbldChns */ |
264 | cdbdb648 | pbrook | mask = 0;
|
265 | e69954b9 | pbrook | for (i = 0; i < s->nchannels; i++) { |
266 | cdbdb648 | pbrook | if (s->chan[i].conf & PL080_CCONF_E)
|
267 | cdbdb648 | pbrook | mask |= 1 << i;
|
268 | cdbdb648 | pbrook | } |
269 | cdbdb648 | pbrook | return mask;
|
270 | cdbdb648 | pbrook | case 8: /* SoftBReq */ |
271 | cdbdb648 | pbrook | case 9: /* SoftSReq */ |
272 | cdbdb648 | pbrook | case 10: /* SoftLBReq */ |
273 | cdbdb648 | pbrook | case 11: /* SoftLSReq */ |
274 | cdbdb648 | pbrook | /* ??? Implement these. */
|
275 | cdbdb648 | pbrook | return 0; |
276 | cdbdb648 | pbrook | case 12: /* Configuration */ |
277 | cdbdb648 | pbrook | return s->conf;
|
278 | cdbdb648 | pbrook | case 13: /* Sync */ |
279 | cdbdb648 | pbrook | return s->sync;
|
280 | cdbdb648 | pbrook | default:
|
281 | cdbdb648 | pbrook | bad_offset:
|
282 | 2ac71179 | Paul Brook | hw_error("pl080_read: Bad offset %x\n", (int)offset); |
283 | cdbdb648 | pbrook | return 0; |
284 | cdbdb648 | pbrook | } |
285 | cdbdb648 | pbrook | } |
286 | cdbdb648 | pbrook | |
287 | c227f099 | Anthony Liguori | static void pl080_write(void *opaque, target_phys_addr_t offset, |
288 | cdbdb648 | pbrook | uint32_t value) |
289 | cdbdb648 | pbrook | { |
290 | cdbdb648 | pbrook | pl080_state *s = (pl080_state *)opaque; |
291 | cdbdb648 | pbrook | int i;
|
292 | cdbdb648 | pbrook | |
293 | cdbdb648 | pbrook | if (offset >= 0x100 && offset < 0x200) { |
294 | cdbdb648 | pbrook | i = (offset & 0xe0) >> 5; |
295 | e69954b9 | pbrook | if (i >= s->nchannels)
|
296 | e69954b9 | pbrook | goto bad_offset;
|
297 | cdbdb648 | pbrook | switch (offset >> 2) { |
298 | cdbdb648 | pbrook | case 0: /* SrcAddr */ |
299 | cdbdb648 | pbrook | s->chan[i].src = value; |
300 | cdbdb648 | pbrook | break;
|
301 | cdbdb648 | pbrook | case 1: /* DestAddr */ |
302 | cdbdb648 | pbrook | s->chan[i].dest = value; |
303 | cdbdb648 | pbrook | break;
|
304 | cdbdb648 | pbrook | case 2: /* LLI */ |
305 | cdbdb648 | pbrook | s->chan[i].lli = value; |
306 | cdbdb648 | pbrook | break;
|
307 | cdbdb648 | pbrook | case 3: /* Control */ |
308 | cdbdb648 | pbrook | s->chan[i].ctrl = value; |
309 | cdbdb648 | pbrook | break;
|
310 | cdbdb648 | pbrook | case 4: /* Configuration */ |
311 | cdbdb648 | pbrook | s->chan[i].conf = value; |
312 | cdbdb648 | pbrook | pl080_run(s); |
313 | cdbdb648 | pbrook | break;
|
314 | cdbdb648 | pbrook | } |
315 | cdbdb648 | pbrook | } |
316 | cdbdb648 | pbrook | switch (offset >> 2) { |
317 | cdbdb648 | pbrook | case 2: /* IntTCClear */ |
318 | cdbdb648 | pbrook | s->tc_int &= ~value; |
319 | cdbdb648 | pbrook | break;
|
320 | cdbdb648 | pbrook | case 4: /* IntErrorClear */ |
321 | cdbdb648 | pbrook | s->err_int &= ~value; |
322 | cdbdb648 | pbrook | break;
|
323 | cdbdb648 | pbrook | case 8: /* SoftBReq */ |
324 | cdbdb648 | pbrook | case 9: /* SoftSReq */ |
325 | cdbdb648 | pbrook | case 10: /* SoftLBReq */ |
326 | cdbdb648 | pbrook | case 11: /* SoftLSReq */ |
327 | cdbdb648 | pbrook | /* ??? Implement these. */
|
328 | 2ac71179 | Paul Brook | hw_error("pl080_write: Soft DMA not implemented\n");
|
329 | cdbdb648 | pbrook | break;
|
330 | cdbdb648 | pbrook | case 12: /* Configuration */ |
331 | cdbdb648 | pbrook | s->conf = value; |
332 | cdbdb648 | pbrook | if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
|
333 | 2ac71179 | Paul Brook | hw_error("pl080_write: Big-endian DMA not implemented\n");
|
334 | cdbdb648 | pbrook | } |
335 | cdbdb648 | pbrook | pl080_run(s); |
336 | cdbdb648 | pbrook | break;
|
337 | cdbdb648 | pbrook | case 13: /* Sync */ |
338 | cdbdb648 | pbrook | s->sync = value; |
339 | cdbdb648 | pbrook | break;
|
340 | cdbdb648 | pbrook | default:
|
341 | e69954b9 | pbrook | bad_offset:
|
342 | 2ac71179 | Paul Brook | hw_error("pl080_write: Bad offset %x\n", (int)offset); |
343 | cdbdb648 | pbrook | } |
344 | cdbdb648 | pbrook | pl080_update(s); |
345 | cdbdb648 | pbrook | } |
346 | cdbdb648 | pbrook | |
347 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pl080_readfn[] = { |
348 | cdbdb648 | pbrook | pl080_read, |
349 | cdbdb648 | pbrook | pl080_read, |
350 | cdbdb648 | pbrook | pl080_read |
351 | cdbdb648 | pbrook | }; |
352 | cdbdb648 | pbrook | |
353 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pl080_writefn[] = { |
354 | cdbdb648 | pbrook | pl080_write, |
355 | cdbdb648 | pbrook | pl080_write, |
356 | cdbdb648 | pbrook | pl080_write |
357 | cdbdb648 | pbrook | }; |
358 | cdbdb648 | pbrook | |
359 | 81a322d4 | Gerd Hoffmann | static int pl08x_init(SysBusDevice *dev, int nchannels) |
360 | cdbdb648 | pbrook | { |
361 | cdbdb648 | pbrook | int iomemtype;
|
362 | b4496b13 | Paul Brook | pl080_state *s = FROM_SYSBUS(pl080_state, dev); |
363 | cdbdb648 | pbrook | |
364 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(pl080_readfn, |
365 | 2507c12a | Alexander Graf | pl080_writefn, s, |
366 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
367 | b4496b13 | Paul Brook | sysbus_init_mmio(dev, 0x1000, iomemtype);
|
368 | b4496b13 | Paul Brook | sysbus_init_irq(dev, &s->irq); |
369 | e69954b9 | pbrook | s->nchannels = nchannels; |
370 | 81a322d4 | Gerd Hoffmann | return 0; |
371 | cdbdb648 | pbrook | } |
372 | b4496b13 | Paul Brook | |
373 | 81a322d4 | Gerd Hoffmann | static int pl080_init(SysBusDevice *dev) |
374 | b4496b13 | Paul Brook | { |
375 | 81a322d4 | Gerd Hoffmann | return pl08x_init(dev, 8); |
376 | b4496b13 | Paul Brook | } |
377 | b4496b13 | Paul Brook | |
378 | 81a322d4 | Gerd Hoffmann | static int pl081_init(SysBusDevice *dev) |
379 | b4496b13 | Paul Brook | { |
380 | 81a322d4 | Gerd Hoffmann | return pl08x_init(dev, 2); |
381 | b4496b13 | Paul Brook | } |
382 | b4496b13 | Paul Brook | |
383 | ff175853 | Peter Maydell | static SysBusDeviceInfo pl080_info = {
|
384 | ff175853 | Peter Maydell | .init = pl080_init, |
385 | ff175853 | Peter Maydell | .qdev.name = "pl080",
|
386 | ff175853 | Peter Maydell | .qdev.size = sizeof(pl080_state),
|
387 | ff175853 | Peter Maydell | .qdev.vmsd = &vmstate_pl080, |
388 | ff175853 | Peter Maydell | .qdev.no_user = 1,
|
389 | ff175853 | Peter Maydell | }; |
390 | ff175853 | Peter Maydell | |
391 | ff175853 | Peter Maydell | static SysBusDeviceInfo pl081_info = {
|
392 | ff175853 | Peter Maydell | .init = pl081_init, |
393 | ff175853 | Peter Maydell | .qdev.name = "pl081",
|
394 | ff175853 | Peter Maydell | .qdev.size = sizeof(pl080_state),
|
395 | ff175853 | Peter Maydell | .qdev.vmsd = &vmstate_pl080, |
396 | ff175853 | Peter Maydell | .qdev.no_user = 1,
|
397 | ff175853 | Peter Maydell | }; |
398 | ff175853 | Peter Maydell | |
399 | b4496b13 | Paul Brook | /* The PL080 and PL081 are the same except for the number of channels
|
400 | b4496b13 | Paul Brook | they implement (8 and 2 respectively). */
|
401 | b4496b13 | Paul Brook | static void pl080_register_devices(void) |
402 | b4496b13 | Paul Brook | { |
403 | ff175853 | Peter Maydell | sysbus_register_withprop(&pl080_info); |
404 | ff175853 | Peter Maydell | sysbus_register_withprop(&pl081_info); |
405 | b4496b13 | Paul Brook | } |
406 | b4496b13 | Paul Brook | |
407 | b4496b13 | Paul Brook | device_init(pl080_register_devices) |