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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * i386 virtual CPU header
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3 | 2c0262af | bellard | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 2c0262af | bellard | #ifndef CPU_I386_H
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21 | 2c0262af | bellard | #define CPU_I386_H
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22 | 2c0262af | bellard | |
23 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
24 | 3cf1e035 | bellard | |
25 | 2c0262af | bellard | #include "cpu-defs.h" |
26 | 2c0262af | bellard | |
27 | 58fe2f10 | bellard | #if defined(__i386__) && !defined(CONFIG_SOFTMMU)
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28 | 58fe2f10 | bellard | #define USE_CODE_COPY
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29 | 58fe2f10 | bellard | #endif
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30 | 58fe2f10 | bellard | |
31 | 2c0262af | bellard | #define R_EAX 0 |
32 | 2c0262af | bellard | #define R_ECX 1 |
33 | 2c0262af | bellard | #define R_EDX 2 |
34 | 2c0262af | bellard | #define R_EBX 3 |
35 | 2c0262af | bellard | #define R_ESP 4 |
36 | 2c0262af | bellard | #define R_EBP 5 |
37 | 2c0262af | bellard | #define R_ESI 6 |
38 | 2c0262af | bellard | #define R_EDI 7 |
39 | 2c0262af | bellard | |
40 | 2c0262af | bellard | #define R_AL 0 |
41 | 2c0262af | bellard | #define R_CL 1 |
42 | 2c0262af | bellard | #define R_DL 2 |
43 | 2c0262af | bellard | #define R_BL 3 |
44 | 2c0262af | bellard | #define R_AH 4 |
45 | 2c0262af | bellard | #define R_CH 5 |
46 | 2c0262af | bellard | #define R_DH 6 |
47 | 2c0262af | bellard | #define R_BH 7 |
48 | 2c0262af | bellard | |
49 | 2c0262af | bellard | #define R_ES 0 |
50 | 2c0262af | bellard | #define R_CS 1 |
51 | 2c0262af | bellard | #define R_SS 2 |
52 | 2c0262af | bellard | #define R_DS 3 |
53 | 2c0262af | bellard | #define R_FS 4 |
54 | 2c0262af | bellard | #define R_GS 5 |
55 | 2c0262af | bellard | |
56 | 2c0262af | bellard | /* segment descriptor fields */
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57 | 2c0262af | bellard | #define DESC_G_MASK (1 << 23) |
58 | 2c0262af | bellard | #define DESC_B_SHIFT 22 |
59 | 2c0262af | bellard | #define DESC_B_MASK (1 << DESC_B_SHIFT) |
60 | 2c0262af | bellard | #define DESC_AVL_MASK (1 << 20) |
61 | 2c0262af | bellard | #define DESC_P_MASK (1 << 15) |
62 | 2c0262af | bellard | #define DESC_DPL_SHIFT 13 |
63 | 2c0262af | bellard | #define DESC_S_MASK (1 << 12) |
64 | 2c0262af | bellard | #define DESC_TYPE_SHIFT 8 |
65 | 2c0262af | bellard | #define DESC_A_MASK (1 << 8) |
66 | 2c0262af | bellard | |
67 | e670b89e | bellard | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
68 | e670b89e | bellard | #define DESC_C_MASK (1 << 10) /* code: conforming */ |
69 | e670b89e | bellard | #define DESC_R_MASK (1 << 9) /* code: readable */ |
70 | 2c0262af | bellard | |
71 | e670b89e | bellard | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
72 | e670b89e | bellard | #define DESC_W_MASK (1 << 9) /* data: writable */ |
73 | e670b89e | bellard | |
74 | e670b89e | bellard | #define DESC_TSS_BUSY_MASK (1 << 9) |
75 | 2c0262af | bellard | |
76 | 2c0262af | bellard | /* eflags masks */
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77 | 2c0262af | bellard | #define CC_C 0x0001 |
78 | 2c0262af | bellard | #define CC_P 0x0004 |
79 | 2c0262af | bellard | #define CC_A 0x0010 |
80 | 2c0262af | bellard | #define CC_Z 0x0040 |
81 | 2c0262af | bellard | #define CC_S 0x0080 |
82 | 2c0262af | bellard | #define CC_O 0x0800 |
83 | 2c0262af | bellard | |
84 | 2c0262af | bellard | #define TF_SHIFT 8 |
85 | 2c0262af | bellard | #define IOPL_SHIFT 12 |
86 | 2c0262af | bellard | #define VM_SHIFT 17 |
87 | 2c0262af | bellard | |
88 | 2c0262af | bellard | #define TF_MASK 0x00000100 |
89 | 2c0262af | bellard | #define IF_MASK 0x00000200 |
90 | 2c0262af | bellard | #define DF_MASK 0x00000400 |
91 | 2c0262af | bellard | #define IOPL_MASK 0x00003000 |
92 | 2c0262af | bellard | #define NT_MASK 0x00004000 |
93 | 2c0262af | bellard | #define RF_MASK 0x00010000 |
94 | 2c0262af | bellard | #define VM_MASK 0x00020000 |
95 | 2c0262af | bellard | #define AC_MASK 0x00040000 |
96 | 2c0262af | bellard | #define VIF_MASK 0x00080000 |
97 | 2c0262af | bellard | #define VIP_MASK 0x00100000 |
98 | 2c0262af | bellard | #define ID_MASK 0x00200000 |
99 | 2c0262af | bellard | |
100 | 2c0262af | bellard | /* hidden flags - used internally by qemu to represent additionnal cpu
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101 | 2c0262af | bellard | states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
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102 | 2c0262af | bellard | using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
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103 | 2c0262af | bellard | with eflags. */
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104 | 2c0262af | bellard | /* current cpl */
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105 | 2c0262af | bellard | #define HF_CPL_SHIFT 0 |
106 | 2c0262af | bellard | /* true if soft mmu is being used */
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107 | 2c0262af | bellard | #define HF_SOFTMMU_SHIFT 2 |
108 | 2c0262af | bellard | /* true if hardware interrupts must be disabled for next instruction */
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109 | 2c0262af | bellard | #define HF_INHIBIT_IRQ_SHIFT 3 |
110 | 2c0262af | bellard | /* 16 or 32 segments */
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111 | 2c0262af | bellard | #define HF_CS32_SHIFT 4 |
112 | 2c0262af | bellard | #define HF_SS32_SHIFT 5 |
113 | 2c0262af | bellard | /* zero base for DS, ES and SS */
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114 | 2c0262af | bellard | #define HF_ADDSEG_SHIFT 6 |
115 | 65262d57 | bellard | /* copy of CR0.PE (protected mode) */
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116 | 65262d57 | bellard | #define HF_PE_SHIFT 7 |
117 | 65262d57 | bellard | #define HF_TF_SHIFT 8 /* must be same as eflags */ |
118 | 7eee2a50 | bellard | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
119 | 7eee2a50 | bellard | #define HF_EM_SHIFT 10 |
120 | 7eee2a50 | bellard | #define HF_TS_SHIFT 11 |
121 | 65262d57 | bellard | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
122 | 65262d57 | bellard | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
123 | 2c0262af | bellard | |
124 | 2c0262af | bellard | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) |
125 | 2c0262af | bellard | #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) |
126 | 2c0262af | bellard | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
127 | 2c0262af | bellard | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) |
128 | 2c0262af | bellard | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) |
129 | 2c0262af | bellard | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) |
130 | 65262d57 | bellard | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
131 | 58fe2f10 | bellard | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
132 | 7eee2a50 | bellard | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
133 | 7eee2a50 | bellard | #define HF_EM_MASK (1 << HF_EM_SHIFT) |
134 | 7eee2a50 | bellard | #define HF_TS_MASK (1 << HF_TS_SHIFT) |
135 | 2c0262af | bellard | |
136 | 2c0262af | bellard | #define CR0_PE_MASK (1 << 0) |
137 | 7eee2a50 | bellard | #define CR0_MP_MASK (1 << 1) |
138 | 7eee2a50 | bellard | #define CR0_EM_MASK (1 << 2) |
139 | 2c0262af | bellard | #define CR0_TS_MASK (1 << 3) |
140 | 7eee2a50 | bellard | #define CR0_NE_MASK (1 << 5) |
141 | 2c0262af | bellard | #define CR0_WP_MASK (1 << 16) |
142 | 2c0262af | bellard | #define CR0_AM_MASK (1 << 18) |
143 | 2c0262af | bellard | #define CR0_PG_MASK (1 << 31) |
144 | 2c0262af | bellard | |
145 | 2c0262af | bellard | #define CR4_VME_MASK (1 << 0) |
146 | 2c0262af | bellard | #define CR4_PVI_MASK (1 << 1) |
147 | 2c0262af | bellard | #define CR4_TSD_MASK (1 << 2) |
148 | 2c0262af | bellard | #define CR4_DE_MASK (1 << 3) |
149 | 2c0262af | bellard | #define CR4_PSE_MASK (1 << 4) |
150 | 64a595f2 | bellard | #define CR4_PAE_MASK (1 << 5) |
151 | 64a595f2 | bellard | #define CR4_PGE_MASK (1 << 7) |
152 | 2c0262af | bellard | |
153 | 2c0262af | bellard | #define PG_PRESENT_BIT 0 |
154 | 2c0262af | bellard | #define PG_RW_BIT 1 |
155 | 2c0262af | bellard | #define PG_USER_BIT 2 |
156 | 2c0262af | bellard | #define PG_PWT_BIT 3 |
157 | 2c0262af | bellard | #define PG_PCD_BIT 4 |
158 | 2c0262af | bellard | #define PG_ACCESSED_BIT 5 |
159 | 2c0262af | bellard | #define PG_DIRTY_BIT 6 |
160 | 2c0262af | bellard | #define PG_PSE_BIT 7 |
161 | 2c0262af | bellard | #define PG_GLOBAL_BIT 8 |
162 | 2c0262af | bellard | |
163 | 2c0262af | bellard | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) |
164 | 2c0262af | bellard | #define PG_RW_MASK (1 << PG_RW_BIT) |
165 | 2c0262af | bellard | #define PG_USER_MASK (1 << PG_USER_BIT) |
166 | 2c0262af | bellard | #define PG_PWT_MASK (1 << PG_PWT_BIT) |
167 | 2c0262af | bellard | #define PG_PCD_MASK (1 << PG_PCD_BIT) |
168 | 2c0262af | bellard | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
169 | 2c0262af | bellard | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
170 | 2c0262af | bellard | #define PG_PSE_MASK (1 << PG_PSE_BIT) |
171 | 2c0262af | bellard | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) |
172 | 2c0262af | bellard | |
173 | 2c0262af | bellard | #define PG_ERROR_W_BIT 1 |
174 | 2c0262af | bellard | |
175 | 2c0262af | bellard | #define PG_ERROR_P_MASK 0x01 |
176 | 2c0262af | bellard | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) |
177 | 2c0262af | bellard | #define PG_ERROR_U_MASK 0x04 |
178 | 2c0262af | bellard | #define PG_ERROR_RSVD_MASK 0x08 |
179 | 2c0262af | bellard | |
180 | 2c0262af | bellard | #define MSR_IA32_APICBASE 0x1b |
181 | 2c0262af | bellard | #define MSR_IA32_APICBASE_BSP (1<<8) |
182 | 2c0262af | bellard | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
183 | 2c0262af | bellard | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
184 | 2c0262af | bellard | |
185 | 2c0262af | bellard | #define MSR_IA32_SYSENTER_CS 0x174 |
186 | 2c0262af | bellard | #define MSR_IA32_SYSENTER_ESP 0x175 |
187 | 2c0262af | bellard | #define MSR_IA32_SYSENTER_EIP 0x176 |
188 | 2c0262af | bellard | |
189 | 2c0262af | bellard | #define EXCP00_DIVZ 0 |
190 | 2c0262af | bellard | #define EXCP01_SSTP 1 |
191 | 2c0262af | bellard | #define EXCP02_NMI 2 |
192 | 2c0262af | bellard | #define EXCP03_INT3 3 |
193 | 2c0262af | bellard | #define EXCP04_INTO 4 |
194 | 2c0262af | bellard | #define EXCP05_BOUND 5 |
195 | 2c0262af | bellard | #define EXCP06_ILLOP 6 |
196 | 2c0262af | bellard | #define EXCP07_PREX 7 |
197 | 2c0262af | bellard | #define EXCP08_DBLE 8 |
198 | 2c0262af | bellard | #define EXCP09_XERR 9 |
199 | 2c0262af | bellard | #define EXCP0A_TSS 10 |
200 | 2c0262af | bellard | #define EXCP0B_NOSEG 11 |
201 | 2c0262af | bellard | #define EXCP0C_STACK 12 |
202 | 2c0262af | bellard | #define EXCP0D_GPF 13 |
203 | 2c0262af | bellard | #define EXCP0E_PAGE 14 |
204 | 2c0262af | bellard | #define EXCP10_COPR 16 |
205 | 2c0262af | bellard | #define EXCP11_ALGN 17 |
206 | 2c0262af | bellard | #define EXCP12_MCHK 18 |
207 | 2c0262af | bellard | |
208 | 2c0262af | bellard | enum {
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209 | 2c0262af | bellard | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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210 | 2c0262af | bellard | CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
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211 | d36cd60e | bellard | |
212 | d36cd60e | bellard | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
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213 | d36cd60e | bellard | CC_OP_MULW, |
214 | d36cd60e | bellard | CC_OP_MULL, |
215 | 2c0262af | bellard | |
216 | 2c0262af | bellard | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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217 | 2c0262af | bellard | CC_OP_ADDW, |
218 | 2c0262af | bellard | CC_OP_ADDL, |
219 | 2c0262af | bellard | |
220 | 2c0262af | bellard | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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221 | 2c0262af | bellard | CC_OP_ADCW, |
222 | 2c0262af | bellard | CC_OP_ADCL, |
223 | 2c0262af | bellard | |
224 | 2c0262af | bellard | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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225 | 2c0262af | bellard | CC_OP_SUBW, |
226 | 2c0262af | bellard | CC_OP_SUBL, |
227 | 2c0262af | bellard | |
228 | 2c0262af | bellard | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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229 | 2c0262af | bellard | CC_OP_SBBW, |
230 | 2c0262af | bellard | CC_OP_SBBL, |
231 | 2c0262af | bellard | |
232 | 2c0262af | bellard | CC_OP_LOGICB, /* modify all flags, CC_DST = res */
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233 | 2c0262af | bellard | CC_OP_LOGICW, |
234 | 2c0262af | bellard | CC_OP_LOGICL, |
235 | 2c0262af | bellard | |
236 | 2c0262af | bellard | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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237 | 2c0262af | bellard | CC_OP_INCW, |
238 | 2c0262af | bellard | CC_OP_INCL, |
239 | 2c0262af | bellard | |
240 | 2c0262af | bellard | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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241 | 2c0262af | bellard | CC_OP_DECW, |
242 | 2c0262af | bellard | CC_OP_DECL, |
243 | 2c0262af | bellard | |
244 | 2c0262af | bellard | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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245 | 2c0262af | bellard | CC_OP_SHLW, |
246 | 2c0262af | bellard | CC_OP_SHLL, |
247 | 2c0262af | bellard | |
248 | 2c0262af | bellard | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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249 | 2c0262af | bellard | CC_OP_SARW, |
250 | 2c0262af | bellard | CC_OP_SARL, |
251 | 2c0262af | bellard | |
252 | 2c0262af | bellard | CC_OP_NB, |
253 | 2c0262af | bellard | }; |
254 | 2c0262af | bellard | |
255 | 2c0262af | bellard | #ifdef __i386__
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256 | 2c0262af | bellard | #define USE_X86LDOUBLE
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257 | 2c0262af | bellard | #endif
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258 | 2c0262af | bellard | |
259 | 2c0262af | bellard | #ifdef USE_X86LDOUBLE
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260 | 2c0262af | bellard | typedef long double CPU86_LDouble; |
261 | 2c0262af | bellard | #else
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262 | 2c0262af | bellard | typedef double CPU86_LDouble; |
263 | 2c0262af | bellard | #endif
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264 | 2c0262af | bellard | |
265 | 2c0262af | bellard | typedef struct SegmentCache { |
266 | 2c0262af | bellard | uint32_t selector; |
267 | 2c0262af | bellard | uint8_t *base; |
268 | 2c0262af | bellard | uint32_t limit; |
269 | 2c0262af | bellard | uint32_t flags; |
270 | 2c0262af | bellard | } SegmentCache; |
271 | 2c0262af | bellard | |
272 | 2c0262af | bellard | typedef struct CPUX86State { |
273 | 2c0262af | bellard | /* standard registers */
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274 | 2c0262af | bellard | uint32_t regs[8];
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275 | 2c0262af | bellard | uint32_t eip; |
276 | 2c0262af | bellard | uint32_t eflags; /* eflags register. During CPU emulation, CC
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277 | 2c0262af | bellard | flags and DF are set to zero because they are
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278 | 2c0262af | bellard | stored elsewhere */
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279 | 2c0262af | bellard | |
280 | 2c0262af | bellard | /* emulator internal eflags handling */
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281 | 2c0262af | bellard | uint32_t cc_src; |
282 | 2c0262af | bellard | uint32_t cc_dst; |
283 | 2c0262af | bellard | uint32_t cc_op; |
284 | 2c0262af | bellard | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
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285 | 2c0262af | bellard | uint32_t hflags; /* hidden flags, see HF_xxx constants */
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286 | 2c0262af | bellard | |
287 | 2c0262af | bellard | /* FPU state */
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288 | 2c0262af | bellard | unsigned int fpstt; /* top of stack index */ |
289 | 2c0262af | bellard | unsigned int fpus; |
290 | 2c0262af | bellard | unsigned int fpuc; |
291 | 2c0262af | bellard | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
292 | 7eee2a50 | bellard | CPU86_LDouble fpregs[8];
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293 | 2c0262af | bellard | |
294 | 2c0262af | bellard | /* emulator internal variables */
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295 | 2c0262af | bellard | CPU86_LDouble ft0; |
296 | 2c0262af | bellard | union {
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297 | 2c0262af | bellard | float f;
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298 | 2c0262af | bellard | double d;
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299 | 2c0262af | bellard | int i32;
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300 | 2c0262af | bellard | int64_t i64; |
301 | 2c0262af | bellard | } fp_convert; |
302 | 2c0262af | bellard | |
303 | 2c0262af | bellard | /* segments */
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304 | 2c0262af | bellard | SegmentCache segs[6]; /* selector values */ |
305 | 2c0262af | bellard | SegmentCache ldt; |
306 | 2c0262af | bellard | SegmentCache tr; |
307 | 2c0262af | bellard | SegmentCache gdt; /* only base and limit are used */
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308 | 2c0262af | bellard | SegmentCache idt; /* only base and limit are used */
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309 | 2c0262af | bellard | |
310 | 2c0262af | bellard | /* sysenter registers */
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311 | 2c0262af | bellard | uint32_t sysenter_cs; |
312 | 2c0262af | bellard | uint32_t sysenter_esp; |
313 | 2c0262af | bellard | uint32_t sysenter_eip; |
314 | 58fe2f10 | bellard | |
315 | 58fe2f10 | bellard | /* temporary data for USE_CODE_COPY mode */
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316 | 7eee2a50 | bellard | #ifdef USE_CODE_COPY
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317 | 58fe2f10 | bellard | uint32_t tmp0; |
318 | 58fe2f10 | bellard | uint32_t saved_esp; |
319 | 7eee2a50 | bellard | int native_fp_regs; /* if true, the FPU state is in the native CPU regs */ |
320 | 7eee2a50 | bellard | #endif
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321 | 2c0262af | bellard | |
322 | 2c0262af | bellard | /* exception/interrupt handling */
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323 | 2c0262af | bellard | jmp_buf jmp_env; |
324 | 2c0262af | bellard | int exception_index;
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325 | 2c0262af | bellard | int error_code;
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326 | 2c0262af | bellard | int exception_is_int;
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327 | 2c0262af | bellard | int exception_next_eip;
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328 | 2c0262af | bellard | struct TranslationBlock *current_tb; /* currently executing TB */ |
329 | 2c0262af | bellard | uint32_t cr[5]; /* NOTE: cr1 is unused */ |
330 | 2c0262af | bellard | uint32_t dr[8]; /* debug registers */ |
331 | 2c0262af | bellard | int interrupt_request;
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332 | 2c0262af | bellard | int user_mode_only; /* user mode only simulation */ |
333 | 2c0262af | bellard | |
334 | 2c0262af | bellard | /* soft mmu support */
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335 | 64a595f2 | bellard | uint32_t a20_mask; |
336 | 2c0262af | bellard | /* 0 = kernel, 1 = user */
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337 | 2c0262af | bellard | CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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338 | 2c0262af | bellard | CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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339 | 2c0262af | bellard | |
340 | 2c0262af | bellard | /* ice debug support */
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341 | 2c0262af | bellard | uint32_t breakpoints[MAX_BREAKPOINTS]; |
342 | 2c0262af | bellard | int nb_breakpoints;
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343 | 2c0262af | bellard | int singlestep_enabled;
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344 | 2c0262af | bellard | |
345 | 2c0262af | bellard | /* user data */
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346 | 2c0262af | bellard | void *opaque;
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347 | 2c0262af | bellard | } CPUX86State; |
348 | 2c0262af | bellard | |
349 | 2c0262af | bellard | #ifndef IN_OP_I386
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350 | 2c0262af | bellard | void cpu_x86_outb(CPUX86State *env, int addr, int val); |
351 | 2c0262af | bellard | void cpu_x86_outw(CPUX86State *env, int addr, int val); |
352 | 2c0262af | bellard | void cpu_x86_outl(CPUX86State *env, int addr, int val); |
353 | 2c0262af | bellard | int cpu_x86_inb(CPUX86State *env, int addr); |
354 | 2c0262af | bellard | int cpu_x86_inw(CPUX86State *env, int addr); |
355 | 2c0262af | bellard | int cpu_x86_inl(CPUX86State *env, int addr); |
356 | 2c0262af | bellard | #endif
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357 | 2c0262af | bellard | |
358 | 2c0262af | bellard | CPUX86State *cpu_x86_init(void);
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359 | 2c0262af | bellard | int cpu_x86_exec(CPUX86State *s);
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360 | 2c0262af | bellard | void cpu_x86_close(CPUX86State *s);
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361 | 2c0262af | bellard | int cpu_x86_get_pic_interrupt(CPUX86State *s);
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362 | 2c0262af | bellard | |
363 | 2c0262af | bellard | /* this function must always be used to load data in the segment
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364 | 2c0262af | bellard | cache: it synchronizes the hflags with the segment cache values */
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365 | 2c0262af | bellard | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
366 | 2c0262af | bellard | int seg_reg, unsigned int selector, |
367 | 2c0262af | bellard | uint8_t *base, unsigned int limit, |
368 | 2c0262af | bellard | unsigned int flags) |
369 | 2c0262af | bellard | { |
370 | 2c0262af | bellard | SegmentCache *sc; |
371 | 2c0262af | bellard | unsigned int new_hflags; |
372 | 2c0262af | bellard | |
373 | 2c0262af | bellard | sc = &env->segs[seg_reg]; |
374 | 2c0262af | bellard | sc->selector = selector; |
375 | 2c0262af | bellard | sc->base = base; |
376 | 2c0262af | bellard | sc->limit = limit; |
377 | 2c0262af | bellard | sc->flags = flags; |
378 | 2c0262af | bellard | |
379 | 2c0262af | bellard | /* update the hidden flags */
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380 | 2c0262af | bellard | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) |
381 | 2c0262af | bellard | >> (DESC_B_SHIFT - HF_CS32_SHIFT); |
382 | 2c0262af | bellard | new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK) |
383 | 2c0262af | bellard | >> (DESC_B_SHIFT - HF_SS32_SHIFT); |
384 | 2c0262af | bellard | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
385 | 2c0262af | bellard | /* XXX: try to avoid this test. The problem comes from the
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386 | 2c0262af | bellard | fact that is real mode or vm86 mode we only modify the
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387 | 2c0262af | bellard | 'base' and 'selector' fields of the segment cache to go
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388 | 2c0262af | bellard | faster. A solution may be to force addseg to one in
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389 | 2c0262af | bellard | translate-i386.c. */
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390 | 2c0262af | bellard | new_hflags |= HF_ADDSEG_MASK; |
391 | 2c0262af | bellard | } else {
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392 | 2c0262af | bellard | new_hflags |= (((unsigned long)env->segs[R_DS].base | |
393 | 2c0262af | bellard | (unsigned long)env->segs[R_ES].base | |
394 | 2c0262af | bellard | (unsigned long)env->segs[R_SS].base) != 0) << |
395 | 2c0262af | bellard | HF_ADDSEG_SHIFT; |
396 | 2c0262af | bellard | } |
397 | 2c0262af | bellard | env->hflags = (env->hflags & |
398 | 2c0262af | bellard | ~(HF_CS32_MASK | HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
399 | 2c0262af | bellard | } |
400 | 2c0262af | bellard | |
401 | 2c0262af | bellard | /* wrapper, just in case memory mappings must be changed */
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402 | 2c0262af | bellard | static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) |
403 | 2c0262af | bellard | { |
404 | 2c0262af | bellard | #if HF_CPL_MASK == 3 |
405 | 2c0262af | bellard | s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; |
406 | 2c0262af | bellard | #else
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407 | 2c0262af | bellard | #error HF_CPL_MASK is hardcoded
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408 | 2c0262af | bellard | #endif
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409 | 2c0262af | bellard | } |
410 | 2c0262af | bellard | |
411 | 2c0262af | bellard | /* the following helpers are only usable in user mode simulation as
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412 | 2c0262af | bellard | they can trigger unexpected exceptions */
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413 | 2c0262af | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); |
414 | 2c0262af | bellard | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32); |
415 | 2c0262af | bellard | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32); |
416 | 2c0262af | bellard | |
417 | 2c0262af | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
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418 | 2c0262af | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
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419 | 2c0262af | bellard | is returned if the signal was handled by the virtual CPU. */
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420 | 2c0262af | bellard | struct siginfo;
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421 | 2c0262af | bellard | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
422 | 2c0262af | bellard | void *puc);
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423 | 461c0471 | bellard | void cpu_x86_set_a20(CPUX86State *env, int a20_state); |
424 | 2c0262af | bellard | |
425 | 64a595f2 | bellard | /* will be suppressed */
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426 | 64a595f2 | bellard | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
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427 | 64a595f2 | bellard | |
428 | 2c0262af | bellard | /* used to debug */
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429 | 2c0262af | bellard | #define X86_DUMP_FPU 0x0001 /* dump FPU state too */ |
430 | 2c0262af | bellard | #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ |
431 | 2c0262af | bellard | void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags); |
432 | 2c0262af | bellard | |
433 | 2c0262af | bellard | #define TARGET_PAGE_BITS 12 |
434 | 2c0262af | bellard | #include "cpu-all.h" |
435 | 2c0262af | bellard | |
436 | 2c0262af | bellard | #endif /* CPU_I386_H */ |